Uploaded by Harish Sv

Assignment CIE 2

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Assignment 2
1. Draw the circuit schematic and stick diagram of CMOS 2 input Logic Gate (NAND
NOR, EX-OR, EX-NOR) or Any circuit equations may be asked
2. Explain Briefly λ based design rules for wire and transistor (nMOS, pMOS, CMOS)
3. Explain briefly the circuit of inverting and non-inverting super buffer
4. What are the most commonly used scaling models? Provide scaling factor for
i. Power dissipation per gate
ii. Current density
iii. Channel resistance Ron
iv. Parasitic capacitance Cx
v. Maximum operating frequency
vi. Saturation current
vii. Gate delay
viii. Gate Area
5. What are the general considerations to be followed in designing a sub system?
6. Explain the design steps for 4 bit adder
7. Design a 4-bit ALU to implement addition, subtraction, EXOR, EXNOR and AND
operation
8. With a neat diagram explain 4X4 Barrel shifter
9. Define Manchester carry chain element
10.Explain the general arrangement of a 4-bit data path processor
11.With a diagram derive an expression for sheet resistance and mention the Rs value
of metal, p and n transistor channels for 5 µm technology
12.Derive an equation for rise time and fall time with respect to CMOS Inverter
13.Discuss the problems associated with VLSI design? How do you reduce them?
14. Discuss different types of bus architecture?
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