EEL6935 RC2 Lab#5
UFID: 33834963
Chong HUANG
NOTE:
Part: Tuning A
Test the Bitdiff Module
Although it already satisfied the requirement of the 250MHz, but I want to push it
further make it will not be out design bottleneck.
The adder has a really long adder chain, I’m using adder trees and reg to pipeline the
calculation and get rid of the FSM and rst, to gain the performance as well as fmax.
My design is using 4 stage adder trees to calculate the total number of the 1, and using
subtract to get the bit diff number.
Using bit shift to do the multiple and minus a fixed number greatly help to reduce the
T_LUT.
Every Stage of the COMB output is connected to a register(s), the design is pipelined.
Results:
The final Fmax can reach the 325MHz, will not be a bottleneck for our design.
Part: Tuning B
Test the bitdiff and Top module.
We already know the bottleneck could not be the bitdiff module, so the tuning target is
the top module.
Same adder problem, the total count has even long adder chain, And for
this design, we notice there is no dependance for the count number output,
and also the total count adder is a individual module which only job is to
output how many data been processed, So it’s an ideal scenario to using
the Multiple cycle path technique let the synthesis tools to allow a longer
setup and hold time.
Using 4 taps let signal have enough time to feedthrough.
Update the SDC file to let the synthesis tools know what we want to do.
Results:
Adder_tree plus enhanced multiplier version still not able to reach the
250MHz.
Multiple cycle path plus enhanced multiplier version can achieve the
281MHz
Part: Tuning C
Squeeze the last Fmax from synthesis tools.
Using a more restrict target and let the synthesis do the maximum
optimize.
Screenshots:
Fmax = 298.6MHz.
Tests passed.