2024/1/4 13:59 Wafer Dicing | Semiconductor Digest (http://semiconductor-digest.com/) (https://www.linkedin.com/groups/4905453/) (https://sst.semiconductor-digest.com/) (https://www.facebook.com/SolidStateTechnology) (https://sst.semiconductor-digest.com/feed/) Wafer Dicing Step 1 To achieve maximum wafer dicing process yield and productivity, there is an integral need for greater accuracy and new control capabilities. ILAN WEISSHAUS, Ph.D., DIANNE SHI, Ph.D. UDI EFRAT Dicing throughput is dependent on the rate at which the wafer substrate is fed into the cutting blade. The major limitations on feed rate are the formation of chipping and yielding of the blade. To determine the maximum feed rate without exceeding these limitations, a special monitoring method is recommended. The parameter monitored is the torque applied on the blade. Another tool crucial for process optimization is the Designed Experiment or Design of Experiment (DOE) method. DOE is an alternative to the trial and error loop often used for process optimization. This article explains the advantages of using DOE in combination with torque data to determine the major factors affecting the wafer dicing process. The Mechanism of Dicing During the silicon wafer dicing process, the silicon wafer is divided into single units, or dice (Figure 1).1 A rotating abrasive disc (blade) performs the dicing, while a spindle at high speed, 30,000 to 60,000 rpm (linear speeds of 83 to 175 m/sec), rotates the blade. The blade is made of abrasive grit, diamonds, that are embedded in an electroplated nickel matrix, the binder. During the separation of dice, the blade crushes the substrate material (wafer) and removes the created debris simultaneously. Material removal occurs along dedicated dicing lines (streets) between the active areas of the dice. When the dicing blade moves along these streets, a groove is formed in the substrate material. The groove width (kerf) is proportional to the thickness of the blade. The throughput of the dicing process is measured by the number of wafers diced per hour. The speed at which the blade advances along the substrate, the feed rate, actually determines the throughput – the higher the feed rate, the higher the throughput. To achieve maximum dicing yield and productivity, it is important to operate the dicing system at the highest throughput possible within the process quality limits. The optimal selection of the process parameters discussed previously enables this objective. In other words, the optimal process is the one that employs the highest possible feed rate without decreasing cut accuracy, creating intolerable chipping, breaking the blade or shortening the blade`s life. Cut Quality Dicing does not add value to the finished device; therefore, the quality of the dicing process is measured by the yield loss it may cause. Potential dicing yield loss factors include cut misplacement, cleanliness and chipping.1 Cut Placement Accuracy https://sst.semiconductor-digest.com/2000/01/wafer-dicing/#:~:text=Back-side chipping (BSC),micro-cracks in the substrate. 1/5 2024/1/4 13:59 Wafer Dicing | Semiconductor Digest Cut placement accuracy is a prerequisite for high dicing yield, especially for narrow-street wafers. While most common dicing systems are adequate for streets 70 to 100 µm and wider, the narrower street widths commonly encountered during wafer dicing requires the capability to place each cut within several µm of the street center. This necessitates high indexing axis accuracy, high optical magnification and advanced alignment algorithms. A common recommendation when dicing wafers with narrow streets is to select the thinnest blade possible. Very thin blades (20 µm or less) are significantly weaker and more susceptible to premature breakage and wear. As a result, their life expectancy and process stability are inferior to thicker blades. The recommended blade thickness for 50 to 76 µm streets is 20 to 30 µm. The following formula associates street width capability with cut placement accuracy, blade width, chipping and required process capability factor. Click here to enlarge image W = street width, P = cut placement factor, K = kerf width factors, s = standard deviations. Cleanliness After dicing, silicon dust residue can be found on the terminal pads. This dust may reduce the strength and reliability of wire bonds to these pads. Silicon dust that settles on the pad during dicing may be hard to remove in the subsequent high-pressure cleaning operation. Proper blade cooling and coolant nozzle adjustment can prevent this problem. Chipping Chipping can occur on the front (top) or back (bottom) surface of the wafer. Front-side chipping becomes a yield concern when chips approach the active area of the die. Front-side chipping is predominantly dependent on blade grit, coolant flow and feed rate. Back-side chipping (BSC) occurs on the bottom surface of the wafer, as micro-cracks propagate away from the bottom of the cut and join together into chip out. The interaction of the blade with the substrate creates a network of micro-cracks in the substrate. When these micro-cracks join, they cause particles of the substrate to loosen and be removed. BSC becomes a yield issue when micro-cracks exceed a certain length, which may increase the sensitivity of the devices to thermal cycling and lower their reliability. Dice intended for flip chip packages are even more sensitive. When packaging these dice, the back side of the die is exposed to the molding material. If the back-side edges of the die are cracked and chipped, the molding may be imperfect, including air bubbles near the chipping. During the packaging process, these bubbles may cause mold cracking, which can reduce yield. Back-side chipping is more pronounced in polyimide-coated wafers where there are heavy metal layers in the streets, or where heavy back-grinding has produced high tensile residual stress at the bottom of the wafer. The wafer is a given in most assembly lines; therefore, the tools available to the process engineer for controlling back-side chipping are limited to blade selection and process parameter optimization. Process Optimization Optimizing a dicing process entails achieving the highest possible throughput with minimal chipping on the die edges. To reach maximum throughput, it is necessary to use the highest possible feed rate. The feed rate is always dependent on the spindle speed and the blade type. Combining these parameters and ensuring optimum throughput is the challenge. It has been shown that all process parameters correlate with blade torque (Table 1).2 The appearance of chipping, especially BSC, also correlates with blade torque (Figure 2). For each set of process parameters, there is a torque value limit. Dicing quality deteriorates and back-side chipping appears above the limit. By measuring the torque on-line, the other process parameters can be set in such a way that the torque limit will not be exceeded and maximum feed rate will be obtained without chip formation. https://sst.semiconductor-digest.com/2000/01/wafer-dicing/#:~:text=Back-side chipping (BSC),micro-cracks in the substrate. 2/5 2024/1/4 13:59 Wafer Dicing | Semiconductor Digest Many experimental variables have to be considered during process optimization. Testing each variable separately is tedious and consumes many wafers. The DOE method is used to reduce the number of tests needed and to provide the combined effect of several parameters. The DOE is a statistical method for evaluation of multi-variable processes. All experimental variables are arranged in a matrix and tested in at least two settings. The outcome of the tests is measured and recorded. Analysis of variance (ANOVA) is done on the measured test results. The DOE tests and analysis reveal the major factors that affect the response (e.g., back-side chipping), as well as the effect of each factor when it increases or decreases. Blade Selection In general, the optimization process should start with blade selection, and process parameter optimization should follow. The blade dimensions are limited by wafer demands; required kerf width determines blade thickness. The thickness of the wafer determines the blade height. Other parameters to choose are blade bonding material hardness, diamond size and concentration, and the shape of the blade edge and hub. During blade selection, two factors should be considered: blade life and cut quality. Blade life is an important factor in the cost of ownership of a dicing system. Blade life depends on blade bonding material properties. Blades with softer bond material typically provide better cut quality, especially regarding control of BSC. These blades also wear much faster than hard bonded blades. A trade-off is required between blade wear and cut quality. The chip size should be acceptable and blade life suYcient. Use of DOE can determine this required compromise without numerous trial and error tests. Process Monitoring The common way to continuously monitor the dicing process is on-line, visually inspecting cut position and chipping on the wafer`s top side. However, to monitor the formation of back-side chips, the diced wafer must be inspected off the machine. There also is a way to monitor BSC on-line using torque measurements. The torque applied by the blade when cutting the substrate reflects changes in the different factors that affect the process. Because these changes indicate variation in the process, the torque also reflects conditions that could lead to formation of back-side chipping. When the torque limits are determined, the torque measurements become an eYcient tool for on-line monitoring of BSC. On-line monitoring of blade torque informs the operator of any deviation. It does not require extra inspection time and alerts in real time when there is danger of yield loss. Subsequent off-line inspection should be a complementary tool, used to calibrate the on-line monitor or to verify the causes of deviations it detects. Dressing To ensure high quality process results, new blades have to be dressed before starting production. This step is required to expose the cutting diamonds in the blade surface and condition the blade for continuous work without dramatic changes in cut quality. Dressing consists of cutting a certain length of material, starting at low feed rate and increasing the rate until the target is reached (Figure 3). The duration of the dressing process is usually based on post-dicing inspection results. Because the mechanism of this process is not fully understood, it tends to be a lengthy procedure that affects productivity. Chipping may result if dressing time is too short. In many cases, extra dressing time is used to maintain a margin of safety. There is a good method for controlling dressing time that can increase productivity. Blade torque measurements provide an on-line method for determining the optimal dressing procedure. If the measured torque values follow a predetermined reference pattern during the dressing procedure, the dressing is being done properly and the point of completion can be determined. Dicing systems offering this capability can significantly increase production time. Process Stability Steady blade torque values indicate a stable process. Once the torque values for a specific process have been established, the other setup parameters should be adjusted to keep these values consistent. Inconsistency of torque values is an indication of deviation in the process because of blade vibration. Blade https://sst.semiconductor-digest.com/2000/01/wafer-dicing/#:~:text=Back-side chipping (BSC),micro-cracks in the substrate. 3/5 2024/1/4 13:59 Wafer Dicing | Semiconductor Digest vibration ends in blade breakage or chipping, and cracking damage to the wafer. System operation at steady torque requires stabilization of the feed rate, spindle speed and coolant flow. The coolant applies drag force on the blade, which makes a significant contribution to the torque. To keep the coolant torque effect steady, the coolant flow is controlled, ensuring steady flow of coolant and no changes in drag force. When the dicing machines have steady coolant flow, and all other parameters are under control, a steady torque is maintained. Any deviations from steady torque, if recorded, are due to uncontrolled factors. These include changes in coolant flow because of nozzle clogging, changes in nozzle adjustment, blade-to-blade variation, blade condition and operator errors. Summary The statistical approach (DOE) to process parameter determination and on-line monitoring of blade torque are required to meet the challenges of the dicing process. These tools upgrade the process development capability by taking into consideration the simultaneous effect of all process parameters. They also ensure process stability by detecting subtle deviations and alerting operators the moment the risk of damage occurs. References 1. Gideon Levinson, “Solving Dicing Problems,” European Semiconductor, Nov/Dec 1994, pp 25-29, and Part II, Jan. 1995, pp.22-23. 2. Udi Efrat and Ilan Weisshaus, “Dicing Yield – Using Blade Torque to Monitor Chipping,” SEMICON Singapore TAP Technical Program, May 1999. ILAN WEISSHAUS, Ph.D., process development manager, can be contacted at Kulicke & Soffa Dicing Systems, P.O. Box 875, Haifa, Israel 31008; (972) 4-8545222; Fax: (972) 4-8550001; E-mail: iweisshaus @kns.dicesys.com. DIANNE SHI, Ph.D., engineering manager, can be contacted at Kulicke & Soffa Dicing Systems (Semitec), 3025 Stender Way, Santa Clara, CA 95054; (408) 496-1092; Fax: (408) 496-1091; Email: shi_dianne@semitec.com. UDI EFRAT, strategic marketing, can be contacted at Kulicke & Soffa Dicing Systems, P.O. Box 875, Haifa, Israel 31008; (972) 4-8545222; Fax: (972) 4-8550001; E-mail: uefrat@kns.dicesys.com. Click here to enlarge image Click here to enlarge image Click here to enlarge image Figure 2. Correlation between torque and back-side chipping. Figure 3. View of a blade cutting edge – after dressing. https://sst.semiconductor-digest.com/2000/01/wafer-dicing/#:~:text=Back-side chipping (BSC),micro-cracks in the substrate. 4/5 2024/1/4 13:59 Wafer Dicing | Semiconductor Digest Click here to enlarge image POST A COMMENT Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share. 4 thoughts on “Wafer Dicing” charles January 19, 2014 at 10:33 pm (https://sst.semiconductor-digest.com/2000/01/wafer-dicing/#comment-84044) Your article states that there can be Si dust on the wafer top side after dicing. This dust can damage the bond pads. Do you have any methods for removing that dust, especially if it is stuck to the wafer such as if there is any adhesive residue on the wafer top side perhaps from a previous step or from tape residue. buddy April 22, 2015 at 11:38 pm (https://sst.semiconductor-digest.com/2000/01/wafer-dicing/#comment-168562) you can use surfactant during wafer cutting. this will reduce the friction between the silicon dust/ contaminants and the surface of the wafer thus it can be wipe off from the wafer easily. hope it helps 🙂 Aaron June 7, 2017 at 7:26 am (https://sst.semiconductor-digest.com/2000/01/wafer-dicing/#comment-188392) For dressing, you stated only “material” as the dressing medium. Is is safe to assume this material be blank Si of similar thickness and grain structure? Corrie Sison July 30, 2017 at 7:17 pm (https://sst.semiconductor-digest.com/2000/01/wafer-dicing/#comment-190374) Hello, Is it necessary to increase the spindle speed if feed speed is increased. Comments are closed. https://sst.semiconductor-digest.com/2000/01/wafer-dicing/#:~:text=Back-side chipping (BSC),micro-cracks in the substrate. 5/5
