North East Frontier Technical University (NEFTU)
PROFESSIONAL ASSESSMENT & CREDITS EVALUATION
SUBJECT: DIGITAL ELECTRONICS
Submitted to:
Submitted by:
Date:
1. Apply De-Morgan’s theorem to simplify A+BC.
̅.B
̅+B
̅ or ̅̅̅̅̅̅
̅
Applying DeMorgan’s theorem states that ̅̅̅̅̅̅̅
A+B= A
A .B = A
A+ BC
̅̅̅̅̅̅̅̅̅̅
̅+B
̅)
A + ̅̅̅̅
BC (Applying De-Morgan’s theorm ̅̅̅̅̅̅
A .B = A
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅
̅.B
̅)
A
+ (B̅ + C̅ ) (Applying De-Morgan’s theorm (A
+B= A
̅.B
̿ . C̿ (Applying B
̿ = 𝐵)
A
̅BC
A
2. Define the term prime implicants and Essential prime implicants.
Prime Implicants:

A group of square or rectangle made up of bunch of adjacent minterms which
is allowed by definition of K-Map are called prime implicants (PI) i.e. all
possible groups formed in K-Map.
Essential prime Implicants:

These are those subcubes (groups) which cover at least one minterm that can’t
be covered by any other prime implicant. Essential prime implicants
(EPI) are those prime implicants which always appear in final solution.
3. If A B are Boolean variables and if A=1 & A+B=0, Find B?
A B A+B
0 0
0
0 1 1
1 0
1
1 1
0 (carry = 1 )
The value of A+B=0 is only true if B = 1
4. Realize F = A’B+AB’ using minimum universal gates.
A'B + AB' = ((A'B)' (AB')')' = [(A + B' ) (A' + B)] '
If (A + B' ) = X and (A' + B) = Y
Then A'B + AB' = (X . Y) ' (1)
X = (A + B') = (A’B)’ = [ 0 + (A’B)]’ = (BB’ + A’B)’ = [B (B’ + A’)]’ = [ B (AB)’]’
.
Y = (A' + B) =(A . B')' = (0 + (A B')) ' = ( AA’ + AB’)’ = [ A (A’ + B’)]’ = [A (AB)’]’
Five nand gates are required.
5. What are universal gates implement AND gate using any one universal gate?
A universal gate is a gate which can implement any Boolean function without need to use any
other gate type. The NAND and NOR gates are universal gates.
A.B = ((A.B)')'
6. What are the advantages of Schottky TTL family?
The Schottky diode is a semiconductor-metal diode that has a low cut-in voltage (forward
bias voltage drop), typically 300 millivolts, compared with 600 mV for other common
semiconductor diodes. It also has a relatively high switching speed. In Schottky TTL the low
cut-in voltage of the diode limits the base-collector voltage to about 400 mV, which prevents
the transistor falling into saturation. This results in faster switching times for the transistors
constructed in this way.
7. Define the term (i). Propagation delay (ii). Power dissipation
Propagation delay: symbolized tpd, is the time required for a digital signal to travel from the
input(s) of a logic gate to the output. It is measured in microseconds (µs), nanoseconds (ns),
or picoseconds (ps), where 1 µs = 10-6 s, 1 ns = 10-9 s, and 1 ps = 10-12 s.
Power dissipation: The power dissipation of a logic gate is the power required by the gate to
operate with 50% duty cycle at a specified frequency and is expressed in mill watts. Fan-in.
The fan-in of a logic gate is defined as the number of inputs that the gate is designed to
handle.
8. Write an expression for borrow and difference in a full Subtractor circuit.
This subtractor circuit executes a subtraction between two bits, which has 3- inputs (X, Y,
and Bin) and two outputs (D and Bout). The expression for Difference is,
D = X’Y’Bin + XY’Bin’+ X’YBin’ + XYBin
The expression for Borrow is,
Bout = X’Y + (X ⊕ Y)’Bin
9. Differentiate a decoder from a Demultiplexer.
Sr.
Key
Decoder
De-Multiplexer
Purpose
A Decoder decodes an encrypted input
A De-Multiplexer routes an
signal to multiple output signals from
input signal to multiple output
one format to another format.
signals.
A Decoder has 'n' input lines and
A De-Multiplexer has single
maximum of 2n output lines.
input, 'n' selection lines and
No.
1
2
Input/ Output
maximum of 2n outputs.
3
Inverse
Decoder's inverse is Encoder.
De-Multiplexer's inverse is
Multiplexer.
Sr.
Key
Decoder
De-Multiplexer
Usage
Decoder is used to detect bits, encoding
De-Multiplexer is used in
of data.
switching, data distribution.
Decoder has no select lines.
De-Multiplexer contains select
No.
4
5
Select Lines
lines.
6
Application
Decoder is heavily used in networking
De-Multiplexer is employed in
applications.
communication systems.
10. Design Half – adder using only NAND gates.
If A and B are inputs, S is sum and C is carry.
S = A’B + AB’
A'B + AB' = ((A'B)' (AB')')' = [(A + B' ) (A' + B)] '
If (A + B' ) = X and (A' + B) = Y
Then A'B + AB' = (X . Y) ' (1)
X = (A + B') = (A’B)’ = [ 0 + (A’B)]’ = (BB’ + A’B)’ = [B (B’ + A’)]’ = [ B (AB)’]’
.
Y = (A' + B) =(A . B')' = (0 + (A B')) ' = ( AA’ + AB’)’ = [ A (A’ + B’)]’ = [A (AB)’]’
C= AB= [(AB)’]’
The minimum number of NAND gates required to design half adder is 5.
11. What is code converter? List their types.
A code converter circuit will convert coded information in one form to a different coding
form. The different code converters are:
BCD-to-seven-segment code converter,
BCD-to-Gray code converter,
BCD-to-excess-3 code converters
BCD to binary
Binary to BCD
Grey code to binary
Binary to Grey code
12. Draw a logic diagram of 1 to 4 data distributor
The data distributor, known more commonly as a Demultiplexer or “Demux” for short, is the
exact opposite of the Multiplexer we saw in the previous tutorial. The demultiplexer takes
one single input data line and then switches it to any one of a number of individual output
lines one at a time. The demultiplexer converts a serial data signal at the input to a parallel
data at its output lines as shown below.
13. Express Gray code 10111 into binary numbers.
B4 = G4 =1
B3 = B4 ⊕ G3 =1
B2 = B3 ⊕ G2 =0
B1 = B2 ⊕ G1=1
B0 = B1 ⊕ G0 =0
Thus, the binary code is 11010
14. Implement full adder using multiplexer.
Step 1: Truth table of full adder is written as shown below
Step 2: Write the design tables for sum and carry outputs
Step 3: The full adder using 4:1 multiplexer
15. What is race around condition? How do you eliminate it?
Race condition occurs in RS flip-flop. When the S and R inputs of an SR flip flop is at logical
1 and then the input is changed to any other condition, then the output becomes unpredictable
and this is called the race around condition. Race around condition can be eliminated using
the master-slave flip-flop. Master-Slave flip-flop is the cascaded combination of two flipflops among which the first is designated as master flip-flop while the next is called slave
flip-flop.
16. Mention any two differences between the edge triggering and level triggering.
The main difference between edge and level triggering is that in edge triggering, the output of
the sequential circuit changes during the high voltage period or low voltage period while, in
level triggering, the output of the sequential circuit changes during transits from the high
voltage to low voltage or low voltage to high voltage.
Another difference between edge and level triggering is that the flip flops will work
according to edge triggering, whereas Latches work according to level triggering.
17. What is sequential circuit? Give some example.
A Sequential logic circuit is a form of the binary circuit; its design employs one or more
inputs and one or more outputs, whose states are related to some definite rules that depend on
previous states. Both the inputs and outputs can reach either of the two states: logic 0 (low) or
logic 1 (high). In these circuits, their output depends, not only on the combination of the logic
states at its inputs but moreover on the logic states that existed previously. In other words,
their output depends on a sequence of the events occurring at the circuit inputs. Examples of
such circuits include clocks, flip-flops, bi-stables, counters, memories, and registers. The
actions of the circuits depend on the range of basic sub-circuits.
18. Convert transparent flip flop into a JK flip flop.
D-Flip Flop is called transparent. Because D-FF has one input and one output. When the
input enable is high we can write to FF and when the output enable is high then we can read
the data. One D-FF is used to store one bit data. And also input and output of D-FF is same.
So the D-FF is called transparent.
The given D flip-flop can be converted into a JK flip-flop by using a D-to-JK conversion
table as shown
Following this, we need to simplify the expressions for the D-input in terms of J, K, and Qn.
We will again employ the K-map technique.
The resultant system would be as shown below:
19. Differentiate Asynchronous and Modulus counter
Asynchronous counters are those whose output is free from the clock signal. Because the flip
flops in asynchronous counters are supplied with different clock signals, there may be delay
in producing output.
Modulus Counters, or simply MOD counters, are defined based on the number of states
that the counter will sequence through before returning back to its original value.
20. How the memories are classified.
Computer memory is of two basic type – Primary memory (RAM and ROM) and Secondary
memory (hard drive, CD, etc.). Random Access Memory (RAM) is primary-volatile memory
and Read Only Memory (ROM) is primary-non-volatile memory. It is also called as read
write memory or the main memory or the primary memory.
21. What is an EPROM?
EPROM stands for Erasable-Programmable ROM. The ICs hold code, often an auxiliary
program such as an application, utility or game which can be loaded immediately on start up.
Sometimes they were used to house the bootstrap code and/or the BASIC interpreter in old
microcomputers although this function was often more commonly provided by mask ROMS.
Mask ROMS have embedded code that can't be changed. EPROMS also hold code but can be
erased and reprogrammed. Once reprogrammed (or "burned"), they can hold their data for
many years.
22. Compare and contrast static RAM and dynamic RAM
SRAM has lower access time, and is faster whereas DRAM has a higher access time and is
slower compared to SRAM. SRAM uses transistors and latches while DRAM uses capacitors
and very few transistors. SRAM is in the form of on-chip memory, but DRAM has the
characteristics of off-chip memory.
23. What is PLD? List their types.
A programmable logic device (PLD) is an electronic component used to build reconfigurable
digital circuits. Unlike integrated circuits (IC) which consist of logic gates and have a fixed
function, a PLD has an undefined function at the time of manufacture. There are three
fundamental types of standard PLDs: PROM, PAL, and PLA. A fourth type of PLD, which is
discussed later, is the Complex Programmable Logic Device (CPLD), e.g., Field
Programmable Gate Array (FPGA). A typical PLD may have hundreds to millions of gates.
24. Explain write operation with an example.
A write is the transfer of a piece of data to some destination. The destination might be RAM when a program, for example, sets the value of a variable. It might be a peripheral device, for
example a hard disk, a flash drive, or a USB port. The destination might be a control element
of a piece of hardware, for example control registers in a GPU.
25. Distinguish between PAL and PLA.
In PLA or Programmable Logic Array, there are massive functions can be implemented.
Whereas in PAL or Programmable Array Logic, there is finite functions can be
implemented.The distinction between PLA and PAL is that, PAL have programmable AND
array and fixed or array. On the other hand, PLA have programmable AND array and
programming OR array.PLA speed is lower than PAL. While PAL’s speed is higher than
PLA.
26. Which memory is called volatile? Why?
Volatile memory is storage device that only maintains its data while the device is powered.
Most RAM (random access memory) used for primary storage in personal computers is
volatile memory. RAM is much faster to read from and write to than the other kinds of
storage in a computer, such as the hard disk or removable media. However, the data in RAM
stays there only while the computer is running; when the computer is shut off, RAM loses its
data.
27. Write the advantages of EPROM over a PROM.
The advantages of EPROM are

Ability to re-program EPROMs makes it essential part in software development and
testing in spite of higher cost compare to PROMs.

It retains memory even without power. Hence no external memory is required.

It is re-programmable as mentioned above.

It is very cost effective.
28. Compare the features of PROM, PAL and PLA
PROM: A PROM has a fixed AND array but a programmable OR array. When AND array is
fixed that means we can only get certain min-terms. As OR can be programmable, we can
combine them in whatever combinations we like. So not all but a few logic functions can be
implemented,
PLA: This is very flexible as both AND and OR array can be programmed to our wish. Using
this we can implement whichever logic function we need provided we have required number
of AND and OR gates. But, here the hardware is complex and expensive. Logic functions can
be easily implemented using PLA than with PAL and PROM.
PAL: Here OR array is fixed and AND array is programmable. So here the min terms can be
made as we wish, The hardware is less sophisticated than PLA. So one needs to write the
logic function in an optimised way to get the most of it. This is used more often than PLA.
29. Differentiate synchronous and asynchronous sequential circuits?
Synchronous sequential circuits are digital circuits governed by clock signals. Asynchronous
sequential circuits are digital circuits that are not driven by clock. They can be called as selftimed circuits. Synchronous circuits are used in counters, shift registers, memory unit.
Synchronous counters are used in digital clocks, digital locking system, keyboard controller,
frequency counter etc. Shift registers are used in data transfer and also to introduce time delay
into circuits. Asynchronous circuits are used in low power and high speed operations. They
are employed in simple microprocessors, digital signal processing units and in
communication systems for email applications, internet access and networking.
30. What are the two types of Asynchronous sequential circuits?
Asynchronous sequential circuit can be classified according to mode as given below:

Fundamental Mode: Only one input bit may be changed at a time and the circuit
must reach a stable state before another input bit is changed. A circuit operated in
fundamental-mode need only worry about one input bit changing at a time.
Multiple-bit input changes are not allowed.

Pulse mode: - More than one input can be change at a time after stable state.
31. Differentiate Moore machine and Mealy machine.
A mealy machine is defined as a machine in theory of computation whose output values are
determined by both its current state and current inputs. In this machine at most one transition
is possible.
A moore machine is defined as a machine in theory of computation whose output values are
determined only by its current state.
32. Define flow table and primitive flow table.
A state transition table with its internal state being symbolized with letters is called flow
table.
Flow table with only one stable state per row is called a primitive flow table. An example of
primitive flow table is shown below
33. Write a Verilog HDL model of a full subtractor circuit.
The full subtractor contains two individual half subtractor circuits, with the outputs of AND
gate ORed together for the final borrow out Bout.
This module is for the OR gate:
module or_gate(a0, b0, c0);
input a0, b0;
output c0;
assign c0 = a0 | b0;
endmodule
This module is for the XOR gate:
module xor_gate(a1, b1, c1);
input a1, b1;
output c1;
assign c1 = a1 ^ b1;
endmodule
This module is for the AND gate:
module and_gate(a2, b2, c2);
input a2, b2;
output c2;
assign c2 = a2 & b2;
endmodule
This module is for the NOT gate:
module not_gate(a3, b3);
input a3;
output b3;
assign b3 = ~ a3;
endmodule
We’ll first construct a half subtractor, as discussed before, and then will use that module of
half subtractor for implementing a full subtractor.
module half_subtractor(a4, b4, c4, d4);
input a4, b4;
output c4, d4;
wire x;
xor_gate u1(a4, b4, c4);
and_gate u2(x, b4, d4);
not_gate u3(a4, x);
endmodule
Using this half_subtractor module for implementing a full subtractor, we need the OR gate
for combining the outputs for the Bout variable.
module full_subtractor(A, B, Bin, D, Bout);
input A, B, Bin;
output D, Bout;
wire p, q, r;
half_subtractor u4(A, B, p, q);
half_subtractor u5(p, Bin, D, r);
or_gate u6(q, r, Bout);
endmodule
34. Define state table and state assignment.
In a general model for sequential circuits, the effect of all previous inputs on the outputs is
represented by a state of the circuit. Thus, the output of the circuit at any time depends upon
its current state and the input. These also determine the next state of the circuit. The
relationship that exists among the inputs, outputs, present states and next states can be
specified by either the state table or the state diagram.
State assignment procedures are concerned with methods for assigning binary values
to states in such a way as to reduce the cost of the combinational circuit that drives the flip
flops. This is particularly helpful when a sequential circuit is viewed from its external inputoutput terminals.
35. What is combinational circuit? Give examples.
Combinational circuit is a circuit without a memory. In this type of logic circuits outputs
depend only on the current inputs.
A combinational circuit consists of input variables (n), logic gates, and output variables (m).
For (n) input variables there are 2n possible combinations of binary input values. For each
possible input combination there is one and only one possible output combination, a
combinational circuit can be describe by (m) Boolean functions one for each output variable.
Each output function expressed in terms of the (n) input variables.
Example: encoder, decoder, multiplexer and demultiplexer.
PART II
1.
Explain the operation of 3 input TTL NAND gate with required diagram & truth
table.
Figure above demonstrates a TTL NAND gate with a totem pole output. The
totem pole
output implies that transistor T4 sits atop T3 in order to give low output impedance. The low
output impedance means a short time constant RC therefore the output can change rapidly
from one state to the other. T1 is a multiple type emitter transistor. Such transistor can be
thought of like a combination of various transistors along with a common collector and base.
In this figure, T1 has 3 emitters thus there can be three inputs A, B, C. The transistor
T2 functions as a phase splitter since the emitter voltage is out of phase along with the
collector voltage. The transistors T3 and T4 by the totem pole output, the capacitance CL
shows the stray capacitance and so on. The diode D is added to make sure that T 4 is cut off
while output is low. The voltage drop of diode D remains the base-emitter junction of
T4 reverse biased therefore only T3 conducts while output is low. The operation can be
described briefly by three conditions as specified below:
Condition 1: At least one input is low (that is, 0). Transistor T1 saturates. Thus, the base
voltage of T2 is almost zero. T2 is cut off and forces T3 to cut off. T4 functions as an emitter
follower and couples a high voltage to load. Output is high (that is Y=1).
Condition 2: Each input is high. The emitter base junctions of T1 are reverse biased. The
collector base junction of T1 is forward biased. Therefore, T1 is in reverse active mode. The
collector current of T1 flows in reverse direction. Because this current is flowing in the base
of T2, the transistors T2 and T3 saturate and then output Y is low.
Condition 3: The circuit is operating under II while one of the inputs becomes low. The
consequent emitter base junction of T1 starts conducting and T1 base voltage drops to a low
value. Thus, T1 is in forward active mode. The high collector current of T1 shifts the stored
charge in T2 and T3 and hence, T2 and T3 go to cut-off and T1 saturates and then output Y
returns to high.
2.
Compare & contrast the features of TTL & CMOS logic families
The advantage of the CMOS over the TTL chips is that the CMOS has a higher density of
logic gates within the same material. TTL chips consume more power as compared to the
power consumed by the CMOS chips even at rest. The power consumption of the CMOS
depends on various factors and is variable. The clock rate is one of the major factors for
power consumption. Higher clock values will result in higher power consumption. When
making the comparisons, a single gate in CMOS chip would consume the 10nW of power
whereas an equivalent gate on the TTL chip will consume approximately 10mW power. The
difference is substantially high and this is why the CMOS chips are always preferred over the
TTL chips. When the design and fabrication are considered, no doubt that the CMOS chips
are very delicate and it is difficult to handle as these are highly susceptible to electrostatic
discharge. A very minute amount of static electricity could cause damage to the CMOS chips.
Thus people often unwillingly damage their chips only by touching the terminals of the
CMOS. Some basic differences between CMOS and TTL are explained below: CMOS
components are generally more expensive when compared to the TTL components. But on
system-level, CMOS chips are less expensive as these are smaller in size as compared to the
TTL chips. There is propagation delays present in both. On average, the propagation delays
of TTL are usually 10ns whereas the propagation delays for the CMOS lies between 20 to
50ns. CMOS has longer rise and fall times thus digital signals are simpler and less expensive
with the CMOS chips. There is a substantial difference in the voltage level range for both.
For TTL it is 4.75 V to 5.25 V while for CMOS it ranges between 0 to 1/3 VDD at a low
level and 2/3VDD to VDD at high levels. CMOS technology is more economical and
preferred more as compared to the TTL logic. The current requirements of the CMOS are low
and thus power consumption is limited. Therefore it is easier for the circuits to be designed
with the best power management. The electromagnetic disruptions CMOS components are
more sensitive as compared to the TTL components CMOS has one other advantage over the
TTL that it has allowed lower noise during the transmission The number of standard loads
that could be connected to the output of the gate under the normal operation that is the fanout is 10 for TTL whereas it is 50 for the CMOS. The number of standard inputs that can be
connected to the gate is the fan in, which is approximately 12-14 for the TTL and for the
CMOS it is 10 only. CMOS circuits have better noise immunity then the TTL circuits The
basic gates which are used in the construction of the TTL are the NAND gate whiles both the
NAND-NOR gates are used in the CMOS circuits.
3.
Design a BCD to Gray code converter. Uses don’t care
Truth Table for BCD to Gray Code is:
BCD input
Gray Code output
A
B
C
D
W
X
Y
Z
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
0
1
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
1
1
0
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
X
X
X
X
X
1
1
X
X
X
X
X
X
Since BCD only ranges from 0 - 9, 10 - 15 become "don't cares"
K map for W
K map for X
K map for Y
K map for Z
Minimized function:
W = A + BC + BD
X = BC’
Y=B+C
Z = A’B’C’D + BCD +AD’ + B’CD’
The PAL wiring can be shown as:
4.
Explain the operation of carry look ahead adder with neat diagram
A carry look-ahead adder (CLA) is an electronic adder used for binary addition. Due to the
quick additions performed, it is also known as a fast adder. The CLA logic uses the concepts
of generating and propagating carries. We can say that the CLA adder is the successor of the
Ripple Carry Adder
Let us consider a full adder. We have the inputs signals A, B, and Cin. If we consider the
addition of these three variables in every possible case, we get a truth table like the one
below.
On analysing the truth table, we see that the Carry is 1 when
1. Either the value of A or B is one, as well as Cin, is 1, or
2. Both A and B have the value 1.
Let us now consider two new variables, Carry Generate (Gi) and Carry Propagate (Pi).
For case 1, we see that an output carry is propagated, when we give an input carry. We will
refer to this with Pi. So, the mathematical expression of Pi can we represented as :
Pi = Ai ⊕ Bi
While considering case 2, we see that an output carry is generated when both inputs, A and
B, are high, regardless of the value of the input carry. We will refer to this output carry as
Gi. Thus, we can mathematically express Gi as :
Gi = Ai . Bi
Originally, for a full adder we have the following equations:
Sum = A⊕B⊕Ci
Carry = Ci(A+B) + AB
Thus, we can rewrite the equations of the full adder in terms of Carry Propagate (Pi) and
Carry Generate (Gi) as :
Sum = Pi ⊕ Ci
Carry = Gi + Pi . Ci
The equations of Sum and Carry can be represented by a logic circuit given below.
Advantages of Carry Look Ahead Adders

CLA Adders generate the carry-in for each full adder simultaneously, by using
simplified equations involving Pi, Gi, and Cin.

This system reduces the propagation delay. This is because the output carry at any
stage is dependent only on the first Carry signal given at the input.

5.
It is the fastest adder when compared to other addition mechanisms.
i). Design and explain the working of an 4-bit Parallel counter
Synchronous counters are called as parallel counter because the clock input of all the
individual flip-flops within the counter are all clocked together at the same time by the same
clock signal
It can be seen above, that the external clock pulses (pulses to be counted) are fed directly to
each of the J-K flip-flops in the counter chain and that both the J and K inputs are all tied
together in toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they
connected HIGH, logic “1” allowing the flip-flop to toggle on every clock pulse. Then the
synchronous counter follows a predetermined sequence of states in response to the common
clock signal, advancing one state for each pulse.
The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-flop FFA,
but the J and K inputs of flip-flops FFC and FFD are driven from separate AND gates which
are also supplied with signals from the input and output of the previous stage. These
additional AND gates generate the required logic for the JK inputs of the next stage.
If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop
outputs (Q) are “HIGH” we can obtain the same counting sequence as with the asynchronous
circuit but without the ripple effect, since each flip-flop in this circuit will be clocked at
exactly the same time.
Then as there is no inherent propagation delay in synchronous counters, because all the
counter stages are triggered in parallel at the same time, the maximum operating frequency of
this type of frequency counter is much higher than that for a similar asynchronous counter
circuit.
ii). Design and working of a BCD ripple counter with timing diagram.
A binary coded decimal (BCD) is a serial digital counter that counts ten digits .And it resets
for every new clock input. As it can go through 10 unique combinations of output, it is also
called as “Decade counter”. A BCD counter can count 0000, 0001, 0010, 1000, 1001, 1010,
1011, 1110, 1111, 0000, and 0001 and so on. A 4 bit binary counter will act as decade
counter by skipping any six outputs out of the 16 (24) outputs.
Truth Table of Decade Counter
The above table describes the counting operation of Decade counter. It represents the count
of circuit for decimal count of input pulses. The NAND gate output is zero when the count
reaches 10 (1010). The count is decoded by the inputs of NAND gate X1 and X3. After count
10, the logic gate NAND will trigger its output from 1 to 0, and it resets all flip flops.
The above figure shows a decade counter constructed with JK flip flop. The J output and K
outputs are connected to logic 1. The clock input of every flip flop is connected to the output
of next flip flop, except the last one. The output of the NAND gate is connected in parallel to
the clear input ‘CLR’ to all the flip flops. This ripple counter can count up to 16 i.e. 24.
Decade Counter Operation: When the Decade counter is at REST, the count is equal to 0000.
This is first stage of the counter cycle. When we connect a clock signal input to the counter
circuit, then the circuit will count the binary sequence. The first clock pulse can make the
circuit to count up to 9 (1001). The next clock pulse advances to count 10 (1010).
Then the ports X1 and X3 will be high. As we know that for high inputs, the NAND gate
output will be low. The NAND gate output is connected to clear input, so it resets all the flip
flop stages in decade counter. This means the pulse after count 9 will again start the count
from count 0.
6.
i).Design and explain the working of an 4-bit Up/Down ripple counter
4-bit Up/Down ripple counter can be designed by connecting the normal and complement
output of flip-flops to two AND gates, D and E, and the output of theses AND gates is fed
to the clock input of the next flip-flop via an OR gate F, as shown in the circuit diagram.
The rest two terminals of the AND gates are connected to an up-down control X. When the
up-down control is at binary 1 state, gates D and F are enabled and gate E is inhibited due
to inverted input. Thus the normal output of each flip-flop is coupled via OR gate F to the
clock input of next flip-flop and the counter counts up. Similarly, when the up-down
control is at binary 0 state, gate D is inhibited and gates E and F are enabled. Hence, the
complement output of each flip-flop is connected to the clock input of next flip-flop and
the counter counts down.
ii). Design and working of a synchronous MOD- 5 counter.
MOD Counters are cascaded counter circuits which count to a set modulus value before
resetting. “m = 5”, so 2n must be greater than 5. As 21 = 2, 22 = 4, 23 = 8, and 8 is greater than
5, then we need a counter with three flip-flops (N = 3) giving us a natural count of 000 to 111
in binary (0 to 7 decimal). MOD 5 Counter has five counter states. The counter design table
for such counter shows the three flip-flop and their states also (0 to 5 states), as in table (a),
the 6 inputs needed for the three flip-flops. The flip-flop inputs needed to step up the counter
from the current to the next state have been worked out along with the assist of the excitation
table illustrated in the table.
Excitation table for counter
K-map simplification
For JC
For KC
Jc=QBQA
KC=1
For JB
JB=QA
For KB
KB=QA
Logic Diagram
Timing Diagram
For JA
JA=QC’
For KA
KA=1
7.
Explain read cycle and write cycle timing parameter with the help of timing
diagram.
Basic parameters to draw timing diagram of 8085 microprocessor are:
i.
Instruction Cycle: Instruction cycle is the total time taken for completing one
instruction execution
ii.
Machine cycle: Machine cycle is the time required to complete one operation such as
accessing either the memory or an I/O device
iii.
T-state: T-state is the time corresponding to one clock period. It is a basic unit. It used
to calculate the time taken for execution of instructions and programs in a processor.
Five control signal to understand timing diagram of 8085 microprocessor are:
i.
IO/ M: IO/ M signal indicate whether I/O or memory operation carried out. A high on
this signal indicates I/O operation while a low indicates memory operation.
ii.
S0 and S1: S0 and S1 indicate the type of machine cycle in progress.
iii.
ALE: ALE is indicates the availability of a valid address on the multiplexed
address/data lines. When it is high act as a address bus and low act as a data bus.
iv.
Rd^: Read is an active low signal. It indicates that data has to read form the selected
memory or i/o device through data bus.
v.
WR^: Write is an active low signal that indicates that data on the data bus is to be
write form the selected memory or i/o device.
In below table show the status of different control signal for different operation.
Memory read and memory write machine cycle
Both the Memory Read and Memory Write machine cycles are 3T states in length. In
Memory Read the contents of R/W memory (including stack also) or ROM are read while in
Memory Write, it stores data into data memory.
As is evident from Fig during T2 and T3 states data from either memory or CPU are
made available in Memory Read or Memory Write machine cycles respectively. The status
signal (IO/ M, S0, S1) states are complementary in nature in Memory Read and Memory
Write cycles. Reading or writing operations mainly performed in T2 cycle.
In T3 of Memory Read, data from data bus are placed into the specified register (A,B, C,
etc.). After that it raises RD so that memory will disabled. While in T3 of Memory Write,
WR^ signal raised for disabling the memory.
Write short notes on PLD, types of PLDs
8.
A programmable logic device (PLD) is an electronic component used to build reconfigurable
digital circuits. Unlike integrated circuits (IC) which consist of logic gates and have a fixed
function, a PLD has an undefined function at the time of manufacture. Before the PLD can
be used in a circuit it must be programmed (reconfigured) by using a specialized program.
There are three kinds of PLDs based on the type of arrays, which has programmable feature.

Programmable Read Only Memory

Programmable Array Logic

Programmable Logic Array
The process of entering the information into these devices is known as programming.
Basically, users can program these devices or ICs electrically in order to implement the
Boolean functions based on the requirement. Here, the term programming refers to hardware
programming but not software programming.
Programmable Read Only Memory PROM
Read Only Memory ROM is a memory device, which stores the binary information
permanently. That means, we can’t change that stored information by any means later. If the
ROM has programmable feature, then it is called as Programmable ROM PROM. The user
has the flexibility to program the binary information electrically once by using PROM
programmer.
PROM is a programmable logic device that has fixed AND array & Programmable OR array.
The block diagram of PROM is shown in the following figure.
Programmable Array Logic PAL
PAL is a programmable logic device that has Programmable AND array & fixed OR array.
The advantage of PAL is that we can generate only the required product terms of Boolean
function instead of generating all the min terms by using programmable AND gates.
The block diagram of PAL is shown in the following figure.
Programmable Logic Array PLA
PLA is a programmable logic device that has both Programmable AND array &
Programmable OR array. Hence, it is the most flexible PLD. The block diagram of PLA is
shown in the following figure.
Differentiate Moore and Mealy machines with block diagram
9.
Mealy Machine
A Mealy Machine is an FSM whose output depends on the present state as well as the
present input.
It can be described by a 6 tuple (Q, ∑, O, δ, X, q0) where −

Q is a finite set of states.

∑ is a finite set of symbols called the input alphabet.

O is a finite set of symbols called the output alphabet.

δ is the input transition function where δ: Q × ∑ → Q

X is the output transition function where X: Q × ∑ → O

q0 is the initial state from where any input is processed (q0 ∈ Q).
The state table of a Mealy Machine is shown below −
The state diagram of the above Mealy Machine is –
Moore Machine
Moore machine is an FSM whose outputs depend on only the present state.
A Moore machine can be described by a 6 tuple (Q, ∑, O, δ, X, q0) where −

Q is a finite set of states.

∑ is a finite set of symbols called the input alphabet.

O is a finite set of symbols called the output alphabet.

δ is the input transition function where δ: Q × ∑ → Q

X is the output transition function where X: Q → O

q0 is the initial state from where any input is processed (q0 ∈ Q).
The state table of a Moore Machine is shown below –
The state diagram of the above Moore Machine is −
The following table highlights the points that differentiate a Mealy Machine from a Moore
Machine.
Mealy Machine
Moore Machine
Output depends both upon the present state Output depends only upon the present state.
and the present input
Generally, it has fewer states than Moore Generally, it has more states than Mealy
Machine.
Machine.
The value of the output function is a function The value of the output function is a function
of the transitions and the changes, when the of the current state and the changes at the
input logic on the present state is done
clock edges, whenever state changes occur.
Mealy machines react faster to inputs. They In Moore machines, more logic is required to
generally react in the same clock cycle.
decode the outputs resulting in more circuit
delays. They generally react one clock cycle
later.
10.
Derive the state table and state diagram of the sequential circuit shown in below
figure. Explain the function that the circuit performs
Figure not shown