JK Flip-Flop
Due to the undefined state in the SR flip
flip-flops, another flip-flop
flop is required in electronics. The JK flip-flop
flip
is an improvement on the SR flip-flop
flop where S=R=1 is not a problem.
The input condition of J=K=1 gives an output inverting the output state. However, the outputs are the
same when one tests the circuit practically.In simple words, If J and K data input are different (i.e. high
and low), then the output Q takes the value of J at the next clock edge. If J and K are both low, then no
change occurs. If J and K are both high at the clock edge, then the output will toggle from one state to
the other. JK Flip-Flops
Flops can function as Set or Reset Flip
Flip-flops.
JK FF Truth Table:
J
K
Q
Q’
0
0
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
D Flip-Flop
D flip-flop
flop is a better alternative that is very popular with digital electron
electronics.
ics. They are commonly used
for counters and shift registers and input synchronization.
In the D flip-flops,
flops, the output can only be changed at the clock edge, and if the input changes at other
times, the output will be unaffected.
Truth Table:
Clock
D
Q
Q’
↓»0
0
0
1
↑»1
0
0
1
↓»0
1
0
1
↑»1
1
1
0
The change of state of the output is dependent on the rising edge of the clock. The output (Q) is the
same as the input and can only change at the rising edge of the clock.
T Flip-Flop :
A T flip-flop
flop is like a JK flip
flip-flop. These are basically single-input versions of JK flipflip
flops. This modified form of the JK is obtained by connecting inputs J and K together. It has only one
input along with the clock input.
These flip-flops are called T flip-flops
flops because of their ability to complement their state i.e. Toggle,
hence they are named Toggle flip-flops
flops.
Truth Table:
T
Q
Q (t+1)
0
0
0
1
0
1
0
1
1
1
1
0
Master Slave Flip Flop
A master-slave
slave flip
flip-flop contains two clocked flip-flops.
flops. The first is called a master and
the second is a slave. When the clock is high the master is active. The output of the master is set or reset
according to the state of the input. As the slave is in active during this period its output remains in the
previous state. When the clock becomes low the output of the slave flip-flop
flop changes because it
becomes active during the low clock period. The final output of the master
master-slave flip-flop is the output
of the slave flip-flop.
flop. So the output of master
master-slave
slave flip flop is available at the end of a clock
cloc pulse.
Master Slave JK Flip Flop is a combination of two JK flip flops which are connected as shown in the
figure:
In this combination of two JK flip flop, one acts as a master flip flop and the other acts as a slave flip
flop. In this master-slave flip flop, the outputs of the master JK flip flop are connected to the inputs of
the slave JK flip flop. The outputs of the slave flip flop are fed back to the inputs of the master JK flip
flop.
In the master-slave JK flip flop, a NOT gate (Inverter) is also used which is connected to clock signal in a
manner that the inverted clock signal is applied to the slave flip flop.
Therefore, when clock signal to master flip flop is 0, then for slave flip flop the clock signal is 1, and if the
clock signal to master flip flop is 1, then for the slave flip flop it 0.
Working of Master-Slave JK Flip Flop
When the clock pulse goes to high, the slave flip flop becomes inactive and the inputs J and K can control
the state of the system.
When the clock pulse goes back to low, the information is transferred from master flip flop to the slave
flip flop, and the final output of the system is obtained.
From the circuit, it is clear that the master flip flop is positive level triggered and the slave flip flop is
negative level triggered. Consequently, the master flip flop responds before the slave flip flop. Now, let
us discuss the operation of the master-slave JK flip flop for different combinations of inputs J and K.


When J = 0 and K = 0, both JK flip flops remains inactive and hence the output Q remains
unchanged. This is called Hold State of the master-slave JK flip flop.
When J = 0 and K = 1, the output Q' of the master flip flop is high and goes to the input K of the
slave flip flop. The clock signal forces the slave flip flop to reset. Therefore, the slave flip flop has


the same output has the master flip flop, i.e., high Q' and low Q. This is called reset state of the
master-slave JK flip flop.
When J = 1 and K = 0, the output Q of the master flip flop is high and goes to the input J of the
slave flip flop, the negative transition of the clock signal sets the slave flip flop. Hence, this is
called the set state of the master-slave JK flip flop.
When J = 1 and K = 1, for this input combination, the master flip flop toggles on the positive
transition of the clock pulse and the slave flip flop toggles on the negative transition of the clock
pulse. Hence, the problem of the race around condition of the JK flip flop is solved.
Truth Table of Master-Slave JK Flip Flop
Inputs
Output
Comment
J
K
Qn+1
0
0
Qn
No Change
0
1
0
Reset
1
0
1
Set
1
1
Qn'
Toggle
Registers
A register is a device used to store multiple bits of data, with the help of n-flip-flops connected in an
order.
Shift Register
If the register is capable of shifting bits either towards right hand side or towards left hand side is known
as shift register. An ‘N’ bit shift register contains ‘N’ flip-flops. Following are the four types of shift
registers based on applying inputs and accessing of outputs.




Serial In − Serial Out shi register
Serial In − Parallel Out shi register
Parallel In − Serial Out shi register
Parallel In − Parallel Out shi register
Serial In − Serial Out (SISO)Shift Register
The shift register, which allows serial input and produces serial output is known as Serial In – Serial
Out (SISO) shift register. The block diagram of 3-bit SISO shift register is shown in the following figure.
This block diagram consists of three D flip-flops, which are cascaded. That means, output of one D flipflop is connected as the input of next D flip-flop. All these flip-flops are synchronous with each other
since, the same clock signal is applied to each one.
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input
is also called as serial input. For every positive edge triggering of clock signal, the data shifts from one
stage to the next. So, we can receive the bits serially from the output of right most D flip-flop. Hence,
this output is also called as serial output.
Serial In - Parallel Out (SIPO)Shift Register
The shift register, which allows serial input and produces parallel output is known as Serial In – Parallel
Out( SIPO) shift register. The block diagram of 3-bit SIPO shift register is shown in the following figure.
This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is
connected as the input of next D flip-flop. All these flip-flops are synchronous with each other since, the
same clock signal is applied to each one.
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input
is also called as serial input. For every positive edge triggering of clock signal, the data shifts from one
stage to the next. In this case, we can access the outputs of each D flip-flop in parallel. So, we will
get parallel outputs from this shift register.
Parallel In − Serial Out (PISO) Shift Register
The shift register, which allows parallel input and produces serial output is known as Parallel In − Serial
Out (PISO) shift register. The block diagram of 3-bit PISO shift register is shown in the following figure.
This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is
connected as the input of next D flip-flop. All these flip-flops are synchronous with each other since, the
same clock signal is applied to each one.
In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1.
For every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we will
get the serial output from the right most D flip-flop.
Parallel In - Parallel Out (PIPO) Shift Register
The shift register, which allows parallel input and produces parallel output is known as Parallel In −
Parallel Out (PIPO) shift register. The block diagram of 3-bit PIPO shift register is shown in the following
figure.
This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is
connected as the input of next D flip-flop. All these flip-flops are synchronous with each other since, the
same clock signal is applied to each one.
In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1.
We can apply the parallel inputs through preset or clear. These two are asynchronous inputs. That
means, the flip-flops produce the corresponding outputs, based on the values of asynchronous inputs. In
this case, the effect of outputs is independent of clock transition. So, we will get the parallel
outputs from each D flip-flop.
Application for XOR gate
Error detection codes are used to detect error during the transmission,it can only detect the errors but
cannot be corrected.
The parity generator and parity checker’s main function is to detect errors in data
transmission.The parity bit is an extra bit that is set at the transmission side to either ‘0’ or ‘1’, it is used
to detect only single bit error and it is the easiest method for detecting errors.
The parity bit or check bits are the bits added to the binary code to check whether the
particular code is in parity or not.
For example, whether the code is in even parity or odd parity is checked by this check bit or parity bit.
The parity is nothing but number of 1’s and there are two types of parity bits they are even bit and odd
bit.
In odd parity bit, the code must be in an odd number of 1’s, for example, we are taking 5-bit code
100011, this code is said to be odd parity because there is three number of 1’s in the code which we
have taken. In even parity bit the code must be in even number of 1’s, for example, we are taking 6-bit
code 101101, this code is said to be even parity because there are four number of 1’s in the code which
we have taken.
The parity generator is a combination circuit at the transmitter, it takes an original message as input
and generates the parity bit for that message and the transmitter in this generator transmits messages
along with its parity bit.
The combinational circuit at the receiver is the parity checker. This checker takes the received message
including the parity bit as input. It gives output ‘1’ if there is some error found and gives output ‘0’ if no
error is found in the message including the parity bit.
Analog to Digital Converter(ADC)
Analog-to-Digital converters (ADC) translate analog signals, real world signals like temperature,
pressure, voltage, current, distance, or light intensity, into a digital representation of that signal. This
digital representation can then be processed, manipulated, computed, transmitted or stored.
In ADC, the conversion of the signal from analog to digital can be explained through the below block
diagram.
Sampler
Holding Circuit
Quantizer
Encoder
Sampler
Sampler takes samples from the continous analog signal according to already set sampling frequency
sampler convert continous amplitude signal to continous amplitude discrete signal.
Holding Circuit
It hold the samples generated by the sampler until next sample arrives.After sample arrives old signals
are released.
Quantizer
It breaks samples into small parts. It quantizes the signal from continuous amplitude discrete time signal
to discrete time amplitude signal.
Encoder
The circuit actually generate digital signal to binary form.
Working Principle of ADC
First, the analog signal is applied to the first block namely a sample wherever it can be sampled at an
exact sampling frequency. The amplitude value of the sample like an analog value can be maintained as
well as held within the second block like Hold. The hold sample can be quantized into discrete value
through the third block like quantize. Finally, the last block like encoder changes the discrete amplitude
into a binary number.
Digital to Analog Convertor(DAC)
A Digital to Analog Converter (DAC) converts a digital input signal into an analog output signal. The
digital signal is represented with a binary code, which is a combination of bits 0 and 1 and the analog
signal be voltage or current.
Digital
input
Serial register
Voltage switching
Resistive summing
network
Amplifierome pin
Analog Signal
Reference
Voltage
First, the N-bit digital input is provided to a DAC serial register. The voltage switch and resistor summing
network converts the digital inputs to analog output levels.