Layout tutorial
Setup
 Open, link to layout from schematic
1. Open schematic circuit
2. Choose Launch  Layout XL
3. Connectivity  Generate  All from source
 Grid
1. Option  Display
2. Choose value for X/Y Snap spacing
 Work environment: in layer tab choose V (Visibility) and S (Selection) for
easier process
Hot key
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A: Align
K: Ruler
C: copy
M: Move
H and ‘.’: identical copy (space and size)
Shift + C: Cut
S: Stretch
N: Direction of device movement
Ctrl+F: red cell view
Shift+F: Layers view
P: Create wire with minimum width according to DRC
R: Create rectangular shape
O: Create Via/Contact
F4: Select whole/edge of shape
Q: Edit object properties
Tools
VIA
+ Reset Parameters to: Minimum Rule Enclosures
+ Enclosures: used to adjust the edge of VIA/Contact
+ Choose Via definition: none/M4X_M3X_V/M4X_M3X_H to create vias with
different direction
PIN
Pin has 2 part
+Pin: use drawing layer
+Label: use pin layer
Hight light
+ When select a device in schematic or layout  the other will be highlighted
+ Right click and probe to mark with different colors (with wire in schematic an
device in layout)
+ Color in schematic and layout are the same
Simulation/Checker
DRC: use to check design rule
Calibre  run DRC  OK
Add Design Rule for DRC as figure below
Choose input to run DRC
+ Default: check DRC for whole circuit
+ Area: check DRC for a specific area that we can choose from layout window
LVS: layout-schematic check
Choose LVS link similar to DRC
 OK  Run LVS (default input is whole circuit)
If there is no error
 Clean (smile face)
Common mistake
Off-grid
Symptoms: Shape, device’s corner doesn’t coincide with the grid’s dot
Cause:
+ Not set the snap spacing in slide 5
+ 2 workstations work on different snap spacing
+ Align with other off-grid devices
Solution:
+ Set the smallest snap spacing
+ Move device to grid
+ Re-set snap spacing
Contact/Via
Use not enough via/contact
Consequences:
+ Large resistor
+ Un-connect wire if one via/contact is corrupt in the process (in case use only 1
via/contact)
Solution:
+ Add more via/contact (specially from POLY to METAL)
N-well/Deep N-well
It is compulsory to Bias VDD or GND for N-well and Deep N-well
Reason:
+ Digital VDD/GND is different from Analog VDD/GND
+ Bulk/Substrate terminal is connected automatically to main GND of the chip 
shorted/wrong connection
+ N-well has to cover edge of
Deep N-well
Wire’s width
Avoid routing wires with large difference in width
Multiple/Finger
Multiple should be multiplication of 2 or 4
+ multiple of 2: floor plan is symmetrical to an axe
+ Multiple of 3: floor plan is symmetrical to a center point
Floor plan
 Dummy device
 Devices on ends array experience different effects than inner devices
 Add dummy devices at array ends to ensure all devices”experience
same environment”
 Dummy devices have all terminals shorted together
 Be mindful of added parasitics
 Importance of matching
Bias
PVT sensitivity
Operating headroom
Quiescent Control
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Offset
Input pairs
Common Mode
Range
CMRR
PSRR
Common centroid
 Common Centroid is an extension of interleaving. Resisters A&B
share common center.
 Reduces mismatch even further in presence of linear gradients
 Wiring more complicated added parasitic