High Efficiency CMOS Rectifier Circuits for VHF
RFIDs V sing Vth Cancellation Techniques
Koji Kotani* and Takashi Ito
Abstract - Two types of CMOS rectifier circuits for UHF
RFIDs have been proposed. Large power conversion
efficiency (PCE) has been achieved by Vth cancellation
techniques. In the Self- Vth-Cancellation (SVC) CMOS
rectifier, the threshold voltage of MOSFETs is cancelled by
gate bias voltage generated from the output voltage of the
rectifier itself, resulting in excellent PCE. The differentialdrive CMOS rectifier has a cross-coupled bridge
configuration and is driven by a differential RF input. A
differential-drive scheme realizes an active gate bias
mechanism and simultaneously enables both low ONresistance and small reverse leakage of diode-connected MOS
transistors, resulting in large PCE, especially under small RF
input power conditions. Test circuits for both types of
rectifiers were fabricated and the measured performances
were compared with those ofconventional rectifiers.
Index Terms rectifier, radio frequency identification
(RFID), ultra high frequency (UHF), Vth cancellation.
I.
INTRODUCTION
The application of a passive-type radio-frequency
identification (RFID) tag is rapidly expanding in various fields,
including supply chain management, logistics, access control,
etc. [1]-[3]. Passive RFID tags have no battery and must be
powered by an RF signal radiated from a reader/writer (R/W).
Among various types of RFIDs operating at respective
frequencies, the ultra-high-frequency (UHF: 860-960 MHz)
RFID is the best to realize the longest communication distance.
Recently, UHF RFID having communication distances of 7 m
has been reported [4].
The available power at the tag antenna PAVAIL can be
theoretically calculated by the Friis' transmission equation:
PA VAlL
= (4~
J
PEIRPGtag'
where A is the wavelength of the radio wave, d is the
distance between the R/W and the tag, PEIRP is the effective
isotropic radiation power of R/W, and Gtag is the tag antenna
gain. P EIRP is determined by regional regulations, and Gtag is
mainly determined by the allowable antenna area (1.64 for A/2
dipole antenna).
Under the conditions where the frequency is 953 MHz,
P EIRP is 4 W, and Gtag is 1.64, the available power PAVAIL is
resultantly as small as 114 JlW (-9.4 dBm), assuming that the
distance d is 6 m. Input RF power is then converted into DC
power by a rectifier circuit and supplied to the tag circuits.
Since the power dissipation of the tag circuit P tag is roughly
determined by the functions implemented in the tag (varies
from 10 to 100 JlW according to the baseband signal
processing functions of the tag), PCE of the rectifier circuit
which is evaluated by Ptag/ PAVAIL should be as large as
The authors are with the Department of Electronics, Graduate School of
Engineering, Tohoku University, Sendai 980-8579 JAPAN (e-mail:
kotani@ecei.tohoku.ac.jp).
possible in order to achieve larger d. When Ptag is 30 JlW, a
PCE of larger than 26% is required at the very low input
power condition of -9.4 dBm in order to achieve a
communication distance d of 6 m. This is very challenging
since it is very difficult to achieve a large PCE under very low
input power conditions.
II. CONVENTIONAL RECTIFIER CIRCUITS
The PCE of the rectifier circuit is affected by circuit
topology, diode parameters, and input RF signal level as well.
As for the diode parameters, small ON-resistance and small
reverse leakage current of the diode device are essential to
increase PCE. In conventional diode devices, reverse leakage
current is generally small enough to be ignored. Therefore,
diode devices having small ON-resistance are effective. Small
ON-resistance can generally be achieved by small tum on
voltage YTO of the diode. For this purpose, Schottky diode
having a tum-on voltage of 200-300 mY is sometimes utilized
[4], [5]. But, Schottky diode is not suitable for the practical
applications since it requires costly fabrication processing and
has large temperature dependence. Instead, a diode-connected
MOS transistor is widely used. The effective YTO of the
diode-connected MOS transistor is almost equal to the
threshold voltage of the MOS transistor, which is slightly
larger than a Schottky diode but smaller than a pn-junction
diode.
While the PCE for rectifiers using a simple diode-connected
MOS transistor is not so large, it can be drastically increased
when an appropriate Vth-cancellation mechanism is applied.
The external-Vth-cancellation (EYC) scheme [6] was
proposed for a semi-passive tag. nMOS gate bias voltage is
generated with a switched-capacitor (SC) circuit. Since the
operation of the SC circuits requires an external power supply
and clocking, this scheme cannot be applied to passive-type
RFIDs.
The internal-Vth-cancellation (IYC) scheme [7] was also
proposed. Gate bias voltage is generated internally from the
output DC voltage by a bias generation circuit. This circuit
works well in large input power conditions, but not under
small input power conditions since gate bias voltages are
generated by the voltage division mechanism. In addition, the
bias generation circuit dissipates some amount of power due
to the DC pass current, resulting in slight degradation in PCE.
III. SELF-VTH-CANCELLATION RECTIFIER CIRCUIT
Figure 1 shows the developed self-Vth-cancellation (SYC)
CMOS rectifier circuit [8], [9]. It is the same as the diodeconnected CMOS rectifier circuit except that gate electrodes
of the n-MOS transistor and the p-MOS transistor are
connected to the output terminal and ground terminal,
respectively. This connection boosts gate-source voltages of
the n-MOS and p-MOS transistors as much as possible. In
other words, threshold voltages of the MOS transistors are
equivalently decreased by the same amount as the output DC
voltage.
Compared with the EYC scheme using the switched549
978-1-4244-3870-9/09/$25.00 ©2009 IEEE
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VRr-'~""'''''''''''''±C''''''''''''''''''''''u;;it:~'i'''''
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Fig. 1 Self-Vth-cancellation (SVC) rectifier circuit.
capacitor mechanism and the IVC scheme, this SVC scheme is
much simpler and requires no additional power, possibly
resulting in better PCE. In addition, the SVC scheme can
obtain the best Vth cancellation efficiency at lower DC output
voltage conditions, and hence at the lower RF input power and
voltage conditions, as compared with the IVC scheme in
which gate bias voltage is generated by dividing the DC
output voltage by the IVC circuit. This is quite important,
especially in UHF RFID applications where input RF signal
voltage is quite small.
In diode-connected MOSFET with Vth cancellation, excess
gate bias voltage results in effective Vth which is too small.
In this condition, reverse leakage current increases
dramatically, resulting in increased diode loss under
conditions of large gate bias. In the SVC scheme, since gate
bias voltage is directly supplied from output DC voltage, PCE
decreases under conditions of large DC voltage output. As a
result, PCE of the SVC rectifier circuit will first increase with
the increase in input power, but then decrease with the further
increase in input power, exhibiting some peak value in
between.
A test circuit for the SVC CMOS rectifier was designed and
fabricated with 0.35 urn CMOS 2P3M technology. A single
unit stage composed of one nMOS and one pMOS transistor
was designed. Drawn gate length and width of the MOS
transistors are 0.4 urn and 40 urn for n-MOS and 0.4 urn and
120 urn for p-MOS, respectively. MOS transistors have a
multi-finger structure where each finger has a length of 5 urn,
Measurement of threshold voltages of n-MOS and p-MOS
showed them to be 0.585 V and -0.828 V, respectively. An
input coupling capacitor Cc and an output smoothing
capacitor C, were fabricated with a polysilicon-polysilicon
capacitor structure and designed to have capacitances of 3.4
pF and 7.6 pF, respectively.
Figure 2 shows a
photomicrograph of the fabricated SVC CMOS rectifier
circuit. A conventional CMOS rectifier, an n-MOS-only
rectifier, and a p-MOS-only rectifier with the same device
sizes and parameters as those in the SVC CMOS rectifier were
also designed for performance comparison.
Measurement conditions were as follows unless otherwise
specified. RF frequency was 953 MHz, which is the center
frequency of the licensed frequency band for UHF RFIDs in
Japan. To emulate the power dissipation of functional circuits
in RFIDs as a load of a rectifier, a 10 kQ resistor was
connected to the DC output terminal of the rectifier.
Figure 3 shows measured PCE as a function of RF input
power PIN. The SVC CMOS rectifier developed in this study
was compared with conventional nMOS, pMOS and CMOS
rectifiers under the same design parameters and measurement
conditions.
Although PCEs for conventional rectifiers
monotonically increase in input power PIN, PCE of the SVC
CMOS rectifier first increases and then decreases with the
further increase in PIN as expected. PCE of the SVC CMOS
rectifier exhibits a peak PCE of 32% at a PIN of -10 dBm. At
Fig. 2 Photomicrograph of the fabricated SVC CMOS
rectifier test circuit.
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Fig. 3 Measured PCE as a function ofRF input power
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Fig. 4 peEs as a function ofRF input voltage VRF•
this condition, the SVC CMOS rectifier has a larger PCE than
conventional nMOS, pMOS and CMOS rectifiers. In addition,
it is superior to the EVC nMOS rectifier and the IVC CMOS
rectifier, although the design parameters and measurement
conditions of the latter two are different from those of the
SVC CMOS rectifier.
The conventional nMOS rectifier is superior to the SVC
CMOS rectifier in the small input power range below -14
dBm. This is because under extremely small input power
conditions the SVC mechanism cannot work well and the
SVC CMOS rectifier operates just like a conventional CMOS
rectifier. The CMOS rectifier contains a pMOS diode which
has a larger tum-on voltage than an nMOS diode, resulting in
degraded PCE. However, since PCE obtained by the nMOS
rectifier under the extremely small input power conditions is
too small to be applied practically, this inferiority of the SVC
CMOS under these conditions is not disadvantageous at all.
In addition, PCE of the SVC CMOS rectifier is inferior to
the conventional nMOS rectifier when input power becomes
larger than -7 dBm. This is also no problem since the larger
550
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PCE under the small input power condition is the only
requirement and large PCE at large input power condition is
not helpful for achieving longer communication distance of
RFIDs.
PCEs are re-plotted as a function of RF input voltage and
shown in Fig. 4. PCE of SVC rises sharply at an RF input
voltage of 440 mVrms. This is the threshold for triggering the
Vth cancellation mechanism. When RF input voltage reaches
this point, rectifier starts to operate and DC output voltage
increases. This increases the Vth cancelling bias voltage and
increase PCE. Then, DC output voltage, which is increased
by the increase in PCE, further increases PCE. Meanwhile,
DC output voltage excessively increases, effective threshold
voltage of diode-connected MOS transistors decreases due to
the SVC mechanism and leakage current increases, resulting
in the suppression of the further increase in PCE. Then the
operation reaches steady-state. At this point the maximum
PCE can be obtained.
IV. CMOS DIFFERENTIAL RECTIFIER CIRCUIT
In the SVC CMOS rectifier circuit described in the previous
section, gate-source voltages of the n-MOS and p-MOS
transistors are "statically" biased using the output DC voltage,
thus reducing the effective Vth of the MOS transistors.
However, when the effective threshold voltage of the MOS
transistor becomes too small, increased reverse leakage
current cannot be ignored. If the reverse leakage current is
not negligible, it directly results in energy loss since charges
flowing in a reverse direction are wasted. In addition, the
forward current must be further increased to compensate the
reverse leakage current, thus increasing energy loss. As a
result, it is concluded that we cannot achieve a small ONresistance and a small reverse-leakage current at the same time
by "static" Vth cancellation schemes.
In order to solve the problem, we have developed a
differential-drive CMOS rectifier circuit [10] shown in Fig. 5.
The circuit has a cross-coupled differential CMOS
configuration with a bridge structure. This kind of circuit
topology is known as a low-frequency rectifier circuit and is
sometimes applied to the rectifier in RFIDs without actual
test-chip measurement and/or detailed performance analysis
[11]. We analyzed it thoroughly under various operating
conditions and found that it is also very effective as a highfrequency rectifier for RFIDs. Common-mode voltage VCM,
which is about half of the output DC voltage VDC , is generated
at the internal nodes Vx and V y by a rectification operation
and acts as a kind of static gate bias voltage compensating Vth,
as in the previous Vth cancellation schemes [6]-[9]. In
addition, in this differential scheme, the gate of transistors is
"actively" biased by a differential-mode signal. When Vx is
negative, which corresponds to the forward bias condition for
the nMOS MNI diode, the gate voltage ofMNl, which is V y ,
is positively biased and effectively decreases the effective Vth
of MNl, resulting in a small ON-resistance. On the other
hand, when Vx becomes positive, which corresponds to the
reverse bias condition, the gate voltage rapidly decreases,
which effectively reduces the reverse leakage current.
Figure 6 shows measured I-V characteristics of a diodeconnected nMOS transistor. In the figure, the static Vth
cancellation and the active differential Vth cancellation
schemes are compared. In the static Vth cancellation case,
static gate bias voltage reduces ON-resistance in contrast with
the zero-bias condition (simple diode-connected), but also
increases the reverse leakage current, which leads to diode
Fig. 5 Differential-drive CMOS rectifier circuit.
t--_I----t---+---+_~--+--~-~
vos (V)
0.6
,
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~
Active Differential -10
VG=0.5 + Vos(V) -15
Fig. 6 I-V characteristics of diode-connected nMOS
transistors.
Fig. 7 Photomicrograph of fabricated differential-drive
CMOS rectifier.
loss and degradation of the PCE. On the other hand, in the
active differential Vth cancellation scheme, both smaller ONresistance and smaller reverse leakage current are
simultaneously obtained.
A test chip was designed and fabricated with 0.18 urn
CMOS process having RF options. Channel width/length of
nMOS and pMOS transistors were 3.6 um/Ol S urn and 18
um/Ol S urn, respectively. Measured Vths for nMOS and
pMOS were 0.437 V and -0.450 V, respectively. Both
coupling capacitor Cc and smoothing capacitor Cs were
designed to be 1.13 pF. A photomicrograph of the chip is
shown in Fig. 7. Since shielded low-loss probing pads and
MIM capacitors were used, substrate loss could be avoided.
Figure 8 shows measured PCE as a function of input RF
power PIN in dBm. The measurement was carried out at 953
MHz and an RL of 10 KQ. The newly developed differential
CMOS rectifier achieved 67.5% of the peak PCE at -12.5
dBm, which is the highest PCE ever reported, and specifically,
more than two times larger than the previous Self-VthCancellation (SVC) scheme.
This allows the possible
operation of a tag dissipating 40 fl W at an 8-m range under
551
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conditions. In the multi-stage configuration, unit stages are
connected in parallel to the RF input as described before and
this reduces the input impedance of the rectifier. Therefore,
the RF signal voltage amplitude of the multi-stage rectifier
becomes smaller than that of the single-stage rectifier under
the same RF input power condition and this leads to the
decrease in PCE since sufficient RF signal voltage amplitude
larger than the threshold voltage of MOS transistors is
essential for achieving higher PCE.
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Fig. 8 Measured PCE as a function of PIN.
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We developed high-efficiency CMOS rectifier circuits
utilizing the Vth-cancellation scheme for UHF RFID
applications. The SVC CMOS rectifier creates VGs-boosting
bias voltage from the DC output voltage itself. The circuit is
quite simple and requires no additional power dissipation,
resulting in large PCE. The 32% of PCE has been achieved at
-10 dBm of RF input power.
We also developed the
differential-drive CMOS rectifier circuit with an active Vth
cancellation scheme. The rectifier can automatically minimize
the effective Vth of diode-connected MOS transistors in a
forward bias condition and automatically increase it in a
reverse bias condition by a cross-coupled differential circuit
configuration. The rectifier circuit achieved a PCE as large as
67.5% at 953 MHz, -12.5 dBm of RF input and 10 Kn of
output loading.
The multi -stage configuration was also
evaluated as being effective to achieve large output DC
voltage without degrading PCE.
0
Fig. 9 Measured VDC as a function of PIN"
UHF RFID regulations (4W EIRP). At this point, measured
input impedance of the rectifier was 390-j 1815 n, which
corresponds to an equivalent parallel resistance and
capacitance of 8.8 Kn and 88 fF, respectively.
In the differential-drive CMOS rectifier, peak PCEs are
obtained at an output DC voltage around 0.6 V. This output
DC voltage is insufficient for CMOS digital baseband circuits
in RFIDs, where 3---5xVth is generally required for V DD power
supply voltage. In order to obtain larger output DC voltage,
the multi-stage configuration, in which unit stages are serially
stacked along the DC path and connected in parallel to the
input RF terminals, is effective.
By the multi-stage
configuration, we can design a rectifier circuit which can
provide appropriate DC output voltage at the optimal
operating point where the maximum PCE can be obtained.
As an example of the multi-stage differential-drive CMOS
rectifier, a triple-stage rectifier was designed and its
performance was compared with that of the single stage
rectifier. Figure 9 shows output DC voltages as a function of
RF input power. Output loading resistance was set at 50 Kn
in this case. At an RF input power larger than -14 dBm, the
triple-stage rectifier outputs larger DC voltage than the singlestage rectifier since stacked rectifier stages work effectively
under the sufficiently-large RF signal amplitude. When RF
input power was -10 dBm, for instance, sufficient DC voltage
of 1.8 V was obtained. At this operating condition, PCE was
maintained at 65%. On the other hand, the triple-stage
rectifier outputs smaller DC voltage than the single-stage
rectifier at an RF input power less than -14 dBm. This is
because in the multi-stage configurations, PCE becomes
smaller than the single-stage under small RF input power
CONCLUSION
ACKNOWLEDGMENT
The test chips were designed with Cadence and Agilent
CAD tools and fabricated through the chip fabrication
program of the VLSI Design and Education Center (VDEC),
the University of Tokyo, in collaboration with Rohm
Corporation and Toppan Printing Corporation.
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