CSE670
FPGA based UART
Project Status
Tom Prohaszka
03/29/04
Task List
• Learn about UARTs & Protocol
• Top Level Design and Interface
• Detailed Design
• Implementation
• Test
2/18/2019
thp-FPGA Based UART
2
Learn about UARTs & Protocol
• Two forms of interfaces: DTE and DCE
•
•
– DTE for PC, D2E board is a DCE, so NO NULL MODEM!
10 bits (LSB first): Start Bit(0), 8 bits Data, 1 Stop Bit(1)
Clocks and Prescalars: TX Data uses BAUD Rate, RX Data
uses 16 times Baud Rate, Why? Compatibility w/16550
and Sampling.
2/18/2019
thp-FPGA Based UART
3
Top Level Design
• One Uart has 3 Pieces
– Baud Generator, Transmit Control , Receive Control
– Example Baud: 2400 bps, 1 bit=1/2400=416.66us,
error of less than 0.07%
2/18/2019
thp-FPGA Based UART
4
More to do…
• Implementation & Test
– TX State Machine
– RX State Machine
– Test Bench connected to PC
– Hooks into FC16??
2/18/2019
thp-FPGA Based UART
5