CSE670
VHDL UART for Spartan
Tom Prohaszka
04/12/04
Abstract:
Universal Asynchronous Receiver/Transmitters (UARTs) provide a simple means of allowing two
computer systems to communicate with each other using a serial bit stream and protocol. This paper
discusses the theory of operation for UARTs as well as an implementation of a VHDL based UART
implementation for the Spartan 2E FPGA. The resulting design allows for multiple instances of a
UART within a higher level design to support multiple connects to computers. The design provides
transmit and receive holding registers and flexible baud rate selection. Aspects of the design such as
timing diagrams, low level design, and test benches will be discussed.
Table Of Contents
1
2
3
4
5
6
7
Introduction ......................................................................................................................................... 3
UART Theory of Operation ................................................................................................................ 4
2.1
Overview ..................................................................................................................................... 4
2.2
Electrical Characteristic .............................................................................................................. 4
2.3
Communication Protocol ............................................................................................................ 5
Digilent D2E Hardware Interface ....................................................................................................... 7
UART Design ..................................................................................................................................... 8
4.1
UART Overview ......................................................................................................................... 8
4.2
Baud Generator Design ............................................................................................................. 10
4.3
Transmitter Design.................................................................................................................... 11
4.4
Receiver Design ........................................................................................................................ 14
Test Bench Design ............................................................................................................................ 17
Conclusion ........................................................................................................................................ 18
References ......................................................................................................................................... 19
Table Of Figures
Figure 1 Example of DTE and DCE devices .............................................................................................. 4
Figure 2 DTE and DCE minimum Pin Connection .................................................................................... 4
Figure 3 Electrical Signal Levels ................................................................................................................ 5
Figure 4 Communication Protocol .............................................................................................................. 6
Figure 5 D2E MAX3386 Schematic ........................................................................................................... 7
Figure 6 D2E Hardware Pinout................................................................................................................... 7
Figure 7 UART Block Diagram .................................................................................................................. 8
Figure 8 UART Top Level Design ............................................................................................................. 8
Figure 9 Baud Rate Generator Design ...................................................................................................... 10
Figure 10 Baud rate timing diagram ......................................................................................................... 10
Figure 11 Transmit Design ....................................................................................................................... 11
Figure 12 Transmit State Machine ............................................................................................................ 12
Figure 13 Transmit Control and Datapath ................................................................................................ 12
Figure 14 Transmit Control and Datapath timing diagram ....................................................................... 13
Figure 15 Receive Design ......................................................................................................................... 14
Figure 16 Receive State Machine ............................................................................................................. 15
Figure 17 Receive Control and Datapath .................................................................................................. 15
Figure 18 Receive Control and Datapath timing diagram ........................................................................ 16
Table Of Tables
Table 1 Top Level UART Signal Description ............................................................................................ 9
Table 2 Baud Rate Selections and Bit Timing Data ................................................................................. 10
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CSE670 W04 Tom Prohaszka
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1 Introduction
The Universal Asynchronous Receiver/Transmitters (UARTs) is a computer component that handles
asynchronous serial communication with another computer device. Every computer contains a UART to
manage the serial ports. Microprocessors contain a similar implementation called Serial
Communications Interface(SCI). This project implements a form of the UART design modeled after a
microprocessor implementation using VHDL in a Xilinx Spartan 2E FPGA running on a Digilent D2E
board. To properly implement the design, a theory of operation for UARTs will be discussed, which
includes the baud clock generation and low level serial protocol wave form descriptions. Based on the
theory of operation, the top level FPGA component design of the UART will be discussed as well as the
low level blocks that comprise the UART. Additionally, the test bench will be described that is used to
verify the UART design.
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2 UART Theory of Operation
This section describes the overall UART theory of operation.
2.1 Overview
A long time ago in the 1960’s, the Electronic Industries Association (EIA) developed a standard which
defined how computer equipment should be interfaced from hardware pin assignments to signal level
descriptions. Most recently, the standard has been re-named EIA232E, but it is historically known as
the RS232 standard. The standard classifies two types of devices. One is the Data Terminal
Equipment(DTE) device which is a dumb terminal(which is a terminal program on a PC today) which is
considered the source of data. The other is a Data Circuit-terminating Equipment(DCE) device, which
is historically a modem, but can be any other hardware device. The devices are connected using a
standard cable which allows them to send serial data to each other.
RS232 Cable
DTE-PC
DCE-Modem
Figure 1 Example of DTE and DCE devices
The standard defines that all pin names and assignments be defined from the point of view of the DTE
device. This is important, especially when understanding how to connect the two devices. The cable
connecting the two devices can contain up to 25 pins. Most implementations today use a simplified
DB9 pin cable, and generally only 3 pins are used in this cable for the most simple of interfaces. Below
are the DB9 pin assignments and description for the simplified DB9 connection.
DTE(PC)
DB9 Male
DCE
DB9 Female
Pin 2 Transmit Data
Pin 2 Receive Data
Pin 3 Receive Data
Pin 3 Transmit Data
Pin 5 Ground
Pin 5 Ground
Figure 2 DTE and DCE minimum Pin Connection
2.2 Electrical Characteristic
Binary data is represented as voltage levels with a range of values representing ones and zeros. The
standard defines voltage ranges of -3v to -25v with respect to signal ground as logic '1' (the marking
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condition), and voltage ranges of +3v to +25v as logic '0' (the spacing condition). Voltages between -3v
and +3v is a transition region and is not a valid signal state. Figure 3 shows a diagram of the signal
states.
voltage
space
space
+25v
Logic 0
+3v
-3v
Logic 1
-25v
mark
Figure 3 Electrical Signal Levels
The voltage levels need to be shifted for use by computer equipment circuitry. This level shifting is
accomplished using a level shifter which converts the high voltage logic levels to 3.3 or 5 volt levels.
Logic 0 is generally 0 volts, and Logic 1 is 3.3 volts(CMOS logic) or 5 volts(TTL logic) levels.
2.3 Communication Protocol
With the logic levels established between the two computer devices, the next step is defining the data
communication protocol which is used to exchange data between the devices. Since there are
individual transmit and receive lines for the DTE/DCE devices, data communication can occur at full
duplex operation, which allows data to be transmitted and received by the DTE(or DCE device)
concurrently. Some implementations support a half-duplex or simplex mode of operation, but those will
not be covered or supported. Additionally, control lines ready/clear to send specified in the EIA
standard could be used, but this implementation will not use them.
Bits of data are exchanged between the DTE and DCE devices at a pre-determined bit timing, or baud
rate. Baud rates are referenced as bits per second. For example, a baud of 9600 bps implies a bit must
maintain its value for a time of 1/9600 or 0.000104166 seconds per bit.
In general, the protocol consists of 10 bits: 1 start bit, 1 stop bit, and 8 data bits. Variations include 1.5
or 2 stop bits, and the addition of a parity bit. This implementation does not support those variations.
From the transmitting devices point of view, when no transmission are taking place, the transmit line
maintains a logic ‘1’ level. When the DTE is ready to transmit, it sends a start bit which is logic 0. This
signals the DCE device that data is about to be sent. It then sends 8 data bits representing the data to be
communicated. Finally, the stop bit is sent which is a logic level of 1. If more data is to be sent, the
process starts over. Figure 3 shows an example bit stream(note parity bit shown, but not used in this
implementation).
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Figure 4 Communication Protocol
For the receiving device, it will be looking for a start bit transition to start sampling the bit stream. The
ideal place for a receiver to sample the bits is in the middle of the bit. This allows for small variations in
the actual baud rate between the devices. To accomplish this, the receiver must sample at a higher rate
than the baud rate. A standard value of 16 times faster than the baud rate appears to be a standard that
most UARTs use. After the receiver sees a start bit transition, it can verify that the start bit is valid and
does not change levels by performing multiple samples. If a valid start bit is not seen, it can wait for
another start bit transition. If a valid start bit is sensed, then it can wait 16 bit times to sample the center
of the successive bits. After 8 data bits are captured, the receiver then samples the stop bit, and then
enters an idle state waiting for the process to repeat. The stop bit allows the receiver time to reinitialize
for the next transmission.
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3 Digilent D2E Hardware Interface
The D2E board is considered a DCE device. It connects to the DTE PC using a standard DB9 straight
through cable. The D2E board has a Max 3386E Level Shifter to perform the required voltage level
shifting. Figure 5 shows the D2E to MAX3386 interface schematic copied from the D2E reference
schematic.
Figure 5 D2E MAX3386 Schematic
One of the big issues with the D2E board is the silk-screen labeling on the 6 pin header J13 relative to
the actual pin connections. Also, the D2E reference manual incorrectly shows the TX on p202 and RX
p201 which is not correct. Listed below is a breakdown of the proper connections for use in the
implementation.
PC/DTE
DB9
Male
RX 2
TX 3
SGND 5
DSR 6
RTS 7
CTS 8
FPGADCE
DB9
Female
RX 2
TX 3
SGND 5
DSR 6
RTS 7
CTS 8
MAX Chip
T1out 17
R1in 14
GND
T2out 16
R2in 13
T3out 15
T1in 07
R1out 11
GND
T2in 08
R2out 10
T3in 09
6 Pin D2E
Header J13
TXD 5
RXD 1
GND 6
DSR 2
RTS 3
CTS 4
D2E Pin#
OU Name
TX p201
RX p202
GND
DSR p200
RTS p198
CTS p199
Figure 6 D2E Hardware Pinout
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4 UART Design
4.1 UART Overview
A block diagram of a basic UART is shown below in Figure 7.
DIN
TXRDY
WR
CCLK CLR
RXRDY
RD
DOUT
Receive Hold Register
Transmit Hold Register
Transmit
Control
Logic
Baud
Generator
Transmit Shift Register
Rxclk
16x
Baud
Clock
TRASMITTER
TX
Receive
Control
Logic
Receive Shift Register
Rxclk
16x
Baud
Clock
RECEIVER
UART
BAUDSEL
RX
Figure 7 UART Block Diagram
The UART is comprised of three units, a transmitter, a receiver, and a shared baud rate control
generator. Each of these sub blocks will be described below. A schematic symbol of the top level
UART designed is shown in Figure 8 and a description of the signals is given in Table 1 Top Level
UART Signal Description.
Figure 8 UART Top Level Design
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Table 1 Top Level UART Signal Description
Signal Name
cclk
clr
baudsel<2:0>
din<7:0>
dout<7:0>
rx
tx
rd
wr
txrdy
rxrdy
Description
This is the system clock. This design uses a 25 MHz clock.
Clears and resets system when ‘1’
Bit encoded value that selects desired baud rate for UART
Data to be written
Data that was read
This is the FPGA input pin for receiving bit data, which is pin 202
This is the FPGA output pin for transmitting bit data, which is pin 201
Strobe a value of ‘1’ indicates the application read the Receive holding
register
Strobe a value of ‘1’ indicates the application is writing to the
Transmit holding register.
A value of ‘1’ indicates the THR is ready to accept new data.
A value of ‘1’ indicates the RHR contains new data.
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4.2 Baud Generator Design
The top level Baud Rate Generator design is shown in Figure 9 Baud Rate Generator DesignThe baud
generator generates rxclk which is 16 times faster than the baud clock, txclk. The 16 times clock is
used for receive sampling as well as for transmitting data. The system clock is divided down based on
the baud rate selections and the associated Clock divisor. When the number of system clocks counted
matches the divisor, a corresponding rxclk is generated. The txclk is generated and is only used for
simulation. Figure 10 shows the rxclck timing diagram for a baud select of 2400 baud. The 16 receive
clocks can be seen as well as the corresponding transmit clock pulse.
Figure 9 Baud Rate Generator Design
Table 2 Baud Rate Selections and Bit Timing Data
SysClk-> 25000000 Hz
Select
000
001
010
011
100
101
110
111
Baud
Rate
2400
4800
9600
14400
19200
38400
57600
115200
16 Times Baud
Clock =
sysclk/(divisor*16)
651.0
325.5
162.8
108.5
81.4
40.7
27.1
13.6
Baud
Clock=
sysclk/baud
10416.7
5208.3
2604.2
1736.1
1302.1
651.0
434.0
217.0
Clock
Divisor
(hex)
028B
0145
00A2
006C
0051
0028
001B
000D
Txclk =
1/baud
(bit cell period)
0.00041666667
0.00020833333
0.00010416667
0.00006944444
0.00005208333
0.00002604167
0.00001736111
0.00000868056
rxclk =
1/16*baud
0.00002604167
0.00001302083
0.00000651042
0.00000434028
0.00000325521
0.00000162760
0.00000108507
0.00000054253
Figure 10 Baud rate timing diagram
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4.3 Transmitter Design
When the transmitter is idle, the Transmit control unit will set the TX bit to a logic ‘1’ to conform to the
serial protocol. The transmitter consists of a transmit holding register(THR) which is used to latch the
data to be written. When TXRDY is ‘1’ , the user can set DIN and latch it by strobeing the WR line.
The transmit hold control unit will set the internal signal TXDATARDY to ‘1’ to notify the transmit
shift control that new data is available. TXRDY becomes ‘0’ since it is the opposite of the
TXDATARDY signal. The transmit hold control unit will not allow an overwrite of the THR if the WR
line is strobed again. When the data in the TSR is finished transmitting, the transmit shift control will
take the latched data in the THR and load it into the TSR, at which point the internal RESET signal
strobed to ‘1’ which will reset the transmit control TXDATARDY to ‘1’. The user can again load
another byte into the THR. This is a double buffered scheme which allows a byte to be primed for
transmission when one is actively being transmitted. Since we are running on an FPGA, the use of a
transmit queue did not make sense, there are no ISR routines and the hardware is essentially running in
parallel with other tasks. When the TSR contains data, the transmit shift control will append the start bit
value of ‘0’ in the TSR. It will then begin to shift out the start bit and 8 data bits at the desire baud
rate. Data is sent least significant bit first from the TSR to the TX output. As data is shifted out, a value
of ‘1’ is shifted into the TSR since this is the final value of the stop bit as well as the idle line state
value. After the stop bit is sent, the transmit shift control enters the idle state.
Figure 11 Transmit Design
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Clear
txdatardy=0
idle
wait for txrdatardy
tx=1
reset=0
txdatardy=1
load
Shifting
shift
reset=1
TX=TSR(0)
Shifting done
Figure 12 Transmit State Machine
DIN
WR CLR CLK
Txrdy
Load
THR CTRL
THR
b7 b6 b5 b4 b3 b2 b1 b0
RESET
0
Txdatardy
Load
1
TSR
b8 b7 b6 b5 b4 b3 b2 b1 b0
TSR CTRL
Shift
TX
Figure 13 Transmit Control and Datapath
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The following diagram shows how two values are written out of the transmitter. First, a value of $AA is
latched into the THR which is seen by the first WR strobe. After the TSR Control takes the value from
the THR and loads the TSR(tshift) and begins shifting. In the middle of shifting, the WR is strobed
again and a value of $7F is loaded into the THR. At this point, TXRDY goes low. Only after the $AA
is shifted out and the stop bit is sent, will the TSR control restart and begin sending the $7F.
Figure 14 Transmit Control and Datapath timing diagram
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4.4 Receiver Design
The receiver design is very similar to the transmitter design. When the receiver is idle, it waits for a
falling edge on the RX line, which signifies a start bit is possibly starting. A transition to the state
validate start is entered, where the start bit is sampled for 8 uart clock cycles. If the start bit is still valid,
the shift state is entered, otherwise the receiver transitions back to the idle state since this is not a valid
start bit.
In the shift state, the uart clock times 16 clock ticks to the center of the next data bit, takes the sample,
and begins timing for the next data bit. After the stop bit is sampled, the data in the Receive Shift
Register is loaded into the Receive holding register and the RXRDY line is set to ‘1’ to notify the
application that data is available. The Receive shift then transitions back to the idle state to repeat the
process.
The application must read the data before the next byte of data is read otherwise the data in the Receive
hold register will be lost. The application must strobe the RD line to notify the Receive Hold control
that the data has been read, which in turn clears the RXRDY signal. This is a double buffered scheme
which allows a byte to be in process of being received while a byte is being held in the holding register.
Since we are running on an FPGA, the use of a receive queue did not make sense, there are no ISR
routines and the hardware is essentially running in parallel with other tasks.
Figure 15 Receive Design
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Clear
RX='1'
idle
RX='1'
wait for RX='0'
rxdone='0'
RX='0'
Valid Count<8
and RX='0'
Valid
Start
Shifting
shift
RSHIFT(7)=RX
SHIFT RSHIFT
Figure 16 Receive State Machine
DOUT
RD
CLR CLK
RXRDY
Load
RHR CTRL
RHR
b7 b6 b5 b4 b3 b2 b1 b0
RXDONE
RSHIFT
b7 b6 b5 b4 b3 b2 b1 b0
RSHIFT CTRL
Shift
RX
Figure 17 Receive Control and Datapath
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The following diagram shows how a simulated value of $55 is received by the receiver.
Figure 18 Receive Control and Datapath timing diagram
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5 Test Bench Design
TBD
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6 Conclusion
TBD
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7 References
The following are references used in the implementation of this project.
http://www.camiresearch.com/Data_Com_Basics/RS232_standard.html#anchor367782
http://www.camiresearch.com/Data_Com_Basics/data_com_tutorial.html
MAX3386E.PDF – rs232 transceiver chip data sheet
D2E_RM.PDF - D2E Reference manual
D2E_SCH.PDF – D2E Schematic
PC16550D.PDF-National Semiconductor UART data sheet
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