www.silabs.com
Clock Generator Timing Solutions
for Consumer & Embedded Designs
Trend - Speed, Dense, Low Power, Portable
2
Trend—Speed
 Speed
 Higher Freq
 Accuracy
 Hitting the freq
target
 Jitter
 Consistent timing
3
Trend  Timing Challenges
 Frequency flexibility – many high speed, non-integer clocks
 Frequency accuracy – hitting the mark
 Jitter / Phase noise performance
 Size / Density / Power
 Bridging interface differences – formats / voltages
 Signal Integrity & EMI Control
4
Silicon Labs Timing Product Toolbox
Any frequency on any output
Low jitter, GbE and PCIe Gen 1/2/3 compliant
Standard and custom LVCMOS/differential clocks
Tiny Clock - smallest, lowest power!
Clock
Buffers
Ultra low jitter fan out (150fs RMS)
Differential / single-ended level translation
Zero delay buffers w/industry-standard footprint
PCIe Buffers
Jitter
Attenuating
Clocks
Ultra low jitter (0.3ps RMS)
Any-frequency translation
Low loop bandwidths (down to 4Hz)
1-PLL and 4-PLL options
XO/VCXO
2 week lead times, any frequency (100kHz–1.4GHz)
Ultra low jitter (0.3ps RMS)
Multi-frequency operation (dual, quad, I2C)
Si51x
Si53x
Si55x
Si57x
Si59x
Silicon
Oscillators
Quartz XO replacement (0.9 - 200MHz)
Cost effective CMOS and differential oscillators
Highly reliable, all silicon design (no moving parts)
Si500
Oscillators
JA Clocks
Clocks
Clock
Generators
5
Si533x
Si535x
Si5214x
Si5121x
Si5330
Si5335
Si5315x
Si537x
Si536x
Si532x
Si531x
Silicon Labs Clock Generator Toolbox
Any frequency on any output
Low jitter, GbE and PCIe Gen 1/2/3 compliant
Standard and custom LVCMOS/differential clocks
Tiny Clock - smallest, lowest power!
Clock
Buffers
Ultra low jitter fan out (150fs RMS)
Differential / single-ended level translation
Zero delay buffers w/industry-standard footprint
PCIe Buffers
Clocks
Clock
Generators
 Programmable Clock Generators – Si533x, Si535x
 Factory programmed – fixed or pin controlled – Web or Desktop tools
 I2C programmable
 PCI Express Clock Generators – Si5335, Si5214x
 Gen 1.1, 2.1, 3.0 compliant
 2,4,6, 9 output versions
 Tiny Clock Generator – Si5121x
 Smallest, lowest power clock generator with big clock features
 Clock Buffers – Si5330, Si5335, Si5315x
6
 Low additive jitter
 Output format flexible
Si533x
Si535x
Si5214x
Si5121x
Si5330
Si5335
Si5315x
Programmable Clock Generators
Si5338/Si5334
Si5350/Si5351
 Generates any combination of output frequencies
 Exact frequency synthesis with 0 ppm error
 Supports LVCMOS (Si535x) to 200MHz and Differential (Si533x) to 710MHz
 Replaces multiple discrete XOs, clocks & level shifters




Minimizes BOM cost and complexity, improving reliability
Standard and factory-customized I2C and pin-controlled clocks
Any format on any output (LVPECL, LVDS, HCSL, LVCMOS @ 1.8, 2.5, 3.3V)*
Web-based utility simplifies device customization (2 week lead time)
*Si535x LVCMOS outputs only
Perfect for replacing misc. discrete XTALs, XOs, and Clocks
7
Si5350/51 Any-Frequency CMOS Clock
 Generates up to 8 non-integer related frequencies
 Any frequency from 8 kHz to 160 MHz
 LVCMOS/LVTTL compatible outputs
 Any voltage: 1.8, 2.5, or 3.3V
 Low period jitter: 100 ps pk-pk
 Any output can be synchronized to xtal, clk, or Vc input
 Configurable SSC per output
 Accepts 25/27MHz xtal or 10-100 MHz clock input
 Configurable control pins: OE, PDN, FS,
 Glitchless frequency shifting for audio/video clocking,
power saving, frequency margining
8
 Si5351 is I2C programmable, Si5350 Web-customizable
with 2 week lead times.
 Exact frequency synthesis: 0 ppm error
SS_EN, LOL
 Small size: 4x4 mm 20-QFN,
24-QSOP, 10-MSOP
Si5350/51 Dynamic Frequency Switching
Example: DF = from 10 to 15 MHz
 Glitchlessly switches between multiple output frequencies on each output
 Increases system performance and minimizes power consumption




Enables easy processor overclocking to improve CPU performance
Improves audio DAC operation during sampling rate changes: no “popping”
Simplifies processor setup and hold time margin testing
Enables board-level power management through clock frequency reduction
2
 Available via pin control (Si5350) or I C control (Si5351)
9
Si5335 Quad Clock Generator/Buffer Overview
Osc
VDDO0
PLL Bypass
CLK0A
÷MultiSynth0
XA / CLKIN
XB / CLKINB
CLK0B
PLL
PLL Bypass
OEB0
CLKIN
VDDO1
CLK1A
÷MultiSynth1
CLK1B
P1
P2
P3
P4
P5
P6
Programmable
Pin Function
Options:
PLL Bypass
OEB1
VDDO2
CLK2A
÷MultiSynth2
OEB0/1/2/3
OEB_all
SSENB
FS[1:0]
RESET
Control
PLL Bypass
CLK2B
OEB2
VDDO3
CLK3A
÷MultiSynth3
CLK3B
LOS
 Generates any frequency, format, voltage on each output
 Any frequency from 1 to 350 MHz
 Any format: CMOS, LVDS, LVPECL, HCSL, CML
 Any voltage: 1.5, 1.8, 2.5, or 3.3V
OEB3
 PCIe Gen 1/2/3 compliant jitter
 1 ps rms phase jitter (12 kHz to 20 MHz)
 2 LBW options: 1.6 MHz & 475 kHz
 Web ClockBuilder configurable, including PLL bypass mode  Core VDD: 1.8 or 2.5 or 3.3 V
 FS pins support up to 3 unique profiles per device
 Low core power: 45 mA, –40 to +85 oC
 Master or per bank OE control pins
 4x4 mm 24-QFN
10
Web-Customizable Clocks
 ClockBuilder web utility enables
simple device customization
 Three unique frequency profiles per device
 Any frequency, any format on any output
 Any format or supply voltage on each output
 Synchronous or free-run operation
 Loop bandwidth selection (LBW)
 Spread spectrum clocking (SSC)
 Frequency profile select (FS)
Example:
CLK 0
CLK 1
CLK 2
CLK 3
LBW
SSC
Profile #1
100 MHz HCSL
125 MHz LVDS
200 MHz CML
25 MHz CMOS
1.6 MHz
On
 Benefits
 Single Si5335 reusable across multiple designs
 AVL simplification and consolidation
Samples ship within 2 weeks
11
Profile #2
50 MHz CMOS
50 MHz CML
200 MHz LVDS
33.33 MHz LVDS
475 kHz
Off
Profile #3
125 MHz LVDS
74.25 MHz CMOS
74.1758 MHz CML
312.5 MHz LVDS
1.6 MHz
On
Si5121x Low Power Tiny Clock
Device
Package
Output
Freq .
(MHz)
Inputs /
Max #
Outputs
VDD
Si51210
6 TDFN
1.4x1.2mm
3-200
1/2
2.5-3.3V
Si51211
8 TDFN
1.6x1.4mm
3-200
1/3
2.5-3.3V
Si51214
6 TDFN
1.4x1.2mm
3-133
1/2
1.8V
Si51219
8 TSSOP
3-200
1/3
2.5-3.3V
 Industry’s smallest, lowest power programmable clock (1.2x1.4mm, 2.5 mA typ)
 Factory customized frequencies and control pins
 1-3 LVCMOS outputs from 3 to 200 MHz
 8 to 48 MHz crystal or 3 to 166 MHz clock input
 Optional center Spread Spectrum (±0.25 to ±1.0%)
 4 tr/tf options per output
 Independent 1.8 to 3.3V VDDO (Si51211/19)
 Custom samples in two weeks
12
Lowest Power Factory-Configurable Clock
 Ultra-low supply current = extended battery life
 High-performance, low-power PLL core consumes only
1.5 mA
 6 mA typical with 3 clock outputs
 Up to 60% lower power than competing clock
solutions
 Supports wide range of supply voltage
 1.8 V VDD (Si51214)
 2.5–3.3 V VDD (Si51210/Si51211/Si51219)
 Optional OE pin to turn off unused clock output for
additional power saving
13
Competitive Analysis
Vendors
Si51211
IDT
PhaseLink
AKM
8-pin TDFN
1.4 mm x 1.6 mm
8-pin SOIC
6 mm x 4.9 mm
8-pin MSOP
3 mm x 4.9 mm
8-pin USON
2 mm x 2 mm
6 mA
14 mA
15 mA
7 mA (2 outputs)
Max clock outputs
3 LVCMOS
3 LVCMOS
3 LVCMOS
Output frequency range
3-200 MHz
0.25-200 MHz
<200 MHz
fixed
Input clock range
Crystal: 8-48 MHz
CLKIN: 3-166 MHz
Crystal: 5-27 MHz
CLKIN: 2-50 MHz
Crystal: 10-75 MHz
CLKIN: <200 MHz
CLKIN = 36 MHz
Programmability
OTP
OTP
OTP
Mask
Programmable input pin
2
0
1
0
Output drive strength options
4
1
2
1
150 ps pk-pk
200 ps pk-pk
N/A
200 ps pk-pk
YES
VDD = 1.8 V, 2.5-3.3 V
VDDO = 1.8 V, 1.8-3.3 V
YES
NO
VDD = 3.3 V
VDD = 2.5-3.3 V
NO
VDD = 1.8 V
VDDO = 1.8 V, 3.0 V
Specs
Package size
Supply current (3 outputs)
Jitter Performance
Configurable Spread Spectrum
Voltage
2 LVCMOS
The Si512xx is the industry’s smallest, most power efficient clock
without trading off performance or configurability
14
Si5121x Features and Benefits Summary
Key Feature
15
Benefits
Customer Advantage
 Very low power
consumption



Consumes less power
Generates less heat
Contributes to the green initiative in the
system level


Extends battery life
Lowers cost
associated with heat
sink/cooling fans
 Ultra-small
package with
multiple output

Addresses need for small footprint in
portable applications
More board space for easier layout
Saves PCB space
BOM consolidation


Reduces board cost
Simplifies board
design
Simplifies supply
chain management
 Short lead time for
custom
configuration
through factory
OTP programming


Reduces customer development cycle
Accommodates midstream design or
component changes

 Spread-spectrum
clock (SSCG)
generation and
programmable
drive strength

Cost effective solution for EMI-sensitive
applications
Provides EMI reduction assurance
Improves signal integrity









Improves time to
market
Improves inventory
management
Saves total system
cost
Reduces time to
market
Si5214x/Si5315x PCIe Clocks/Buffers
Si52144―PCIe Clock Generator
Si53154―PCIe Clock Buffer
 PCIe Gen 1, 2, & 3 compliant
 PCIe Gen 1, 2, & 3 compliant
 <0.50 ps RMS Phase Jitter (Gen 3)
 <0.10 ps RMS Phase Jitter (Gen3)
 Available in 2, 4, 6, or 9 output options
 Available in 2, 4, 6, or 9 output options
 Low power: <50mA (max) for 4 outputs
 Low power: <30mA (max) for 4 outputs
 Accepts 25 MHz crystal or clock input
 Accepts 90 to 210 MHz external clock
 No external termination resistors required
 No external termination resistors required
 I2C interface for signal tuning
 I2C interface for signal tuning
 Output Enable for each output CLK
 Output Enable for each output CLK
16
Level Translating Clock Buffers
 Versatile, low-jitter clock buffers




1:4 LVPECL, LVDS, HCSL support
1:8 CMOS, HSTL, SSTL support
Clock distribution of frequencies up to 710 MHz
Low jitter 150 fs RMS typical (12kHz – 20MHz)
 Integrated output format and voltage level translation
 Differential-to-CMOS or CMOS-to-differential
 Independent input/output 1.8V, 2.5V, 3.3V voltage levels
Si5330 eliminates need for additional output & level translators
17
www.silabs.com
Consumer/Embedded Applications
and Solutions
Example Application – HDTV
Free-running
Clocks
Input Options
Si5350/51
XA
Crystal:
25 – 27 MHz
PLL
OSC
CLK0
125 MHz
CLK1
48 MHz
Multi
Synth
2
CLK2
28.322 MHz
Multi
Synth
3
CLK3
Multi
Synth
0
XB
Multi
Synth
1
Multi
Synth
4
Optional:
Clock:
10 – 100 MHz
or
Analog Control Voltage:
10 – 1000 ppm
PLL
Multi
Synth
5
Multi
Synth
6
Control
Pin
(Si5350)
Multi
Synth
7
Ethernet
PHY
USB
Controller
HDMI
Port
28.322 MHz
HDMI
Port
CLK4
74.25 MHz
- or CLK5
74.25/1.001 MHz
CLK6
22.5796 MHz
CLK7
24.576 MHz
Video/Audio
Processing
- or Synchronous
Clocks
I2C
(Si5351)
 Any output can be synchronized to either PLL
 Enables simultaneous synchronous + asynchronous operation
 System and peripheral clocks can be generated by a single device
 Enables BOM consolidation and cost reduction
19
Clkin
Broadband Gateway Solution
 Application Processor / SoC clock expansion
 Used in conjunction with Application Processor for feature expansion
 Uses external clock input (optional)
20
PCIe Refclk (100 MHz, 3.3V HCSL)
PCIe Refclk (100 MHz, 3.3V HCSL)
Phy Clk (125 MHz, 2.5V LVDS)
Display Clk (27 MHz, LVCMOS)
FPGA/ASIC Clk (200 MHz, 2.5V LVDS)
PCIe
Switch
FPGA /
ASIC
CPU Clk (100 MHz, 1.8V LVDS)
DDR Clk (166 MHz, 1.8V LVDS)
Audio Clk (28.224 MHz, LVCMOS)
DSP /
CPU
SDI Clk (147.456 MHz, 3.3V LVDS)
Video
 Before - 8 Oscillators, 1 discrete PLL
Si5338 Si5335
Video Conferencing System
Si5317
PCIe
Switch
FPGA /
ASIC
DSP /
CPU
Video
 After - 2 Clock Gen, 1 JA Clock
 Embedded systems…
 May use many clocks (9 here) with differing requirements (SE/Diff/VDD)
 Might require clocks generated on-board or sourced external to system
 Are an ideal application for clock integration using clock generators!
21
PCIe Add-On Card
Before
After (w/Si5335)
Si5335 PCIe RefClk Generation - Jitter Test Comparison
(When locked to external clock source)
Jitter Tool Test Name
Test Ext Clock
limit
Jitter Pass/
HF/LF (ps)
(ps)
Fail
Typical PCIe
Si5335
Clock
w/475 kHz
Generator Pass/
BW
Pass/ Si5335
(ps)
Fail
(ps)
Fail Margin
PCIE_1_1 (J pk-pk)
HF
86.0
128.67
F
111.28
F
22.52
P
74%
PCIE_2_0_5MHZ_1_5M_H3_FIRST (J rms)
HF
3.1
8.87
F
7.35
F
1.05
P
66%
PCIE_2_0_5MHZ_1_5M_H3_FIRST (J rms)
LF
3.0
5.60
F
4.85
F
0.94
P
69%
PCIE_2_0_5MHZ_1_5M_H3_STEP (J rms)
HF
3.1
9.98
F
8.11
F
1.07
P
65%
PCIE_2_0_5MHZ_1_5M_H3_STEP (J rms)
LF
3.0
3.80
F
3.44
F
0.92
P
69%
PCIE_2_0_8MHZ_1_5M_H3_FIRST (J rms)
HF
3.1
6.77
F
5.86
F
0.78
P
75%
PCIE_2_0_8MHZ_1_5M_H3_FIRST (J rms)
LF
3.0
3.01
F
2.77
P
0.44
P
85%
PCIE_2_0_8MHZ_1_5M_H3_STEP (J rms)
HF
3.1
7.44
F
6.35
F
0.82
P
74%
PCIE_2_0_8MHZ_1_5M_H3_STEP (J rms)
LF
3.0
1.35
P
1.30
P
0.36
P
88%
PCIE_3_0_2MHZ_4M_H3_FIRST (J rms)
HF
1.0
2.19
F
1.87
F
0.31
P
69%
PCIE_3_0_2MHZ_5M_H3_FIRST (J rms)
HF
1.0
1.60
F
1.43
F
0.24
P
76%
 Si5335 reduces BOM, saves PCB area, increases performance
 Provides >70% margin to PCIe Gen 1/2/3 specifications
22
Si512xx Tiny Clock Target Applications
Segment
Consumer






Digital camera/camcorder
Smartphone
Set-top box
Blu-ray player/recorder
Console/Mobile gaming
Home media
Enterprise




Video conferencing
Office automation
IP phone/VoIP
Projectors
Embedded





In-vehicle infotainment
Navigation
Medical equipment
POS
Smart meter
Computation
Communications
23
Application
 Graphics cards
 EPON/GPON
 Gateway
 Routers/Switches
Si512xx Reduces BOM Cost and Board Space
Multiple Crystals and Oscillators
Traditional Solution
Silicon Labs Si512xx
• Multiple discrete crystals
and/or oscillators


Up to 80% board space savings
Single IC solution reduces BOM cost, supply chain complexity
• One output per device
with fixed frequency


Up to three outputs per device
Selectable frequencies increases flexibility (FSEL input pin)
• No spread-spectrum
clock capability

Configurable SSCG for EMI reduction

Configurable slew rate for EMI reduction and signal integrity
improvement
• Fixed output slew rate
24
Single Silicon
Labs Si52111
Digital Still Camera
Si51210
 PLL frequency synthesis of CCD clocks
Si51211
 Generation of multiple system frequencies (3)
Tiny Clock saves space, reduces BOM, and lowers power
consumption!
25
Laser Printer
 Si51219 in Laser Printer
 Supplies all system clocks in single, extremely small package
 Provides Spread Spectrum Clocking to reduce EMI (radiated emissions)
26
www.silabs.com
Signal Integrity and EMI Control
Programmable Output Drive Strength
Si5121x Programmable Output Drive Strength
 Programmable output drive strength improves signal integrity and
EMI optimization
 Four levels of drive strength for each output
 Reduces clock overshoot/undershoot caused by impedance mismatch
 Adjusts clock output slew rate for lower EMI
28
EMI Reduction Using Spread Spectrum Clocking
 Reduces EMI by spreading the power among adjacent frequencies
 Center and down spread support
 0.1% to >2.5% spread in 0.1% increments
 SSC enable pin
 SSC configurable per output
SSC Features supported by Si533x/5x
29
Reduce EMI—Spread Spectrum Clocking
 Spread spectrum reduces
source-clock EMI
 Reduces radiated energy at the
fundamental and harmonics
 Si5121x offers factory-configurable spread profiles
 Center spread profiles ranging from ±0.25 to ±1.0%
 Modulation rates from 16 to 150 kHz
 Excellent solution for standalone EMI reduction clock
 Inserting Si5121x in clock lines to quickly solve EMI failure
 Ultra small package requires minimum board space to implement
SSC Features supported by Si5121x
30
Reduce EMI—Differential Skew Adjust
Example of mismatched differential edge rate and signal skewing
 Mismatches in differential signal skew and edge rate produce common
mode energy spikes causing EMI and potential data loss
 Using I2C control on each output, Silicon Labs PCIe solutions reduce EMI,
adjust cross points and improve signal integrity with independent, true or
compliment edge rate and skewing
Feature on Si5214x PCIe Clock Generator
Resolves EMI or signal integrity issues without PCB spins
31
www.silabs.com
Tools & Support
www.silabs.com/Timing
 Parametric Search
 Reference Designs
 Tech Support
 Selector Guides
 Datasheets/App notes
 Development Tools
 Timing Software
 Cross Reference
 White Papers
 Eval Boards
33
Custom Timing Design Services
 Custom XO/VCXO
 Custom Clocks
 Clock Tree Design
Recommendation
http://www.silabs.com/custom-timing
34
www.silabs.com
PCI Express Timing Solutions
for Consumer and Embedded Applications
PCI Express Physical Link
PCI Express Standards
36
Generation
Date
Bit Rate
Coding
Data Rate
(per Lane)
1.1
2003
2.5 Gbps
8B/10B
500 MBytes/s
2.1
2007
5.0 Gbps
8B/10B
1 GBytes/s
3.0
2010
8.0 Gbps
128B/130B
~2 GBytes/s
PCI Express Timing—RefClk Architectures
PCIe RefClk
PCIe RefClk
 PCIe RefClk
 Common Clock Rx is most commonly
used clocking architecture
 Spec is 100 MHz HCSL
 Multiplied up in Tx/Rx PLL to
 2.5 GHz, 5.0 GHz, or 8 GHz
 Jitter performance is critical
 125 MHz or 250 MHz used in special
cases
37
PCIe RefClk
RefClk Jitter Measurement
 Calculating acceptable RefClk jitter is complex




Varies for each PCIe generation (spec version 1.1, 2.1, 3.0)
Function of clocking architecture and PLL transfer functions
Result is multiple jitter masks
Find “worst case” mask combinations
 RefClk jitter measured using Intel Jitter Tool v 1.6.4




Capture clock waveform on high speed oscilloscope
Clock waveform capture must contain minimum number of sample intervals
Clock waveform capture post-processed by Jitter Tool
Jitter calculated based on transfer function criteria in PCIe spec (jitter mask)
 PCIe RefClk Jitter measurements are NOT 12Khz – 20MHz
 Each revision uses transfer functions as defined in PCIe spec
 Transfer functions define bandwidths and jitter masks
38
RefClk Jitter Measurement—Gen 1.1
 Intel PCIe Clock Jitter Tool
Ver. 1.6.4
 Approved by PCI-SIG
 Used by vendors in
characterization
39
RefClk Jitter Measurement—Gen 3.0
 Intel PCIe Clock Jitter Tool
Ver. 1.6.4
 Approved by PCI-SIG
 Used by vendors in
characterization
40
PCIe RefClk Design Timing Challenges
 Multiple clock support – RefClk + other clocks
 Board space / integration / power consumption
 Meeting jitter spec requirements (Gen 1.1, 2.1, 3.0)
 Jitter design margin (important)
 HCSL clock termination / signal interfacing
 EMI mitigation – especially in multi-clock designs
41
www.silabs.com
Silicon Labs PCI Express Timing
Solutions
Introducing the PCIe Clock Gen/Buffer Family
 Fully compliant to PCIe 1.1, 2.1 and 3.0
 Backward compatible to previous PCIe generations
 2, 4, 6 or 9 output options, all equipped with output enable (OE)
 Superior to incumbent solutions in all key parameters





>50% lower power than IDT and other solutions
>50% lower jitter than PCIe 3.0 jitter requirements
Reduces BOM by up to 37 components
Reduces required board space by >50%
Provides I2C-signal tuning for improved data integrity, EMI
compliance and ease of design
 Provides additional 25 MHz buffered output clock
Si5214x PCIe
Clock Generator
 Available off-the-shelf and in mass production
43
 24-QFN 4 mm x 4 mm (2 or 4 outputs)
 32-QFN 5 mm x 5 mm (6 outputs)
 48-QFN 6 mm x 6 mm (9 outputs)
Si5315x PCIe
Clock Buffer
PCIe Block Diagrams and Overview
Si52144 – PCIe Clock Generator
 Low Power: <50 mA (max) for 4 output
device (fully loaded)
 Low Power: <30 mA (max) for a 4 output
device (fully loaded)
 Small footprint packages
 Small footprint packages
 2, 4, 6 or 9 OE outputs
 2, 4, 6 or 9 OE outputs
 No external termination or current resistors
required
 No input/output termination or current
resistors required
 I2C interface for signal tuning
 I2C interface for signal tuning
 Accepts 25 MHz crystal or external clock
 Accepts 90–210 MHz external clock
 Provides 25 MHz LVCMOS buffered
reference clock (Si52142/3)
44
Si53154 – PCIe Clock Buffer
Reduced BOM Cost and Smaller Footprint
Incumbent solutions
4 resistors required per output pair
Required
current source
resistor
Silicon Labs Si5214x and Si5315x
No resistors required
4 required
resistors per
output pair
 Reduced component count and BOM cost
 Fully integrated termination resistors on all PCIe outputs
 No current reference resistors needed
 Reduced board design complexity
Saves 37 resistors for a nine output device
and reduces system layout complexity
45
PCIe Solution Comparison
Board space
reduction and
BOM savings
Incumbent Solutions
Limitations




46
Silicon Labs Solution
Advantages
Large BOM and board space requirement  2x lower power consumption
High power consumption
 Reduces BOM count by up to 37
resistors
Sub-optimal cost
 2 to 9 output options
Limited configurability
 I2C configurable signal tuning
 Supports all PCIe generations
50% Jitter Performance Margin
Clock Jitter Tool Image Shots
PCI SIG jitter
requirement
0.37190
1.00000
Si5214x jitter performance
 Si5214x RMS phase jitter performance exceeds PCIe 3.0
requirement by more than 50%
Provides higher data integrity
and increased system reliability margin
47
Reduced EMI
Example of mismatched differential edge rate and signal skewing
 Mismatches in differential signal skew and edge rate produce common
mode energy spikes causing EMI and potential data loss
 Using I2C control on each output, Silicon Labs PCIe solutions reduce EMI,
adjust cross points and improve signal integrity with independent, true or
compliment edge rate and skewing
Quickly resolves last minute EMI or signal integrity issues
without PCB spins
48
Si5214x and Si5315x Key Features/Benefits
Key Feature
Customer Benefits
Performance
 2x lower power consumption than competition
 Up to 50% RMS phase jitter margin
 Supports customer “green initiatives”
 Helps reduce dependency on cooling fans
 Higher system reliability
Integration
 Fully integrated termination resistors on PCIe outputs
 No current reference resistor needed
 Available 25 MHz buffered reference output clock
 Eliminates four resistors per output pair and
a current reference resistor
 Saves board space and BOM cost
Signal Integrity Tuning
 Independent, true or complement edge rate control
 Independent, true or complement skew control




Easy to use
 Individual output enable
 Spread spectrum enable
 Simplifies power management
 Simplifies EMI and RFI compliance
Allows signal integrity optimization
Helps in EMI and RFI compliance
Allows fast time-to-market
Helps resolve late development
changes/issues
Outstanding solution for PCIe system design!
49
Competitive Comparison
Vendors
Silicon Labs
Si52143
IDT
Competitor 2
Competitor 3
Quad PCIe output maximum IDD (mA)
60
125
120
170
PCIe Gen1, 2, 3 compliant
Yes
Yes
Yes
No
Requires external termination resistors
(4 per output pair)
No
Yes
Yes
Yes
Requires an IREF Resistor
No
Yes
Yes
Yes
Offers both clock generators and buffers
with more than 4 PCIe outputs
Yes
Yes
No
No
Configurable skew controls
Yes
No
No
No
Configurable edge rate controls
Yes
No
No
No
25 MHz buffered reference clock
Yes
Yes
No
Yes
Specs
Footprint
24-QFN
(4 mm x 4 mm)
28-TSSOP
20-TSSOP
(9.7 mm x 4.5 mm) (6.5 mm x 4.5 mm)
32-QFN
(5 mm x 5 mm)
Silicon Labs PCIe products offer advantages over incumbent
solutions
50
Si5335 PCIe Clock Generator/Buffer
Si5335 – PCIe Clock Generator/Buffer
Osc
VDDO0
PLL Bypass
CLK0A
÷MultiSynth0
XA / CLKIN
XB / CLKINB
CLK0B
PLL
PLL Bypass
OEB0
CLKIN
VDDO1
CLK1A
÷MultiSynth1
CLK1B
P1
P2
P3
P4
P5
P6
Programmable
Pin Function
Options:
PLL Bypass
OEB1
VDDO2
CLK2A
÷MultiSynth2
OEB0/1/2/3
OEB_all
SSENB
FS[1:0]
RESET
Control
PLL Bypass
CLK2B
OEB2
VDDO3
CLK3A
÷MultiSynth3
CLK3B
LOS
 Generates any frequency, format, voltage on each output
 Any frequency from 1 to 350 MHz
 Any format: CMOS, LVDS, LVPECL, HCSL, CML
 Any voltage: 1.5, 1.8, 2.5, or 3.3V
 Web configurable, including PLL bypass mode
 Up to 3 unique profiles per device
 GbE and PCIe Gen 1/2/3 compliant jitter
 Optional PCIe jitter cleaning (475 kHz LBW)
51
OEB3
PCIe Add-On Card with Si5335
Before
After (w/Si5335)
Si5335 PCIe RefClk Generation - Jitter Test Comparison
(When locked to external clock source)
Jitter Tool Test Name
Test Ext Clock
limit
Jitter Pass/
HF/LF (ps)
(ps)
Fail
Typical PCIe
Si5335
Clock
w/475 kHz
Generator Pass/
BW
Pass/ Si5335
(ps)
Fail
(ps)
Fail Margin
PCIE_1_1 (J pk-pk)
HF
86.0
128.67
F
111.28
F
22.52
P
74%
PCIE_2_0_5MHZ_1_5M_H3_FIRST (J rms)
HF
3.1
8.87
F
7.35
F
1.05
P
66%
PCIE_2_0_5MHZ_1_5M_H3_FIRST (J rms)
LF
3.0
5.60
F
4.85
F
0.94
P
69%
PCIE_2_0_5MHZ_1_5M_H3_STEP (J rms)
HF
3.1
9.98
F
8.11
F
1.07
P
65%
PCIE_2_0_5MHZ_1_5M_H3_STEP (J rms)
LF
3.0
3.80
F
3.44
F
0.92
P
69%
PCIE_2_0_8MHZ_1_5M_H3_FIRST (J rms)
HF
3.1
6.77
F
5.86
F
0.78
P
75%
PCIE_2_0_8MHZ_1_5M_H3_FIRST (J rms)
LF
3.0
3.01
F
2.77
P
0.44
P
85%
PCIE_2_0_8MHZ_1_5M_H3_STEP (J rms)
HF
3.1
7.44
F
6.35
F
0.82
P
74%
PCIE_2_0_8MHZ_1_5M_H3_STEP (J rms)
LF
3.0
1.35
P
1.30
P
0.36
P
88%
PCIE_3_0_2MHZ_4M_H3_FIRST (J rms)
HF
1.0
2.19
F
1.87
F
0.31
P
69%
PCIE_3_0_2MHZ_5M_H3_FIRST (J rms)
HF
1.0
1.60
F
1.43
F
0.24
P
76%
 Si5335 reduces BOM, saves PCB area, increases performance
 Provides >70% margin to PCIe Gen 1/2/3 specifications
52
Industry’s Most Complete PCIe Offering
Si5338
Power & Features
(Off-the-shelf)
FPGA, Switches, routers,
infrastructure, GPON/EPON,
network servers telecom PBX,
WAN
Si5335
(Web Customizable)
Enterprise: Blade servers, storage, printer/
Si5213x
(Factory Customizable)
Si5214x / Si5315x
(Off-the-shelf)
PCIe Gen2
53
Telecom/Datacom:
PCIe Gen3
copiers, MFP, teleconferencing
Embedded: IPC, surveillance, gaming
machines, POS, digital signage, automation,
computing, medical equipment, test, military,
mobile/in-vehicle computing
Datacom/CPE: gateway, wireless AP
Consumer: Set-top boxes/DVR, Blu-ray
recorders
< 1ps RMS
Performance
Industry’s Most Complete PCIe Offering
 Up to 4 differential multi-format outputs
or 8 CMOS outputs
Si5338
 I2C programmable
 Spread spectrum clocking (SSC) per clock
 ClockBuilder Desktop configuration
Power & Features
(Off-the-shelf)
Si5335
(Web Customizable)
Si5213x
(Factory Customizable)




Up to 12 PCIe or 13 LVCMOS, and other mixed combos
Factory customizable
Programmable AC Tuning
Configurable control pins
Si5214x / Si5315x
(Off-the-shelf)
PCIe Gen2





Up to 9 PCIe Gen3 HCSL format outputs
Ultra low power
Low cost
Output enable and spread spectrum control pins
Off-the-Shelf
PCIe Gen3
Performance
54
 Up to 4 differential multi-format outputs or 8
CMOS outputs
 User-programmable spread spectrum, output
enable pins, & frequency plan selection
 ClockBuilder Web configuration
< 1ps RMS
Silicon Labs Complete PCIe Portfolio
Part Number
Si5214x – NEW
PCIe Clock Generator
[off-the-shelf]
Si5315x – NEW
PCIe Clock Buffer
[off-the-shelf]
Si5213x
PCIe and LVCMOS
Clock Generator
[customizable]
Si5335/Si5338
Clock Generator
[customizable]
Description
Targeted Segments
•
•
•
•
•
•
Ultra-low power
• Consumer – PC, laptop, home
Small packages
gateway, STB, DVR, PCs, Blu-ray,
2, 4, 6 or 9 outputs
remote storage, etc…
I2C configurable signal tuning • Datacom / CPE – wireless APs,
Low-cost offering
gateways, routers, Wi-Fi, etc…
25 MHz buffered output clock • Embedded – gaming, computing,
test, in-vehicle, POS, remote
cameras, IPC, endless devices…
• Mix of up to 12 PCIe or 13
• Enterprise – blade servers,
LVCMOS outputs
storage, multi-function printers /
• Mid-range cost
copiers, teleconferencing
• Customizable control pins
• Mix of PCIe HCSL, LVDS and • Telecom/Datacom – FPGA,
LVPECL outputs
switches, routers, PBX,
• Any frequency, any output
infrastructure, GPON/EPON
• Customizable control pins
•Partial table of parts shown. Full listing available at www.silabs.com/pci-express-clocks
Silicon Labs offers PCIe-compliant parts across all sectors
from ultra-high performance to value based
55
Comprehensive Timing Portfolio
 Silicon Labs is a one-stop-shop
timing solutions provider
 PCIe clock generators/buffers
 Customizable PCIe clock generators/buffers
 Any frequency, any output clocks
generators/buffers
 Clock jitter attenuators and multipliers
 XO/VCXO
 Silicon oscillators
 Silicon Labs advantages
 Industry-leading technology and architectures
 Customizable solutions with short lead times
 Superior performance, competitive pricing
Silicon Labs Timing solutions address all timing
requirements from PCIe to DSPLL oscillators
56
www.silabs.com
Tools and Support
Turnkey Tools Get You Started Today
 Evaluation boards
Device Part
Number
Si52144
Generator
4
24-QFN
Si52144-EVB
MSRP
(USD)
$125
Si52147
Generator
9
48-QFN
Si52147-EVB
$175
Si53154
Buffer
4
24-QFN
Si53154-EVB
$125
Si53159
Buffer
9
48-QFN
Si53159-EVB
$175
Clock Type
# of PCIe
Output
Device
Package
EV Board Orderable
Part number
 Convenient evaluation platform
 Allows measurement of device power consumption
 Allows measurement of PCIe Gen1/2/3 compliancy
 SMA connectors support robust, low jitter signal
integrity measurements
 Output enable (OE) pins for power management
 Spread spectrum control pins for easy EMI control
 Kit contents
 Evaluation board
 EVB user’s guide
58
Si52147 Evaluation Board
Si5214x and Si5315x Selector Guide
Device
PCIe Clock
Type
# of PCIe
Outputs
# of Single
Ended Outputs
Package
Package Size
Si52142
Generator
2
1 (25 MHz)
24-QFN
4 mm x 4 mm
Si52143
Generator
4
1 (25 MHz)
24-QFN
4 mm x 4 mm
Si52144
Generator
4
-
24-QFN
4 mm x 4 mm
Si52146
Generator
6
-
32-QFN
5 mm x 5 mm
Si52147
Generator
9
-
48-QFN
6 mm x 6 mm
Si53152
Buffer
2
-
24-QFN
4 mm x 4 mm
Si53154
Buffer
4
-
24-QFN
4 mm x 4 mm
Si53156
Buffer
6
-
32-QFN
5 mm x 5 mm
Si53159
Buffer
9
-
48-QFN
6 mm x 6 mm
 Other Silicon Labs PCIe and configurable clock and buffer solutions
available at www.silabs.com/pci-express-clocks
59
Sales Tools and Collateral
 Collateral
 Clock and Oscillator Timing Selector
Guide
• Available for download at
www.silabs.com/timing
 Documentation
 Product data sheet
 Application notes
• AN636: Si5214x and Si5315x Signal
Tuning for Improved Connectivity
 EVB user’s guide
 Contributed article: Selecting the
Optimum PCI Express Clock Source
 All docs available for download at
www.silabs.com/pci-express-clocks
60
Si5214x and Si5315x Summary
 More Integrated, lower power and higher performance PCIe Solutions
 50% lower power than IDT and other incumbent solutions
 Significant BOM reduction with no termination resistors or current resistors
 Smallest package on the market
 Robust feature set including I2C configurability for EMI and skew rate controls on
all outputs
 Up to 50% jitter performance margin versus the PCIe 3.0 jitter requirements
 PCI Express Generation 1/2/3 compliance
 2, 4, 6 and 9 output options support a broad range of applications
 Complete PCIe product portfolio addressing all segment
requirements
61
Call to Action
 Engage PCI Express customers w/Silicon Labs PCIe Solutions
 Emphasize:






2x lower power
Small package footprint
Higher integration / Fewer parts / BOM savings
Broad range of PCIe products (Si5214x/5x, Si5335/38)
Low jitter (w/margin) Gen 1/2/3 compliant
Built-in EMI mitigation
 Focus on displacing IDT PCI Express sockets
 Win Designs!
62
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Appendix
Additional Application Examples
Additional Selector Guide Information
RISC Processor NAS Application Example
RISC Processor for NAS
100 MHz
HCSL
PCIe
LAN
USB
100 MHz
HCSL
RISC Processor
AMCC460-EX
Si52144
Memory
100 MHz
HCSL
PCIe SATA
Controller
100 MHz
HCSL
PCIe SATA
Controller
64
Video Surveillance Application Example
Video Surveillance
LAN
Device
Memory
100 MHz
HCSL
Storage Network
Processor
PMC Sierra /
AMCC / Freescale
Si52142
100 MHz
HCSL
65
SATA
Controller
Video
Monitor ASIC
IP Gateway Application Example
IP Gateway
25 MHz
10/100/1000
Switch
Memory
Si52143
MindSpeed
Comcerto 1000
100 MHz
USB
HCSL
MoCA
100 MHz
PCIe
Switching
HCSL
100 MHz
HCSL
PCIe
WLAN Card
2
PCIe
SATA Controller
66
PCIe Clock Generators Selector Guide
Off-the-Shelf PCIe Clock Generators
# of PCIe
Output
# of Single
Ended Outputs
Package
Package
Size
25
2
1 (25 MHz)
24-QFN
4 x 4 mm
PCIe Gen 1/2/3
25
4
1 (25 MHz)
24-QFN
4 x 4 mm
Generator
PCIe Gen 1/2/3
25
4
-
24-QFN
4 x 4 mm
Si52146
Generator
PCIe Gen 1/2/3
25
6
-
32-QFN
5 x 5 mm
Si52147
Generator
PCIe Gen 1/2/3
25
9
-
48-QFN
6 x 6 mm
SL28PCIe14
Generator/
Buffer
PCIe Gen1/2/3
25
4
-
32-QFN
5 x 5 mm
# of PCIe
Output
# of Single
Ended Outputs
Package
Package
Size
Device
Type of Clock
PCIe Compliant
Si52142
Generator
PCIe Gen 1/2/3
Si52143
Generator
Si52144
Crystal/Clock Buffer Input
Input (MHz)
(MHz)
100
Customizable PCIe Clock Generators
Device
Crystal/Clock Buffer Input
Input (MHz)
(MHz)
Type of Clock
PCIe Compliant
Si52131
Generator
PCIe Gen1/2
10-40
-
Up to 4
Up to 3
24-QFN
4 x 4 mm
Si52132
Generator
PCIe Gen1/2
10-40
-
Up to 7/5
Up to 1/5
32-QFN
5 x 5 mm
Si52138
Generator
PCIe Gen1/2
10-40
-
Up to 12/5
Up to 9/13
48-QFN
6 x 6 mm
Si5335
Generator/
Buffer
PCIe Gen1/2/3
350
4
8
24-QFN
4 x 4 mm
Si5334/38
Generator/
Buffer
PCIe Gen1/2/3
710
4
8
24-QFN
4 x 4 mm
67
25/27 (xtal)
5 to 350 (clk)
8 to 30 (xtal)
5 to 710 (clk)
PCIe Clock Buffer Selector Guide
Off-the-Shelf PCIe Clock Buffers
Device
Crystal/Clock Buffer Input
Input (MHz)
(MHz)
# of PCIe
Output
# of Single
Ended Outputs
Package
Package
Size
100 MHz
2
-
24-QFN
4 x 4 mm
-
100 MHz
4
-
24-QFN
4 x 4 mm
PCIe Gen 1/2/3
-
100 MHz
6
-
32-QFN
5 x 5 mm
Buffer
PCIe Gen 1/2/3
-
100 MHz
9
-
48-QFN
6 x 6 mm
Buffer
PCIe Gen 1/2/3
-
<750 MHz
4
8
24-QFN
6 x 6 mm
Generator/
Buffer
PCIe Gen1/2/3
25MHz
100
4
-
32-QFN
5 x 5 mm
Type of Clock
PCIe Compliant
Si53152
Buffer
PCIe Gen 1/2/3
-
Si53154
Buffer
PCIe Gen 1/2/3
Si53156
Buffer
Si53159
Si5330
SL28PCIe14
68
www.silabs.com
Thank You
www.silabs.com/PCIe