An Optimized Integrated QVCO for Use in a Clock Generator
for a New Globally Asynchronous, Locally Synchronous
(GALS) Design Methodology.
Presented By
Dwarakaprasad
Ramamoorthy
Overview

Background

Need for this new design methodology.

Why GALS?

What is novel in this design?

Need for QVCO

Design Strategy

Simulations & Layout

Conclusion
CLOCK GENERATOR
cos wu
Phase
Locked
Loop
sin wt
cos wt
Dual
Sample
& Hold
Multiplier
sin w(t-u)
CDA
Clock
sin wu
Multiplier
Run
SRFF1
Init1!
Init2!
Ref [1]
SRFF2
Done!
Simple Phase Locked Loop
Source: http://www.uoguelph.ca/~antoon/gadgets/pll/pll.html
VCO Core Design
H ( s) 
Gm sL  Rs 
s 2 (LC   s(Rs C   1
A
Vosc
2
VnSAT  VDC - A - V1SAT
V pSAT  V DD - A - V DC
Ref [4]
SIOS (Spiral Inductor On Silicon) Design
Spiral Inductor Parameters
Quantity
Value
D0
Outer area length
320 µm
D0
Outer area width
320 µm
W
Conductor width
18 µm
S
Conductor Spacing
2 µm
N
Number of turns
6
Wn
Return path width
18 µm
Ln
Return path length
120 µm
Ls
Series inductance
7.82 nH
Rs
Series resistance
6.24 Ω
Q
Quality factor
5
Qmax
Maximum quality factor
10
fmax
Frequency at Qmax
1.89 GHz
SRF
Self resonating frequency
4.33 GHz
Symbol
Ref [6], [8]
Inversion Mode (I-MOS) Varactor Design
Ref [9]
Quadrature Generation
Ref [12], [13]
QVCO Simulation Summary
QVCO Performance Summary
Center frequency
618 MHz – 687 MHz
Tuning range
10%
Phase noise
-190 dBc/Hz at 600 MHz
Current consumption at
2.5 V power supply
8.4 mA
Power consumption at 2.5
V power supply
21 mW
Technology
TSMC 0.25 µm, single-poly,
five-metal, 2.5 V CMOS
technology
QVCO Full Custom Layout
Conclusion

A good compromise between area and overall power consumption was achieved.

A prototype quadrature –Gm LC-VCO for 650 MHz was designed in standard 0.25 µm, single-poly,
five-metal, 2.5 V CMOS technology.

A tuning range of 10% was obtained through the use of I-MOS varactors.
Conclusion (Contd.)

SIOS achieving a Q of 5 were also created.

Simulated worst-case phase noise is -190 dBc/Hz at 600 MHz.

Occupies an area of 800 µm X 300 µm (0.24 mm2).

The designed VCO dissipates only 21 mW and operates from a single 2.5 V supply voltage.
Future Work

Incorporate QVCO into PLL Design.

Complete other Clock Generator Modules.
An Optimized Integrated QVCO for Use in a Clock Generator
for a New Globally Asynchronous, Locally Synchronous
(GALS) Design Methodology.
Presented By
Dwarakaprasad
Ramamoorthy