energies
Article
A Riding-through Technique for Seamless Transition
between Islanded and Grid-Connected Modes of
Droop-Controlled Inverters
Shang-Hung Hu 1 , Tzung-Lin Lee 1, *, Chun-Yi Kuo 1 and Josep M. Guerrero 2
1
2
*
Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung 80424, Taiwan;
rabbit17212@hotmail.com (S.-H.H.); tv80256@yahoo.com.tw (C.-Y.K.)
Department of Energy Technology, Aalborg University, Aalborg 9100, Denmark; joz@et.aau.dk
Correspondence: tllee@mail.ee.nsysu.edu.tw; Tel.: +886-7-5252-000
Academic Editor: Chunhua Liu
Received: 31 May 2016; Accepted: 31 August 2016; Published: 9 September 2016
Abstract: This paper presents a seamless transition method for a droop-controlled inverter. The droop
control is suitable to make the inverter work as a voltage source in both islanded and grid-connected
modes, however, the transfer between theses modes can result in a big inrush current that may damage
the system. The proposed method allows the droop-controlled inverter to improve the transient
response when transferring between modes, by detecting the inrush current, activating a current
control loop during transients, and then transferring back to droop-controlled mode smoothly by
using a virtual inductance loop. In addition, a local phase-locked-loop (PLL) is proposed to align the
inverter voltage with the grid in order to reduce the transient current during the transition. Therefore,
the droop-controlled inverter is able to operate in both grid-connected and islanded modes, providing
as well a smooth transition between them, requiring neither synchronization signals nor grid-side
information. The control algorithm and design procedure are presented. Experimental results from
a laboratory prototype validate the effectiveness of the proposed method.
Keywords: droop control; virtual inductance; microgrid; grid-connected; islanded
1. Introduction
Inverter-based distributed power generation systems (DPGSs) have received much attention recently
due to their flexible power-control capability [1,2]. Usually, grid-connected inverters with grid-following
control are used as interfaces between the grid and DPGSs. However, this control approach may suffer
from voltage instabilities, frequency variations, voltage harmonics, and is not able to operate in islanded
mode. Alternatively to the grid-following inverter, the grid-forming one is preferred due to its ability to
provide many ancillary services defined in IEEE Std. 1547 [3], such as load regulation, reactive power
compensation, and power quality improvement. However, IEEE Std. 1547 does not define the operation
of distributed resources (DRs) in intentionally islanded electric power systems (EPSs).
Recently, the term “DR Island System” has been defined by IEEE Std. 1547.4 [4] in order to integrate
various DRs into EPSs with the possibility of operating as a microgrid [5,6]. Four operating modes
are presented: (1) area EPS-connected mode; (2) transition to island mode; (3) islanded mode and
(4) reconnection mode. The first mode referred to as the DR operation described in the original IEEE Std.
1547. In the transition-to-island mode, islanded detection is necessary and then the DR system will
be able to disconnect from the main grid, allowing a safe islanded operation. On the other hand,
in islanded mode the DR operates without the presence of the main grid. Further, in the reconnection
mode the DR should be able to reconnect to the main grid when it is present again. Since the islanding
operation has been clearly defined by the IEEE Std. 1547.4, future electrical system planning should
consider the paralleling issues of islanding generation [5–7].
Energies 2016, 9, 732; doi:10.3390/en9090732
www.mdpi.com/journal/energies
Energies 2016, 9, 732
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In islanded mode, frequency- and voltage-droop controls are often implemented in the local
control of the inverters, which are operated as voltage sources, in order to share real and reactive
powers.
The droop control
method is based on a concept in power system. When AC generator
increase
Energies 2016, 9, 732 2 of 15 output power, the frequency is drooping accordingly [8–10]. On the other hand, in grid-connected
In islanded frequency‐ controlled
and voltage‐droop controls are often implemented in the a
local mode, inverters
aremode, conventionally
as current
sources
[11–14].
Consequently,
complex
control of the inverters, which are operated as voltage sources, in order to share real and reactive system is required in order to accomplish proper transition without undergoing large transient current.
The between
droop control method is based source
on a concept in power system. When in
AC generator Thispowers. transition
voltage
and current
has been
intensively
studied
the
recent years,
increase output power, the frequency is drooping accordingly [8–10]. On the other hand, in grid‐
being difficult to achieve in practice [15–19]. The droop-controlled voltage source inverter has been
connected mode, inverters are conventionally controlled as current sources [11–14]. Consequently, a proposed to operate in both grid-connected and islanded modes without requiring a control transition
complex system is required in order to accomplish proper transition without undergoing large between
current and voltage sources [20]. The virtual inductance concept was proposed to reduce
transient current. This transition between voltage and current source has been intensively studied in the inrush
current when connecting a new voltage source inverter to an existing microgrid [21–23].
the recent years, being difficult to achieve in practice [15–19]. The droop‐controlled voltage source However,
grid synchronization is also required to suppress the peak transient current of the inverter
inverter has been proposed to operate in both grid‐connected and islanded modes without requiring before
mode transition. High inrush current may still appear in the transition from islanded to
a control transition between current and voltage sources [20]. The virtual inductance concept was proposed to reduce the inrush current when connecting a new voltage source inverter to an existing grid-connected
modes due to phase error in the phase-locked-loop (PLL) system or in the voltage
microgrid [21–23]. However, grid is also required to suppress the peak transient sensors,
especially
in case
of low
linesynchronization impedance [15].
current of the inverter before mode transition. High inrush current may still appear in the transition The authors have presented a droop-controlled voltage source inverter (VSI) with a seamless
from islanded to grid‐connected modes due to phase error in the phase‐locked‐loop (PLL) system or transition between islanded and grid-connected operation [24,25], in which riding-through control
in the voltage sensors, especially in case of low line impedance [15]. and virtual inductance concept were proposed to suppress transient current. In this paper, we further
The authors have presented a droop‐controlled voltage source inverter (VSI) with a seamless present
full experimental verification and design guideline. As shown in Figure 1, various inverters and
transition between islanded and grid‐connected operation [24,25], in which riding‐through control localand virtual inductance concept were proposed to suppress transient current. In this paper, we further loads are tied to the PCC (point of common coupling) [26]. The proposed droop-controlled inverter
regulates
the voltage and the frequency of the microgrid, whereas the other inverters are operated
present full experimental verification and design guideline. As shown in Figure 1, various inverters and local loads are tied to the PCC (point of common coupling) [26]. The proposed droop‐controlled as current-controlled
source (grid-following inverter). The solid-state transfer switch (STS) connects
inverter regulates the voltage and the frequency of the microgrid, whereas the other inverters are the microgrid
to the utility through the impedance Zg , which includes both line and transformer
operated as current‐controlled source (grid‐following inverter). The solid‐state transfer switch (STS) impedances.
The inrush current, due to asynchronous operation of STS, is able to be reduced by
connects the microgrid to loop.
the utility through the impedance g, which includes both line and activating
a current
control
A local
PLL is
proposed
in Zorder
to obtain the angle of the grid
transformer impedances. The inrush current, due to asynchronous operation of STS, is able to be voltage, which is used to correct the angle of the droop controller voltage reference. In addition,
reduced by activating a current control loop. A local PLL is proposed in order to obtain the angle of a virtual inductance loop is designed in order to reduce the oscillating current due to the mode
the grid voltage, which is used to correct the angle of the droop controller voltage reference. In transferring
between islanded and grid-connected modes. Based on this algorithm, the transient
addition, a virtual inductance loop is designed in order to reduce the oscillating current due to the current
between
the inverter
the grid
be reduced to
an acceptable
without triggering
mode transferring between and
islanded and can
grid‐connected modes. Based on level,
this algorithm, the protections
of the system. In contrast with those presented in the state-of-the-art [15–18], this algorithm
transient current between the inverter and the grid can be reduced to an acceptable level, without doestriggering protections of the system. In contrast with those presented in the state‐of‐the‐art [15–18], not need to sense the grid-side voltage for phase synchronous, which may be difficult to reach
this algorithm does not need to sense the grid‐side voltage for phase synchronous, which may be if the inverter is far away from the PCC. The method could be extended to inverter-based DPGSs,
difficult to reach if the inverter is far away from the PCC. The method could be extended to inverter‐
in order
to reduce the inrush current and to ride-through grid power-quality events, such as voltage
sagsbased DPGSs, in order to reduce the inrush current and to ride‐through grid power‐quality events, and swells. The paper is organized as follows. Section 2 presents the operation principle of the
such as voltage sags and swells. The paper is organized as follows. Section 2 presents the operation proposed control approach. Section 3 shows the design methodology of the main control parameters.
principle of the proposed control approach. Section 3 shows the design methodology of the main Section 4 presents the experimental results when the inverter transfers from islanded to grid-connected
control parameters. Section 4 presents the experimental results when the inverter transfers from modes.
Section 5 concludes the paper.
islanded to grid‐connected modes. Section 5 concludes the paper. MicroGrid
Droop-controlled VSI
STS
C
Lf
Zg
Utility grid
PCC
DG#1
DG#n
Figure 1. The proposed droop‐controlled voltage source inverter (VSI) inverter in the microgrid system. Figure 1. The proposed droop-controlled voltage source inverter (VSI) inverter in the microgrid system.
Energies 2016, 9, 732
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2. Operation Principle
Energies 2016, 9, 732 Figure
2 shows the power stage of the three-phase three-leg inverter supplied by 3 of 15 a dc-link, and
ended by Energies 2016, 9, 732 an LC filter connected
to a local load (Rab , Rbc , Rac ). The static transfer switch 3 of 15 (STS) connects
2. Operation Principle the local load
to the main grid through the grid impedance (Zga , Zgb , Zgc ). The main power stage
2. Operation Principle Figure 2 shows the power stage of the three‐phase three‐leg inverter supplied by a dc‐link, and parameters are given in Table 1. An effective algorithm is proposed in order to allow the inverter
ended by an LC filter connected to a local load (R
ab, Rbc, Rac). The static transfer switch (STS) connects Figure 2 shows the power stage of the three‐phase three‐leg inverter supplied by a dc‐link, and ride-through
when
transferring
between
islanded
and
grid-connected
modes,
needing for
the local load to the main grid through the grid impedance (Zga, Zgb, Zgc). The main without
power stage ended by an LC filter connected to a local load (R
ab, R
bc, Rac). The static transfer switch (STS) connects parameters are given in Table 1. An effective algorithm is proposed in order to allow the inverter any grid side
information.
This grid is especially
interesting
when
is farpower awaystage from the STS,
the local load to the main through the grid impedance (Zgathe
, Zgb, inverter
Zgc). The main ride‐through when transferring between islanded and grid‐connected modes, without needing for so that noparameters are given in Table 1. An effective algorithm is proposed in order to allow the inverter high-speed communication system is needed between the STS and the inverter control.
any grid side information. This is especially interesting when the inverter is far away from the STS, ride‐through when transferring between islanded and grid‐connected modes, without needing for Figure 3 shows
the proposed overall control diagram of the inverter. Independently from being
so that no high‐speed communication system is needed between the STS and the inverter control. any grid side information. This is especially interesting when the inverter is far away from the STS, connectedso that no high‐speed communication system is needed between the STS and the inverter control. or disconnected
to the main
thediagram inverter
is normally
operated in
droop-controlled
Figure 3 shows the proposed overall grid,
control of the inverter. Independently from being connected or disconnected to the main grid, the inverter is normally operated in droop‐controlled mode (both
switches
SWthe and
SW
are
in
position
1),
and
it
is
able
to
switch
between
droop-controlled
Figure 3 shows proposed overall control diagram of the inverter. Independently from being 1
2
mode (both switches SW
1 and SW2 are in position 1), and it is able to switch between droop‐controlled connected or disconnected to the main grid, the inverter is normally operated in droop‐controlled to riding-through
modes in order
to suppress the inrush current (thus SW1 and SW2 change from
to riding‐through modes in order to suppress the inrush current (thus SW1 and SW2 change from 1 and SW
2 are in position 1), and it is able to switch between droop‐controlled position 1mode (both switches SW
to position 2). With
this order,
the droop control will be operated first, followed by the
position 1 to position 2). With this order, the droop control will be operated first, followed by the to riding‐through modes in order to suppress the inrush current (thus SW1 and SW2 change from riding-through
algorithm.
riding‐through algorithm. position 1 to position 2). With this order, the droop control will be operated first, followed by the riding‐through algorithm. Utility grid
vga Utility grid
Zga
vga
Zga
vgb
Zgb
vgb
Zgb
vgc
Zgc
vgc
Zgc
Droop-controlled VSI
Droop-controlled VSI
STS
STS
iga
iga
igb
Eb
Ea
ioa
Lfa
ia
Ea
ioa
iob
Lfa
Lfb
ia
ib
iob
ioc
Lfb
Lfc
ib
ic
ioc
Lfc
ic
igb
E
igc E b
c
igc E
c
Rbc
Rab
Cbc
Cab
Rbc
Rab
Cbc
Cab
Rac
Vdc
Vdc
Cac
Rac
Cac
Figure 2. Power stage of the VSI and its connection to the utility grid. Figure 2. Power stage of the VSI and its connection to the utility grid.
Figure 2. Power stage of the VSI and its connection to the utility grid. Figure 3. The block diagram of the proposed controller. Figure 3. The block diagram of the proposed controller. Figure 3. The block
diagram of the proposed
controller.
Table 1. Power state parameters.
Table 1. Power state parameters.
Description
Symbol
Value
Unit
Ω
Local Load (per phase) R
load
50 Table
1.
Power
state
parameters.
Description
Symbol
Value
Unit
Filter Inductor f 5 mH Ω
Local Load (per phase) RL
load 50 Filter Capacitance 20 μF Filter Inductor LCf f 5 mH Description
Symbol
Value
Ω
0.2 + j1.885 Grid impedance Zfg Filter Capacitance C
20 μF Local Load (perGrid impedance phase)
RloadZg 0.2 + j1.885 50Ω
Unit
Ω
2.1. Droop Control Lf
Filter Inductor
5
mH
2.1. Droop Control C
Filter
Capacitance
20
µF
As can be seen in Figure 3, inverter output voltage and current are transferred into a stationary f
Grid impedance
Zg
0.2 + j1.885
Ω
frame where the superscripts are denoted as ‘s’. The voltage reference E
dq* is determined according to As can be seen in Figure 3, inverter output voltage and current are transferred into a stationary frame where the superscripts are denoted as ‘s’. The voltage reference Edq* is determined according to 2.1. Droop Control
As can be seen in Figure 3, inverter output voltage and current are transferred into a stationary
frame where the superscripts are denoted as ‘s’. The voltage reference Edq * is determined according
to both active power versus frequency (P-ω) droop and reactive power versus voltage (Q-V) droop.
Both P-ω and Q-V droop equations can be expressed as follows:
Energies 2016, 9, 732
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ω = ωo − m· ( P − Po )
(1)
E = Eo − n· ( Q − Qo )
(2)
where ω o is the nominal frequency, Po is the rated active power, Eo is the nominal voltage, Qo is the
rated reactive power, m is the P-ω droop coefficient, and n is the Q-V droop coefficient.
A low-pass filter (LPF) with a cut-off frequency of 10 Hz is used to filter the ripple components
when calculating P and Q. Moreover, LPF is able to help stabilize the droop control of the proposed
inverter. Note that Q-V droop control is needed just for compensating possible voltage variations in
the grid, thus reducing the amount of reactive power injected according to the maximum allowed
voltage variations [20]. The droop control is suitable to make the inverter work as a voltage source
in both islanded and grid-connected modes. However, the transition between these two modes
may result in high inrush current that may damage the system. The proposed method will allow
the droop-controlled inverter to improve the transient response when transferring between modes,
by detecting the inrush current, activating a current control loop during the transient, and then
transferring back to the droop-controlled mode smoothly by using a virtual inductance loop.
When a droop-controlled inverter operates in islanded mode, the frequency and amplitude are
deviated according to the amount of active and reactive powers delivered by the inverters, as follows:
∆ω = m·∆P
(3)
∆E = n·∆Q
(4)
where ∆ω is the frequency deviation (ω − ωo ), ∆E is the amplitude deviation (E − Eo ), ∆P is the active
power deviation (P − Po ) and ∆Q is the reactive power deviation (Q − Qo ). On the other hand, when
the inverter is operated in grid-connected mode, the frequency and amplitude are fixed by the grid,
so that the delivered active and reactive powers will be Po and Qo if ωo and Eo coincide with the grid
frequency and amplitude. From Equations (3) and (4), power deviations ∆P and ∆Q can be reduced by
using large droop coefficients m and n.
2.2. Multi-Loop Voltage Control
In order to track the voltage reference Edq * generated by the droop control, a multi-loop voltage
control is realized by using a proportional gain kp plus a voltage feedforward, as shown in Figure 3 [21].
Due to the feedforward loop, the output voltage of the inverter can be controlled within an acceptable
steady-state error and a proper transient behavior. In addition, a time-derivative term of the capacitor
voltage is used to reduce the resonance produced by the filter capacitor Cf . Here, a proportional gain
kd is designed to accomplish a critical damped response of the inverter. Finally, the PWM is realized to
produce the switching signals of the inverter. A design example of the multi-loop voltage control will
be introduced in the next section.
2.3. Riding-through Algorithm
When the inverter is transferred from islanded to grid-connected modes, it may suffer from a large
transient current due to the phase difference between Eabc and vg,abc . In order to obtain a seamlessly
transition, we present a control algorithm able to help the inverter to ride through this transient.
Figure 3 shows the proposed control method, including a local phase-lock loop (PLL) [27], a current
control, and a virtual inductance loop. The applied local PLL is shown in Figure 4. The subscript ‘e’
denotes the signal under dq-frame. A PI control is used to determine the phase angle when q-axis
component is controlled to zero. The frequency feedforward term ω ff = 377 is to boost transient
response when the inverter starts operation. A detailed flow chart is given in Figure 5 in order to
illustrate the conditions required during the mode transition. If when closing the STS, the transient
current is large enough being bigger than a certain threshold ITH , then the inverter control will
Energies 2016, 9, 732
5 of 15
temporarily switch to the riding-through mode (SW1 and SW2 will switch to position 2) for a time
interval TRD . During this time period, the inverter is operated in current control mode with zero
current
command (i * = 0) and the PLL updates the reference angle of droop controller to align
inverter
Energies 2016, 9, 732 5 of 15 Energies 2016, 9, 732 5 of 15 voltage with grid voltage even though the output of droop controller is disable. This action will
interval TRD. During this time period, the inverter is operated in current control mode with zero reduce
the phase
difference
the the inverter
and
grid due
to the control uncoordinated
connection.
interval TRD. During this between
time period, inverter is the
operated in current mode with zero current command (i * = 0) and the PLL updates the reference angle of droop controller to align inverter Note current command (i * = 0) and the PLL updates the reference angle of droop controller to align inverter that a short time delay TRD is required for the PLL to reach the steady state. After that, the
voltage with grid voltage even though the output of droop controller is disable. This action will inverter
willwith switch
back
to droop-controlled
modeof (SW
SW2 switch
back This to position
1) with
voltage grid voltage even though the output droop controller is disable. action will 1 and
reduce the phase difference between the inverter and the grid due to the uncoordinated connection. reduce the phase difference between the inverter and the grid due to the uncoordinated connection. a virtual
inductance that starts with a large virtual inductor value and is gradually reduced to a small
Note that a short time delay TRD is required for the PLL to reach the steady state. After that, the Note that a short time delay T[12]:
RD is required for the PLL to reach the steady state. After that, the final value,
expressed
as follows
inverter will switch back to droop‐controlled mode (SW
1 and SW2 switch back to position 1) with a inverter will switch back to droop‐controlled mode (SW1 and SW2 switch back to position 1) with a virtual inductance that starts with a large virtual inductor value and is gradually reduced to a small t
virtual inductance that starts with a large virtual inductor value and is gradually reduced to a small Lv = Lv f − Lvi − Lv f ·e− /τ
(5)
final value, expressed as follows [12]: final value, expressed as follows [12]: ∙
(5) (5) d iqds ∙
VLdqs = Lv
(6) (6)
dt (6) wherewhere L
Lvf and
Lvi are
final and initial inductances, respectively, and τ is the time constant. Thus,
vf and L
vi are final and initial inductances, respectively, and τ is the time constant. Thus, an where Lvf and Lvi are final and initial inductances, respectively, and τ is the time constant. Thus, an an induced
voltage in (6) is produced to react against the transient current. The stability of the inverter
induced voltage in (6) is produced to react against the transient current. The stability of the inverter induced voltage in (6) is produced to react against the transient current. The stability of the inverter can also be improved by means of the virtual inductance loop [23]. can also
be improved by means of the virtual inductance loop [23]. can also be improved by means of the virtual inductance loop [23]. Figure 4. The block diagram of the applied PLL. Figure
4. The block diagram of the applied PLL.
Figure 4. The block diagram of the applied PLL. Figure 5. Flow chart of the proposed control strategy. Figure 5. Flow chart of the proposed control strategy. Figure 5. Flow chart of the proposed control strategy.
3. Main Control Parameter Design 3. Main Control Parameter Design 3. Main Control
Parameter Design
This section is devoted to presenting a design example in order to fix the multiple parameters of This section is devoted to presenting a design example in order to fix the multiple parameters of the proposed control algorithms. The discussion will include the droop coefficients, the parameters This
section is devoted to presenting a design example in order to fix the multiple parameters of
the proposed control algorithms. The discussion will include the droop coefficients, the parameters of the multi‐loop voltage control, and the virtual inductance. of the multi‐loop voltage control, and the virtual inductance. the proposed
control algorithms. The discussion will include the droop coefficients, the parameters of
the multi-loop
voltage control, and the virtual inductance.
3.1. Droop Coefficients 3.1. Droop Coefficients According to droop Equations (1) and (2), the droop coefficients can be designed by using the According to droop Equations (1) and (2), the droop coefficients can be designed by using the root locus method [28]. Considering two inverters are connected in parallel. One is treated as grid root locus method [28]. Considering two inverters are connected in parallel. One is treated as grid Energies 2016, 9, 732
6 of 15
3.1. Droop Coefficients
According to droop Equations (1) and (2), the droop coefficients can be designed by using the
root locus method [28]. Considering two inverters are connected in parallel. One is treated as grid
and the other is droop-controlled inverter. The corresponding equations of the low-pass filter, droop
controller and the angle of voltage are given as:
PLPF =
ωc
ωc
P , Q LPF =
Q
s + ωc ins
s + ωc ins
(7)
ω = ωo − m ( Po − PLPF ) , E = Eo − n ( Qo − Q LPF )
w
ωdt = θ + θo
(8)
(9)
where Pins and Qins are calculated by the measuring inverter output current and output voltage.
Note that is the angle of the voltage E. Thus, the state-space equation of one inverter can be developed
from small signal analysis:

.

X1 = 
.
∆ θ1
..
∆ θ1
.
∆ E1


0
 
= 0
0
1
− ωc
0
 

∆θ1
0
0
.
 

0   ∆θ 1  +  0
0
− ωc
∆E1


0
0


0
  ∆P1  = A1 · X1 + B1 · U1 (10)
∆Q1
− n1 ω c
0
− m1 ω c
0
For two inverters, the equations can be expanded as:
"
.
X=
A1
0
0
A2
#"
X1
X2
#
"
+
B1
0
0
B2
#"
U1
U2
#
= AX + BU
(11)
where U is developed by the Newton-Raphson method:



U=

∆P1
∆Q1
∆P2
∆Q2


 
 
=
 

∂P1
∂θ1
∂Q1
∂θ1
∂P2
∂θ1
∂Q2
∂θ1
∂P1
∂E1
∂Q1
∂E1
∂P2
∂E1
∂Q2
∂E1
∂P1
∂θ2
∂Q1
∂θ2
∂P2
∂θ2
∂Q2
∂θ2
∂P1
∂E2
∂Q1
∂E2
∂P2
∂E2
∂Q2
∂E2


1
 
  0
=
  0

0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1

∆θ1










∆θ 1
∆E1
∆θ2




 = JKX




.
.
∆θ 2
∆E2
(12)
Then the state equation of overall system can be written as:
.
X = AX + BJKX = MX
(13)
The droop coefficients of the inverter which represent utility are set as very small due to their
stiffness. Figure 6 shows the movement of roots when varying the P-ω droop coefficient m value.
Note that the grid is assumed to be a stiff voltage source. As can be seen, the two roots become complex
conjugate when m increases from 0.0001 to 0.1. Note that the system is stable with a damped oscillation
only. Then, we can consider parameter variation in both n and m. Figure 7 shows the roots moving to
the right half-plane when increasing both coefficients. These results show that the system will become
unstable for large n values. Based on the above observation, droop coefficients m and n can be chosen
to achieve an acceptable transient response within the operation range.
Energies 2016, 9, 732
Energies 2016, 9, 732 Energies 2016, 9, 732 7 of 15
7 of 15 7 of 15 Figure 6. Root locus when P‐ω coefficient varies from 0.0001 to 0.1. Figure
6. Root locus when P-ω coefficient varies from 0.0001 to 0.1.
Figure 6. Root locus when P‐ω coefficient varies from 0.0001 to 0.1. Figure 7. Root locus when both P‐ω and Q‐E coefficients vary from 0.0001 to 0.1. Figure 7. Root locus when both P‐ω and Q‐E coefficients vary from 0.0001 to 0.1. Figure
7. Root locus when both P-ω and Q-E coefficients vary from 0.0001 to 0.1.
3.2. Multi‐Loop Voltage Control 3.2. Multi‐Loop Voltage Control 3.2.
Multi-Loop Voltage Control
Figure 8 shows the model of the multi‐loop voltage control, including computational and PWM Figure 8 shows the model of the multi‐loop voltage control, including computational and PWM Figure
8 shows the model of the multi-loop voltage control, including computational and PWM
*(s) to E(s) delays. The transfer function from V’(s) to E(s) and the open‐loop transfer function from E
delays. The transfer function from V’(s) to E(s) and the open‐loop transfer function from E
delays. The transfer function from V’(s) to E(s) and the open-loop transfer function from E**(s) to E(s) (s) to E(s)
are given by (14) and (15), respectively: are given by (14) and (15), respectively: are
given by (14) and (15), respectively:
11
∙∙
− 32 ·sT ·∙∙ 1
e
L
C
E (S)
f f
=
0
V (S)
L f +k d R
√
s2 +
·∙∙s +
R
Lf Cf
3 ∙∙
0
= e− 2 ·sT ·∙∙GLC
(s) = G (s ) 1
1
1
(14) (14)
(14) Lf Cf
E (∗ S)
1
(15) (15) ∗
= 11 + k p G (s) (15)
E∗ (S)
We can design the derivative gain kd according to the quality factor with the critically damping We can design the derivative gain k
We can design the derivative gain kdd according to the quality factor with the critically damping according to the quality factor with the critically damping
condition of (16). As can be seen from Figure 9, the high frequency resonance may cause instability condition of (16). As can be seen from Figure 9, the high frequency resonance may cause instability condition of (16). As can be seen from Figure 9, the high frequency resonance may cause instability
when kd = 0. In the case of kdd = 0.00535 (system critically damped), the resonance is clearly suppressed = 0.00535 (system critically damped), the resonance is clearly suppressed when k
when kdd = 0. In the case of k
= 0. In the case of kd = 0.00535 (system critically damped), the resonance is clearly
and the phase lagging is improved. In case of over‐damping condition (kdd = 0.001064), the stability is = 0.001064), the stability is and the phase lagging is improved. In case of over‐damping condition (k
suppressed and the phase lagging is improved. In case of over-damping
condition (kd = 0.001064),
also guaranteed, guaranteed, but but its its time time response response is is slower slower than than that that of of the the critically critically damping damping case. case. After After also the stability is also guaranteed, but its time response is slower than that of the critically damping
case.
determining k
d
, the proportional gain k
p
can be designed according to the frequency response of the determining k
d, the proportional gain kp can be designed according to the frequency response of the After determining kd , the proportional gain kp can be designed according to the frequency response of
open‐loop transfer function of (15). As shown in Figure 10, the crossover frequency is 790 Hz and open‐loop transfer function of (15). As shown in Figure 10, the crossover frequency is 790 Hz and the open-loop transfer function of (15). As shown in Figure 10, the crossover frequency is 790 Hz and
phase margin is 59.1° for k
p = 3: phase margin is 59.1° for k
phase margin is 59.1◦ for kpp = 3: = 3:
Energies 2016, 9, 732
8 of 15
Energies 2016, 9, 732 Energies 2016, 9, 732 Energies 2016, 9, 732 8 of 15 
 > 0.5, (under damping)
L f + kd R 
1
= q
Q=
:
= 0.5,
0.5, (critical damping)
 0.5,
2ξ 1 R L C 
0.5,0.5, (over damping) :
f
f
<
21
0.5,
0.5,
:
0.5,
1
2
2
:
0.5,
0.5,
0.5,
8 of 15 8 of 15 (16)
(16) (16) (16) Figure
8. Model of the multi-loop voltage control.
Figure 8. Model of the multi‐loop voltage control. Figure 8. Model of the multi‐loop voltage control. Figure 8. Model of the multi‐loop voltage control. Figure 9. Frequency responses for three different kd. Figure
9. Frequency responses for three differentd. kd .
Figure 9. Frequency responses for three different k
Figure 9. Frequency responses for three different kd. Figure 10. Bode plot of the open loop for kp = 3. (Crossover frequency = 790 Hz, Phase margin = 59.1°). Figure 10. Bode plot of the open loop for k
= 3. (Crossover frequency = 790 Hz, Phase margin = 59.1°). 3.3. Virtual Inductance Loop Figure
10. Bode plot of the open loop for kp p=
3. (Crossover frequency = 790 Hz, Phase margin = 59.1◦ ).
In this subsection, we will discuss the parameters design of the virtual inductance loop, 3.3. Virtual Inductance Loop including L
vf, Lvi, and τ. Figure 11 shows the equivalent circuit considering the virtual inductance loop. 3.3. Virtual
Inductance
Loop
In this subsection, we will discuss the parameters design of the virtual inductance loop, Similarly, the dynamic equation and the root locus are used for stability analysis purposes. Figure 12 Figure 10. Bode plot of the open loop for k
p = 3. (Crossover frequency = 790 Hz, Phase margin = 59.1°). In
this
subsection,
we will discuss the parameters
design of the virtual inductance loop, including
including L
vf, Lvi, and τ. Figure 11 shows the equivalent circuit considering the virtual inductance loop. shows the root locus when the virtual inductance L
v decreases from 5 H to 80 μH. As demonstrated, Lvf , Lvi
,
and
τ.
Figure
11
shows
the
equivalent
circuit
considering
the virtual inductance loop. Similarly,
roots will be close to the real‐axis as Lv increases. That means the stability of the system is improved Similarly, the dynamic equation and the root locus are used for stability analysis purposes. Figure 12 3.3. Virtual Inductance Loop shows the root locus when the virtual inductance L
v decreases from 5 H to 80 μH. As demonstrated, the dynamic
equation and the root locus are used for
stability analysis purposes. Figure 12 shows the
roots will be close to the real‐axis as L
root locus
when
the virtualwe inductance
Lvv increases. That means the stability of the system is improved decreases
from 5 H design to 80 µH.
demonstrated,
roots will
be
In this subsection, will discuss the parameters of As
the virtual inductance loop, close
to the vfreal-axis
as Lv increases. That means the stability of the system is improved with larger
including L
, Lvi, and τ. Figure 11 shows the equivalent circuit considering the virtual inductance loop. Similarly, the dynamic equation and the root locus are used for stability analysis purposes. Figure 12 shows the root locus when the virtual inductance Lv decreases from 5 H to 80 μH. As demonstrated, roots will be close to the real‐axis as Lv increases. That means the stability of the system is improved Energies 2016, 9, 732
Energies 2016, 9, 732 9 of 15
9 of 15 Energies 2016, 9, 732 9 of 15 with larger virtual inductance. However, induced voltage drop on the virtual inductance will limit virtual
inductance. However, induced voltage drop on the virtual inductance will limit the output
the output current of the inverter, which is a compromise in determining L
vf. current
of the inverter, which is a compromise in determining Lvf .
with larger virtual inductance. However, induced voltage drop on the virtual inductance will limit the output current of the inverter, which is a compromise in determining Lvf. Figure 11. Simplified circuit considering the virtual inductance loop. Figure
11. Simplified circuit considering the virtual inductance loop.
Figure 11. Simplified circuit considering the virtual inductance loop. Lv=80μH
Lv=80μH
λ5 λ5
λ6
λ6
λ2 λ2
λ4
v=80μH
LLv=80μH
λ4
LL
v=80μH
=80μH
v
λ1 λ
1Lv=5H
λ3
Lv=5H
λ3
Lv=80μH
Lv=80μH
Figure 12. Root locus for varying virtual inductance. Figure
12. Root locus for varying virtual inductance.
Figure 12. Root locus for varying virtual inductance. When the operation of the inverter transfers back to droop‐controlled mode, we assume that the When
the operation of the inverter
transfers back to droop-controlled mode, we assume that the
same voltage amplitude exists on L
v, but with a small phase difference δ. By taking account of the When the operation of the inverter transfers back to droop‐controlled mode, we assume that the samephasor analysis, the voltage drop on L
voltage amplitude exists on Lv , but
with
a small phase difference
δ. By taking account of the
v is 2V
psin(δ/2) in Figure 11, where V
p means peak voltage value same voltage amplitude exists on L
v, but with a small phase difference δ. By taking account of the on E. Because of the assumption of a small phase difference δ, the voltage drop can be approximated phasor analysis, the voltage drop on Lv is 2Vp sin(δ/2) in Figure 11, where Vp means peak voltage value
phasor analysis, the voltage drop on L
v is 2Vppsin(δ/2) in Figure 11, where V
means peak voltage value pδ. Thus, the maximum inrush current I
of the inverter can be expressed as follows: on
E.as V
Because
of the assumption of a small
phase
difference δ, the voltage pdrop
can be approximated
on E. Because of the assumption of a small phase difference δ, the voltage drop can be approximated as
Vp δ. Thus, the maximum inrush current1Ip of the inverter can be expressed as follows:
∙ 2 sin
(17) as Vpδ. Thus, the maximum inrush current Ip of the inverter can be expressed as follows: 2
Vp
1
δ
vi value (17)
that can be used to determine Lvi based on the accepted current limitation. Note that a small L
IP = 1 Vp∙·2sin
≈
δ
2
sin
(17) ωLv
22
ωLv may trigger inverter protection or cause the inverter transfer to riding‐through mode more than one time. On the other hand, the time constant τ determines the decay speed of the virtual inductance, vi value that can be used to determine L
that
can be used to determine viL based on the accepted current limitation. Note that a small L
Lvi
vi based on the accepted current limitation. Note that a small
which affects the dynamic behavior of the droop control and oscillating current between the inverter may trigger inverter protection or cause the inverter transfer to riding‐through mode more than one value
may trigger inverter protection or cause the inverter transfer to riding-through mode more than
and the grid. We can tune the value according to the droop coefficient as well as the line impedance. time. On the other hand, the time constant τ determines the decay speed of the virtual inductance, one
time. On the other hand, the time constant τ determines the decay speed of the virtual inductance,
which affects the dynamic behavior of the droop control and oscillating current between the inverter which
affects the dynamic behavior of the droop control and oscillating current between the inverter
3.4. Impact on an Inverter‐Dominated System and the grid. We can tune the value according to the droop coefficient as well as the line impedance. and
the grid. We can tune the value according to the droop coefficient as well as the line impedance.
As shown in Figure 1, except for the proposed inverter, the other inverters are controlled as current sources. In this case, the mode switching of the proposed inverter does not result in stability 3.4.
Impact on an Inverter-Dominated System
3.4. Impact on an Inverter‐Dominated System issues due to voltage‐follow characteristic of the current‐controlled inverters. In an inverter‐
dominated power system, droop control is normally used accomplish power sharing among As
Figure
1, except
for for the
proposed
inverter,
theto other
are controlled
as current
As shown
shown in
in Figure 1, except the proposed inverter, the inverters
other inverters are controlled as multiple voltage‐controlled inverters. Traditional voltages‐controlled inverters may temporarily sources.
In this case, the mode switching of the proposed inverter does not result in stability issues
current sources. In this case, the mode switching of the proposed inverter does not result in stability supply large currents beyond their ofrating due to the power mismatch. situation probably due
to
voltage-follow
characteristic
the current-controlled
inverters.This In an
inverter-dominated
issues due to voltage‐follow characteristic of the current‐controlled inverters. In an inverter‐
triggers circuit protection and results in unintentional shutdowns of the inverters. However, the power
system,
droop
control
is normally
to accomplish
power sharing
among
multiple
dominated power system, droop control is used
normally used to accomplish power sharing among proposed inverter is able to switch to ride‐through mode to reduce any inrush current due to system voltage-controlled
inverters. Traditional
voltages-controlled
inverters may
temporarily
supply
large
multiple voltage‐controlled inverters. Traditional voltages‐controlled inverters may temporarily disturbances. This can improve the system stability, especially in low‐voltage high impedance networks. currents
beyond
their
rating
due
to
the
power
mismatch.
This
situation
probably
triggers
circuit
supply large currents beyond their rating due to the power mismatch. This situation probably protection
and results
in unintentional
of the inverters.
However,
the proposed
inverterthe is
triggers circuit protection and results shutdowns
in unintentional shutdowns of the inverters. However, able
to switch to ride-through mode to reduce any inrush current due to system disturbances. This can
proposed inverter is able to switch to ride‐through mode to reduce any inrush current due to system improve
the system stability, especially in low-voltage high impedance networks.
disturbances. This can improve the system stability, especially in low‐voltage high impedance networks. Energies 2016, 9, 732
10 of 15
Energies 2016, 9, 732 10 of 15 4. Experimental Results 4. Experimental
Results
Energies 2016, 9, 732 10 of 15 A laboratory‐scale prototype was
was built
built and
and tested the the
proposed seamless A laboratory-scale
prototype
testedin inorder orderto toverify verify
proposed
seamless
4. Experimental Results transition method. The experimental setup is shown in Figure 13 and the parameters are given in transition method. The experimental setup is shown in Figure 13 and the parameters are given in
Table 2. When the STS is OFF, the inverter is operated in islanded mode. The setup of the current A laboratory‐scale prototype was built and tested order to mode.
verify the Table 2. When
the STS is OFF,
the inverter
is operated
inin islanded
Theproposed setup ofseamless the current
threshold is determined based on the inverter rating. In this experiment, the current threshold is set transition method. The experimental setup is shown in Figure 13 and the parameters are given in threshold is determined based on the inverter rating. In this experiment, the current threshold is set
as two times the inverter rating. Figure 14 shows steady‐state voltage and current waveforms of the Table 2. When the STS is OFF, the inverter is operated in islanded mode. The setup of the current as two
times in theislanded invertermode. rating.
Figure
14 shows
steady-state
voltage
andinverter currentoutput waveforms
of the
inverter Figure 15 shows the transient response of the voltage, threshold is determined based on the inverter rating. In this experiment, the current threshold is set inverter
in islanded
15 shows
responseObviously, of the inverter
output voltage,
calculated active mode.
power, Figure
and currents when the
the transient
load is increased. the amplitude of as two times the inverter rating. Figure 14 shows steady‐state voltage and current waveforms of the calculated
active
power,
andis currents
when
the nominal load is increased.
Obviously,
the amplitude
of inverter
inverter output voltage maintained at the value and the output power of the inverter inverter in islanded mode. Figure 15 shows the transient response of the inverter output voltage, output
voltage isactive maintained
thecurrents nominalwhen valuethe and
the is output
power
of the inverter
increasesof from
increases from 1 kW to 2 kW. Notice that the calculated active power shown in Figure 15a is processed calculated power, at
and load increased. Obviously, the amplitude 1 kWby a LPF. to
2 kW. output Notice
that theis calculated
shown
Figure
15a is power processed
byinverter a LPF.
inverter voltage maintained active
at the power
nominal value in
and the output of the increases from 1 kW to 2 kW. Notice that the calculated active power shown in Figure 15a is processed by a LPF. ＋
－
＋
－
Figure 13. Experimental setup. Figure 13. Experimental setup.
Table 2. Experimental Parameters. Figure 13. Experimental setup. Table
2. Experimental Parameters.
Description Symbol
Value
Table 2. Experimental Parameters. Grid voltage (line‐line) Vg 220 Description
Symbol
Value
Grid frequency fg 60 Description Value
Grid voltage
(line-line)
Vg Symbol
220
Nominal voltage E0 174.7 Grid voltage (line‐line) Vg 220 GridInverter output power frequency
fg
601000 Po Grid frequency fg 60 Nominal
voltage
E0
174.7
Nominal Frequency ω0 377 Nominal voltage E0 174.7 Inverter output
power
Po
1000
P‐ω droop m −0.0005 Po NominalInverter output power Frequency
ω0
3771000 Q‐V droop n 0 Nominal Frequency ω0 377 P-ω
droop
m
−0.0005
Filter cut‐off frequency ωc 62.8 P‐ω droop m −0.0005 Q-V
droop
n
0 80 Nominal virtual inductor Lvf Q‐V droop n Filter cut-off
frequency
ωc
62.8 3 0 Lvi Initial virtual inductor Filter cut‐off frequency L
ωc 62.8 Nominal virtual
inductor
80 0.3 Time constant τ vf
Nominal virtual inductor Lvf Proportional gain kp Initial virtual
inductor
Lvi
3 3 80 Lvi 3 Initial virtual inductor 0.000532 kd TimeDifferential coefficient constant
τ
0.3
Time constant τ 0.3 Riding‐through period TRD Proportional
gain
kp
3 10 3 Proportional gain kp 10 Current threshold ITH Differential
coefficient
kd
0.000532
0.000532 Differential coefficient kd Riding-through period
TRD
10
Riding‐through period TRD 10 Current threshold
ITH
10
10 Current threshold ITH (a)
(a)
Figure 14. Cont.
Unit V Unit
Hz Unit V V
V W Hz
Hz V
rad/s V W
rad/W W rad/s
V/Var rad/s rad/W
rad/s rad/W V/Var
μH V/Var rad/s
H rad/s s µH
μH ‐‐‐ H
H ‐‐‐ s
s ms —
‐‐‐ A —
‐‐‐ ms
ms A
A Energies 2016, 9, 732
11 of 15
Energies 2016, 9, 732 Energies 2016, 9, 732 11 of 15 11 of 15 (b)
(b)
14. Inverter voltage and current in islanded mode. (a) Inverter output voltage (200 V/div); FigureFigure 14. Inverter
voltage and current in islanded mode. (a) Inverter output voltage (200 V/div);
Figure 14. Inverter voltage and current in islanded mode. (a) Inverter output voltage (200 V/div); (b) Inverter output current (2.5 A/div). (b) Inverter output current (2.5 A/div).
(b) Inverter output current (2.5 A/div). (a)
(a)
(b)
(b)
Figure 15. Inverter voltage, measure power and current in islanded mode when load increases. Figure 15. Inverter voltage, measure power and current in islanded mode when load increases. ab, ebc, eca) (200 V/div); output real power (500 W/div); (b) Inverter output Figure(a) Inverter output voltage (e
15. Inverter voltage, measure
power and current in islanded mode when load increases.
(a) Inverter output voltage (e
currents (ia, ib, ic) (5 A/div). ab, ebc, eca) (200 V/div); output real power (500 W/div); (b) Inverter output (a) Inverter output voltage (eab , ebc , eca ) (200 V/div); output real power (500 W/div); (b) Inverter output
currents (ia, ib, ic) (5 A/div). currents (ia , ib , ic ) (5 A/div).
This experiment can verify effectiveness of the multi‐loop voltage control. It needs to be This experiment can verify effectiveness of the multi‐loop voltage control. It needs to be mentioned that the root mean square (rms) values shown in Figure 15b are not the same. It is the mentioned that the root mean square (rms) values shown in Figure 15b are not the same. It is the This
experiment can verify effectiveness of the multi-loop voltage control. Figure 16 shows that
inverter voltage and grid voltage when the STS is closed at T1 . At this moment, the phase difference
between Eabc and vg,abc is equal to 169.9◦ .
Energies 2016, 9, 732 12 of 15 Energies 2016, 9, 732 12 of 15 oscilloscope root‐mean‐square value calculated by taking into account the whole waveform, which is shown on the monitor. Due to the transient behavior of the current, the calculation results include oscilloscope root‐mean‐square value calculated by taking into account the whole waveform, which unbalance and thus it are pointless. Figure 16 shows that inverter voltage and grid voltage when the is shown on the monitor. Due to the transient behavior of the current, the calculation results include Energies
2016, 9, 732
12 of 15
STS is closed at T
1. At this moment, the phase difference between Eabc and vg,abc is equal to 169.9°. unbalance and thus it are pointless. Figure 16 shows that inverter voltage and grid voltage when the STS is closed at T1. At this moment, the phase difference between Eabc and vg,abc is equal to 169.9°. Figure 16. Inverter output voltage and grid voltage (transient of inverter switching to grid‐connected Figure 16. Inverter output voltage and grid voltage (transient of inverter switching to grid-connected
operation) (100 V/div). Figure 16. Inverter output voltage and grid voltage (transient of inverter switching to grid‐connected operation)
(100 V/div).
operation) (100 V/div). As can be seen from Figure 17, the inverter current exceeds the threshold limitation at T1. Thus, As can be seen from Figure 17, the inverter current exceeds the threshold limitation at T1 . Thus,
subsequently the inverter controller automatically switches to the riding‐through mode. The current As can be seen from Figure 17, the inverter current exceeds the threshold limitation at T1. Thus, subsequently the inverter controller automatically switches to the riding-through mode. The current
controller of the riding through mode fixes the inverter output current to almost zero and the local subsequently the inverter controller automatically switches to the riding‐through mode. The current controller of the riding through mode fixes the inverter output current to almost zero and the local
PLL aligns the phase angle of the voltage command with respect to the grid at the same time. Since controller of the riding through mode fixes the inverter output current to almost zero and the local PLL aligns the phase angle of the voltage command with respect to the grid at the same time. Since the
the proposed strategy does not use any phase synchronization, a voltage dip appears in the inverter PLL aligns the phase angle of the voltage command with respect to the grid at the same time. Since proposed strategy does not use any phase synchronization, a voltage dip appears in the inverter output
output as shown in Figure 16 when the STS is closed. The duration of the voltage dip is less than the the proposed strategy does not use any phase synchronization, a voltage dip appears in the inverter as shown in Figure 16 when the STS is closed. The duration of the voltage dip is less than the clear time
the clear time (160 ms) in case of abnormal voltage according to IEEE 1547.2‐2008 [3].
After a riding‐
output as shown in Figure 16 when the STS is closed. The duration of the voltage dip is less than the (160 ms) in case of abnormal voltage according to IEEE 1547.2-2008 [3]. After a riding-through interval
through interval T
RD, the inverter switches back to droop‐controlled mode at T2, but still works in grid‐connected the clear time (160 ms) in case of abnormal voltage according to IEEE 1547.2‐2008 [3].
After a riding‐
TRD , the inverter switches back to droop-controlled mode at T2 , but still works in grid-connected mode.
2
, the virtual inductance loop is initiated. Figure 18 shows exponentially decreasing mode. At the same time T
through interval TRD, the inverter switches back to droop‐controlled mode at T2, but still works in grid‐connected At the same time T2 , the virtual inductance loop
is initiated. Figure 18 shows exponentially decreasing
feature of the designed virtual inductance with L
vi = 3 H, Lvf = 80 μH and τ = 0.3 s (see (5)). mode. At the same time T2, the virtual inductance loop is initiated. Figure 18 shows exponentially decreasing feature of the designed virtual inductance with Lvi = 3 H, Lvf = 80 µH and τ = 0.3 s (see (5)).
feature of the designed virtual inductance with Lvi = 3 H, Lvf = 80 μH and τ = 0.3 s (see (5)). Figure 17. Inverter output current with virtual inductance loop (5 A/div). Figure 17. Inverter output current with virtual inductance loop (5 A/div).
Figure 17. Inverter output current with virtual inductance loop (5 A/div). Energies 2016, 9, 732
Energies 2016, 9, 732 Energies 2016, 9, 732 13 of 15
13 of 15 13 of 15 Figure 18. The exponential virtual inductance value (1 H/div). Figure 18. The exponential virtual inductance value (1 H/div).
Figure 18. The exponential virtual inductance value (1 H/div). Figure 17 after T2 shows that the virtual inductance can help reduce the circulating current Figure
Figure 17
17 after
after TT22 shows
shows that
that the
the virtual
virtual inductance
inductance can
can help
help reduce
reduce the
the circulating
circulating current
current resulting from both droop operation and phase error. It is worth mentioning that the inverter output resulting
from
both
droop
operation
and
phase
error.
It
is
worth
mentioning
that
the
inverter
output
resulting from both droop operation and phase error. It is worth mentioning that the inverter output current shows oscillation after T
2 because the droop controller is trying to accomplish power sharing, current
shows
oscillation
after
T
because the droop controller is trying to accomplish power sharing,
22 because the droop controller is trying to accomplish power sharing, current shows oscillation after T
and it will reach a steady‐state after a few cycles. For comparison purposes, Figure 19 shows the same and
it will reach a steady-state after a few cycles. For comparison purposes, Figure 19 shows the same
and it will reach a steady‐state after a few cycles. For comparison purposes, Figure 19 shows the same test result as Figure 16 without the virtual inductance loop applied. Obviously, the inverter current test
result
without the virtual inductance loop applied. Obviously, the inverter current of
test result as Figure 16 without the virtual inductance loop applied. Obviously, the inverter current of Figure as
19 Figure
after T16
2 is higher than that of Figure 17. At the steady‐state of the grid‐connected Figure
19 after
T2 is higher
than that
of that Figure
At the
steady-state
of the grid-connected
operation,
of Figure 19 after T2 is higher than of 17.
Figure 17. At the steady‐state of the grid‐connected operation, the output power of the inverter is 1 kW as shown in Figure 20. Note that the current spikes the
output
power
of
the
inverter
is
1
kW
as
shown
in
Figure
20.
Note
that
the
current
spikes
are
operation, the output power of the inverter is 1 kW as shown in Figure 20. Note that the current spikes are different at the instant T1 because Figures 17 and 19 are tested in different instants. different
at
the
instant
T
because
Figures
17
and
19
are
tested
in
different
instants.
are different at the instant T
1 because Figures 17 and 19 are tested in different instants. 1 show Experimental results that how the inrush current can be limited to an acceptable level Experimental
results
show
that
Experimental results show that how
how the
the inrush
inrush current
current can
can be
be limited
limited to
to an
an acceptable
acceptable level
level when starting grid‐connected operation. When the inverter current is larger than the threshold value, when
starting
grid-connected
operation.
When
the
inverter
current
is
larger
than
the
threshold
value,
when starting grid‐connected operation. When the inverter current is larger than the threshold value, the inverter is switched to ride‐through mode and temporarily operated as current mode control with the
inverter is switched to ride-through mode and temporarily operated as current mode control with
the inverter is switched to ride‐through mode and temporarily operated as current mode control with zero current command to reduce the inverter current. When back to droop control mode, the inrush zero
current command to reduce the inverter current. When back to droop control mode, the inrush
zero current command to reduce the inverter current. When back to droop control mode, the inrush current no longer occurs since the angle of voltage command is updated by PLL to synchronize with current
no longer occurs since the angle of voltage command is updated by PLL to synchronize with
current no longer occurs since the angle of voltage command is updated by PLL to synchronize with the utility and virtual inductance is engaged at the same time. the
utility and virtual inductance is engaged at the same time.
the utility and virtual inductance is engaged at the same time. Figure 19. Inverter output current without virtual inductance loop (5 A/div). Figure
19. Inverter output current without virtual inductance loop (5 A/div).
Figure 19. Inverter output current without virtual inductance loop (5 A/div). Energies 2016, 9, 732
Energies 2016, 9, 732 14 of 15
14 of 15 Figure 20. Transient response of invert output power (500 W/div). Figure 20. Transient response of invert output power (500 W/div).
5. Conclusions 5. Conclusions
This paper presents a seamless transition method for droop‐controlled inverters between This
paper
a seamless
transition
for droop-controlled
inverters
between
islanded
islanded and presents
grid‐connected modes. Thus, method
the inverter is able to transfer between both modes and
grid-connected
modes.
Thus,
the
inverter
is
able
to
transfer
between
both
modes
without
using
any
without using any grid‐side information. Consequently, the approach is suitable for an IEEE 1547.4 grid-side
information.
Consequently,
the
approach
is
suitable
for
an
IEEE
1547.4
compliant
microgrid,
compliant microgrid, in which the voltage source inverter responsible for both frequency and voltage in regulation which the voltage
source
inverter
responsible
both frequency
and
voltage
is located
is located far away from the static for
transfer switch. For this case, regulation
an algorithm that farcoordinates away froma the
static
transfer
switch.inductance For this case,
anis algorithm
coordinates
a localwill PLL
and
local PLL and a virtual loop proposed. that
Thus, the ver‐current not a virtual
inductance
loop
is
proposed.
Thus,
the
over-current
will
not
occur.
A
control
parameter
occur. A control parameter design example and stability analysis are presented as well. The experimental results show that the inverter can transfer from islanded to grid‐connected modes even design
example and stability analysis are presented as well. The experimental results show that the
when the inverter voltage is totally out of phase from the grid voltage. inverter
can transfer from islanded to grid-connected modes even when the inverter voltage is totally
outAcknowledgments: This work was supported by Ministry of Science and Technology, TAIWAN under grant of phase from the grid voltage.
104‐2221‐E‐110‐037. Acknowledgments: This work was supported by Ministry of Science and Technology, TAIWAN under
Author Contributions: Tzung‐Lin Lee, Josep M. Guerrero, Shang‐Hung Hu and Chun‐Yi Kuo conceived and grant
104-2221-E-110-037.
designed the experiments; Shang‐Hung Hu and Chun‐Yi Kuo performed the experiments and analyzed the data; Author Contributions: Tzung-Lin Lee, Josep M. Guerrero, Shang-Hung Hu and Chun-Yi Kuo conceived and
Shang‐Hung Hu wrote the paper. designed
the experiments; Shang-Hung Hu and Chun-Yi Kuo performed the experiments and analyzed the data;
Shang-Hung
Hu wrote the paper.
Conflicts of Interest: The authors declare no conflict of interest. Conflicts of Interest: The authors declare no conflict of interest.
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