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Development status of
SOI ASIC / FPGA
Oct. 30th 2007
Electronic, Mechanical Components and
Materials Engineering Group, JAXA
H.Shindou
Background
In 2003, critical EEE parts for space use were
selected at the Japan space EEE parts committee
in order to develop advanced space systems.
Programmable device (FPGA) was selected as
one of the first phase items of critical components.
We started the feasibility study about FPGA
based on 0.15m FD-SOI technology.
We also started the development of SEU / SET
hardened cell library for SOI ASIC.
SEU: Single Event Upset
SET: Single Event Transient
FD-DOI: Fully depleted Silicon on Insulator FPGA: Field Programmable Gate Array
ASIC: Application Specific Integrated Circuit
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Why we choose FD-SOI
For <0.18m technology,
SEEs are main concern for
LSIs for space applications.
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Design Rule (1/2pitch) [m]
JAXA has developed LSIs
with the latest technology for
commercial market.
0.35m, 33MHz 64bitMPU(3.3V)
0.18m, 200MHz 64bitMPU(1.8V)
0.1
0.15m, FDSOI(1.5V)
FD-SOI is attractive for
space because of its SEE
0.01
1990 1995 2000 2005 2010 2015 2020
hardness as compared with
Year
bulk technology.
Design rule trend and JAXA’s
(also suitable for Low power
LSI roadmap
application.)
Now we plan to utilize the FD-SOI as a mainstream technology.
SEE: Single Event Effect
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PD-SOI vs FD-SOI
(Courtesy of OKI, quoted from 19MEWS material)
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Oki FD-SOI Device Structure & Process
- 0.15um SOI (Production line)
LOCOS ⇒ STI
Metal 0.52 ⇒ 0.39(1M)/0.48(<2M)
BOX 200nm ⇒ 145nm
Low Leakage (LL) Ioff<2E-12A/um
(Courtesy of OKI, quoted from 19MEWS material)
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Development schedule (SOI process)
2007
Apr May Jun
Basic Process Development
(3 Metal Layers)
Finalizing
Jul Aug Sep
2008
Oct Nov Dec
Jan Feb Mar
WLR
Process Module Development
for 6 Metal Layers
WLR: Wafer Level
Reliability Evaluation
Process Development for 6
Metal Layers
Test Element Group Chips #1
(3 Metal Layers)
Apr May Jun
WLR
WP: Wafer Processing
WP
Test Element Group Chips #2
(3 & 6 Metal Layers)
Final SPICE
/PDK
Evaluation
WP
Design & Chip production/
Qualification Test
ASIC Cell library / Memory
generator
Design Cell library & evaluation chip
Design Memory generator
WP
- Process development with 6 metal layers is in progress.
- Final SPICE/PDK is scheduled to be released at the end of
fiscal year.
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Target Specification for ASIC / FPGA
0.15μm commercial FD-SOI foundry with
patented SEU/SET free primitive circuits.
(RHBD techniques used)
1.5V for core and 3.3V for I/Os.
SEU/SET free up to LET of 64MeV/(mg/cm2)
TID: 1kGy(Si) (100krad(Si))
ASIC & FPGA
Joint development with CNES / ATMEL
SRAM based re-configurable FPGA.
(Based on ATMEL architecture)
700k ASIC gates
FPGA
RHBD: Radiation Hardened By Design
TID: Total Ionizing Dose LET: Liner Energy Transfer
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Single Event Transient signal generation
CMOS/Bulk Inverter
Input
output
p+
GND
n-Well
p-Substrate
VDD
Input
“0”
VDD
- e-h pair generation by an Ion
strike to the OFF-state transistor
“1”
Output
SET Signal
GND
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- Reversed biased junctions
collect charge
- Voltage transients propagate
appreciable distances
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Advantage of SOI structure
CMOS/SOI Inverter
GND
Input
n+
BOX(SiO2)
output
VDD
p+
p-Substrate
VDD
Input
- Sensitive volume for charge collection
CMOS/Bulk > CMOS/SOI
Output
- All the transistors are electrically
isolated by dielectric material
GND
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It is possible to eliminate the SET
signal generation by implementing
RHBD !
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Basic concept of RHBD
A
Y
Redundant
Tr Pairs
RHBD Inverter
(SET free)
Error X-Section [m2/bit]
1.0
対策なし(リファレンス)
0.1
Conventional
RHBD
Inverter
対策あり
10-2
Ar
Xe
(エラーなし、上限値)
Kr
10-3
0
20
40
60
2
LET [MeV/(mg/cm )]
80
The redundant transistor pairs completely prevent the
SET pulse generations on the output terminal.This
concept can be easily extended for any logic gates and
the logic circuits. However the optimization of area, power,
speed penalties is an important issue.
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TEG evaluation
The design and evaluation (Irradiation test) of the Test
Element Group are in progress.Test results will be applied to
the design of FPGA and Cell library.
Irradiation test system (Heavy-ion accelerator at Japan Atomic Energy Agency)
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Development schedule (ASIC & FPGA)
2007
Apr May Jun
Basic Process Development
(3 Metal Layers)
Finalizing
Jul Aug Sep
2008
Oct Nov Dec
Jan Feb Mar
WLR
Process Module Development
for 6 Metal Layers
WLR: Wafer Level
Reliability Evaluation
Process Development for 6
Metal Layers
Test Element Group Chips #1
(3 Metal Layers)
Apr May Jun
WLR
WP: Wafer Processing
WP
Test Element Group Chips #2
(3 & 6 Metal Layers)
Final SPICE
/PDK
Evaluation
WP
Design & Chip production/
Qualification Test
ASIC Cell library / Memory
generator
Design Cell library & evaluation chip
Design Memory generator
Test Element Group Chips #1
Configuration bits / Free RAMs for FPGA
RAM cells, Shift registers for SET testing
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WP
Test Element Group Chips #2
Core cells for FPGA
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