THE DJOSER THERMAL SIMULATOR FOR ELECTRONIC DEVICES
AND SYSTEMS: DIDACTIC FEATURES FOR IMPROVING
RELIABILITY CULTURE IN ACADEMIC AND INDUSTRIAL
ENVIRONMENTS.
Paolo Emilio BAGNOLI (1), Fabio STEFANI (1), Maurizio BECCAI (2)
(1) Dpt. of Information Engineering. University of Pisa, 56122 Pisa, Italy ,
p.bagnoli@iet.unipi.it, fabio.stefani@iet.unipi.it
(2) EFFEI srl, Via Aldo Moro 11,13, 50019-Sesto Fiorentino, Firenze, Italy, info@effei.it
Abstract
The structure and the technical and didactic characteristics of a novel thermal simulation system
(DJOSER) for electronic device and system mounting structures and based on an analytical resolution
strategy, are shown and discussed by means of several applicative examples having large importance
in the optimum reliability-oriented design of electronic power handling.
Keywords
Temperature, Simulation, Electronics, Power Devices, Packaging, Thermal Analysis, Didactic.
1. INTRODUCTION
The thermal analysis of electronic devices and circuits and their packaging structures is becoming a
crucial need in electronic design and therefore a cultural luggage for the electric and electronic
engineers. This type of analysis is usually performed using the finite-element-method based (FEM)
thermal simulation, which is a general purpose, widely used and reliable tool also for complex threedimensional structures. As known, it is based on the discretization of the thermal conduction equations
within a close net of solid elements. Therefore the FEM analysis needs a 3-D meshing of the solid
system, which is in general, not uniform, so that the model preparation for optimum results may be
complex and overall requires some qualified capabilities by the operator.
Since the thermal analysis must be performed not only by the device producer but also by the system
assembler user which can belong to small or medium size industries, the current situation is that in
these last environment there are not enough financial support to acquire the knowledge and the tools
to perform it, so that the thermal problems are usually solved by adopting the strategy of over-sizing
devices and systems with consequent dimension and cost penalties. Instead the importance of these
reliability problems would require less expensive, less time consuming and more easily programmable
thermal simulation tools in order to perform fast analyses with the same accuracy of FEM programs.
Most of electronic assemblies (both devices and boards), especially for high and very high power
handling, can be described by simple structures consisting of stacks of homogeneous layers of
different materials and dimensions, connected directly or by means of thin soldering or attaching
Fig.1. (A) Assembling structure composed by a stack of homogeneous rectangular layers. (B) The
two-dimensional regular grids of cells at the interfaces of the structure.
layers. The power dissipation may be assumed as two-dimensional on one or more interfaces and with
the bottom side generally connected to a constant temperature heat sink, directly or through a
thermalconvection coefficient. These structures are quite similar to a stepped pyramid [1], eventually
with various degree of asymmetry as shown in the figure 1A.
If the above simple geometrical configuration is suitable to represent the whole assembling structure,
the steady-state thermal simulations may be performed using dedicated mathematical models with
explicit analytical relationships [2] which can be implemented in fast and easily programmable
simulation tools characterized by a shorter computing time than FEM and an almost automatic preprocessing procedure.
In this communication, an analytical thermal simulation tool for the steady-state of electronic systems
having the above cited benefits is presented. In the following it will be addressed as DJOSER model
[3,4]. It can be used for planar electronic systems and it is able to well represent a wide range of
electronic assembling configurations such as integrated circuits encapsulated in power packages, flipchip or BGA (Ball-grid-array) mounted devices, hybrid circuits, multi ‘naked’ chip assemblies, printed
electronic boards assembled in surface mounting technology or on multi-layer metal interconnecting
substrates and hybrid thick film technology. The theoretical and experimental validation activities
performed in the past [5,6] demonstrated that the accuracy of the results is within 1% with respect to
both more sophisticated FEM analyses and experimental measurements.
Just because of its advantages this simulation program is particularly suitable to perform didactic
activities within the university courses devoted to electronic system reliability and, in the industrial
environment, to help the optimized design of electronic packaging and mounting.
2. THE DJOSER SIMULATION PROGRAM
2.1 Mathematical background
Fig. 1A shows a typical assembling structure of a power electronic device which is composed by a
stack of any number of rectangular-shaped homogeneous layers of different materials with different
thermal conductivities, similar to a step pyramid, eventually also asymmetric.
The thermal problem, which is the calculation of the temperature and heat flux distributions at all the
interfaces between the layers, is based on the resolution of the single homogeneous slab. Here the
known thermal functions are the bottom temperature T(x,y,z=Lz), the thermal flux q(x,y,z=0) entering
from the top surface and the two-dimensional power sources P(x,y) and P*(x,y) located at the top and
bottom surfaces respectively, while the unknown variables are the top temperature T(x,y,z=0) and the
heat flux distribution q(x,y, z=Lz) at the bottom surface of the slab. The single slab solution can be
obtained by means of the variable separations and superposition techniques, so that the unknown
variables are expressed by the two following integral relationships:
Lx Ly
Lx Ly

T ( x, y,0) = ∫ ∫ [ P( x′, y′) + q( x′, y′,0)] ⋅ G11 ( x′, y′ | x, y)dx′dy′ + ∫ ∫ [ R * ⋅P *( x′, y′) + T ( x′, y′, Lz )] ⋅ G12 ( x′, y′ | x, y)dx′dy′

0 0
0 0

Lx Ly
Lx Ly
q( x, y, L ) =
′
′
′
′
′
′
′
′
P
(
x
,
y
)
+
q
(
x
,
y
,0)
⋅
G
(
x
,
y
|
x
,
y
)
dx
dy
+
[
]
z
21
∫0 ∫0
∫0 ∫0 [ R *⋅P *( x′, y′) + T (x′, y′, Lz)] ⋅ G22 ( x′, y′ | x, y)dx′dy′


(1)
where R* is an eventual thermal contact resistance per unit area located at the bottom surface of the
single slab. The spatial functions Gij(x’,y’|x,y) are Green functions consisting of double harmonic
cosine Fourier series. Using the coordinates system shown in the figure 1B, the Gij functions are just
cosine-like and may be defined as follows:
∞
∞
Gij ( x′, y′ | x, y ) = ∑ ∑ Cij ( n, m ) cos ( β n x′) cos( µ m y ′) cos( β n x) cos( µ m y )
n =0 m =0
(2)
where Cij(n,m) are suitable coefficients and the eigenvalues βn and µm are given by:
βn = nπ / Lx , µm = mπ / Ly
with n , m integer
(3)
in the adiabatic case, otherwise they are calculated from the zeros of a transcendent equation
containing the top and lateral heat exchange convection coefficients.
If we turn back to the case of step pyramid, it is quite evident that for a single slab of the stack the
functions q(x,y,0) and T(x,y,Lz) are not really known but they are the thermal flux coming from the
upper layer and the temperature distribution of the contact area with the lower layer respectively. The
temperature T(x,y,Lz) at the bottom of the lowest layer is known and corresponds to the heat sink
temperature. Therefore the set of relations (1) for all the layers belong to a system with 2(Ns-1)
integral equations and where the 2(Ns-1) unknown variables are the functions q and T, Ns being the
number of slabs belonging to the whole structure. This is the mathematical core of the DJOSER
model.
However the real implementation of the method and the knowledge of the q and T functions require
the use of suitable numerical calculations and approximations. Firstly, the Green functions, given by
equation (2), must be evaluated for a finite number of eigenvalues, being Nnm the maximum number
of the indices n and m used for the calculations of the Fourier series.
Secondly, the double integrals in equations (1) require the use of suitable formulas for 2-D numerical
integration and therefore the heat flux and temperature functions can be known in the form of a grid of
sample values. This implies that all the interfaces of the structure must be divided into a regular twodimensional grid of cells as shown in the figure 1B: each flux or temperature numerical value ( q(xi,yj)
and T(xi,yj) ) in each layer corresponds or is relative to the centre of a single cell on a given interface
defined by the relative coordinates (xi,yj). Therefore the system of 2(Ns-1) integral equations can be
transformed into a simple algebraic linear system.
In comparison with the FEM calculation strategy which uses irregular meshes of 3-D elements, the
accuracy depending on both the shape and density of the elements, the DJOSER program uses only
regular two-dimensional grids of rectangular cells at the interfaces, dramatically decreasing the
number of variables and therefore the calculation time and memory occupation.
Note that, beside the mathematical background of the DJOSER may be complex, the human operator
is not compelled to have knowledge of it, but its pre-processing action is only devoted to define the
geometrical characteristics of the model.
Fig.2. Details and boundary conditions of the DJOSER models: (A) reference temperatures; (B) two
types of power loads; (C) contact thermal resistances; (D) convection coefficients for each face; (E)
passivating coatings; (F) bottom convection for the external heat spreader design.
2.2 Model builder characteristics
The figure 2 schematically shows all the characteristics and boundary conditions which can be
inserted into the DJOSER model using its pre-processing unit and which make the model itself able to
realistically represent a lot of device mounting configurations.
A) Reference temperatures. There are two different reference temperatures Ta and To (figure 2A).
Ta is the temperature of the external environment surrounding the lateral faces of each layer and the
top ones not covered by an upper layer. To is the temperature of a heat sink placed in contact with the
bottom face of the lowest layer. Note that, while Ta has a unique uniform value, To can have a not
uniform distribution on the assigned plane.
B) Power loads. The assigned electrical power loads (figure 2B), i.e. the surfaces corresponding to
the resistances or the active devices acting as heat sources are supposed to be localized at the
interfaces of the structure (eventually also on the top surfaces not covered by an upper layer) and with
any two-dimensional distributions. The power distributions may be organized in separated islands
each dissipating an assigned power or power density. In each layer two different power sources can
be inserted: those on the top surface P(x,y) and those on the bottom surface P*(x,y), which, of course,
have a true meaning only if the given layer is thermally separated from the lower one by the presence
of a contact thermal resistance. This last type of power source allows to represent also particular
device mounting configurations as flip-chip and BGA, in which the silicon chip is mounted top-sidedown and whose active surface is separated from the underlying substrate by a thin polymeric
insulating layer (underfilling).
C) Thermal contact resistance. The presence of a thermal contact resistance R* (figure 2C) between
two adjacent layers or at the bottom surface may be included in the model. This parameter represent
the contribution of very thin soldering or gluing layers or the effects of an imperfect contact due to the
surface roughness of the two elements of the mounting stack. All these factors, causing a drawback
for the conduction heat flux and therefore an abrupt temperature drop within the structure, are
generally responsible for the uncertainties of the experimental values of the thermal resistance of real
assemblies.
D) Convective boundary conditions. The DJOSER model builder allows the setting of convective
boundary conditions on all the surfaces exposed to the environment (figure 2D) with the only limitation
that the heat exchange coefficient H must be uniform on the whole single surface. Different H
coefficients can be set for different layers and different surfaces (top, north, south, west and east) The
possibility to take into account also the convection heat exchange is very useful from the real
applications since it allows to verify the effectiveness of the internal or external vent in the removal of
excess heat and in the decrease of the device maximum temperature.
E) Passivating coatings. On all the surfaces exposed to the external environment the presence of an
insulating or passivating layer (figure 2E) may be inserted. From the practical point of view this
presence is directly translated into a modification (decrease) of the heat exchange coefficient of the
corresponding surface, since the insulating layer thermally acts as a thermal resistance per unit area
in series to that due to the convection mechanism.
F) Bottom convection. The possibility to set the To temperature equal to that of the environment Ta
and to place a heat convection coefficient Hb on the bottom surface of the structure allows us to verify
the effect of an external dissipater on the device maximum temperature (figure 2F) and therefore to
exactly design the proper dissipating structure needed to decrease the device temperature under the
safe area limits. The details of this procedure is reported in the application section.
3 APPLICATIONS OF THE DJOSER THERMAL SIMULATOR
The DJOSER program was implemented in the MATLAB 7.0 environment which is provided with very
useful and powerful graphic interfaces helping to make the data pre-processing and the results
visualization easy and friendly from the user point of view.
In this section a not-exhaustive set of thermal problems concerning power electronic devices and
packaging are shown and discussed. They are presented just to demonstrate the utility of this
simulation approach in solving thermal problems involving both the conduction and convection heat
exchange mechanisms. Especially thanks to the high speed of the calculation procedures with respect
to other simulation strategies this software provides the possibility of performing a large number of
thermal analyses and hence exploring a large set of mounting solutions. Furthermore, still thanks to all
its benefits, the DJOSER program may also be retained as a powerful, reliable and low-cost didactic
tool in both academic and industrial environments in which the design activities include the reliability
analysis of the electronic systems.
3.1 Power device assembling thermal characterization
The figure 3 shows the cross-section (fig. 3A) of a typical mounting structure for a power electronic
device in surface mounting technology having a bottom copper frame. The whole structure is almost
asymmetrical, as can be seen in the figure 3B depicting the corresponding DJOSER model.
Neglecting as a first approximation the thermal effects due to the presence of the device pins, the
whole assembly corresponds in practice to a stack of homogeneous layers, some conducting and
some insulating, attached each other by means of solders or gluing pastes.
FIG. 3. Cross-section (A) of the sample indicating the layers and their thicknesses, the contact
resistances and the silicon power source map. (B) View of the corresponding DJOSER model.
FIG. 4. Colour-scaled temperature maps on the top surfaces of plastic, silicon, copper and alumina.
Each map has its own color scale.
FIG. 5. (A) Temperature distributions of the five layers along the horizontal axis crossing the centre of
the silicon chip. (B) Temperature distributions of the top plastic surface under four convection
2
conditions ( H = 8, 50, 200,800 W/m °C).
The thicknesses of all the layers, the localization and values of the contact thermal resistances at the
interfaces, the two reference temperatures and the power load map on the top of the silicon layer are
directly reported in the same figure. All the surfaces of all the layers, except those of the silicon chip
and the top surface of the copper frame, are supposed to exchange heat with the environment with a
2
coefficient H = 8 W/m °C.
The temperature maps are shown in the figure 4, while the figure 5A shows the temperature
distributions along the horizontal axis crossing the silicon centre. These types of figures are some of
those available in the DJOSER post-processor for the visualization of the results. The first step of the
calculation procedure, devoted to the algebraic matrix construction and solution, required 158
seconds, while that for obtaining the five more resolved temperature maps required 518 seconds on a
lap-top computer having a clock frequency of 2.1 GHz.
The effects of the different convection coefficients (some of which are unrealistic) were found to be
almost week on the silicon top temperature distribution but more evident on those of the top plastic.
Instead these effects can be clearly seen in the 2-D temperature distribution plots calculated along the
main vertical axis of the plastic layer. The convective heat exchange coefficients were 8, 50, 200 and
2
800 W/m °C.
3.2 Characterization of the insulator thermal conductivity in IMS substrates
The use of metal substrates (IMS) [7] for circuit mountings is becoming irreplaceable for all the
FIG. 6. (A) Cross-section of the sample used for the IMS insulator layer characterization. (B) Top view
of the sample. (C) Results of DJOSER simulations: total thermal resistance vs insulator layer thermal
resistivity. The labels indicate the corresponding thermal conductivity values.
electronic systems handling high and medium powers or which are located in thermally unfavourable
positions such as for automotive electronics [8]. This type of substrate with high heat dissipating
capabilities is composed by a thick aluminium slab covered by a thin insulating layer whose thickness
and composition are crucial for its thermal, thermo-mechanical and dielectric properties. Several
methods are currently used for a reliable deposition of the insulating layer and for keeping its thermal
conductivities as high as possible. These techniques include the use of thin silica tissues in a
polymeric matrix or the use of fine alumina powder mixed to the polymer material. However the
accurate experimental knowledge of the insulating layer specific thermal conductivity is very important
not only for the customer, in order to choose the most suitable substrate for his application, but also for
the producer which must provide these data and must take the deposition technological process under
control.
The joined use of an experimental thermal resistance measurement method and of the DJOSER
thermal simulations provides an easy and highly accurate technique for the characterization of the
specific thermal properties of the thin insulating layer of an IMS substrate, which is independent from
the sample geometry.
The figure 6A shows the cross-section of a power device in a SO10P package soldered to an IMS
substrate and placed on a thermostatic plate. The same system is shown in the top view photograph
of figure 6B where the encapsulating plastic of the device was eroded with the aim to highlight the
geometry of the inner silicon chip. The sample was kept in vacuum in order to eliminate any heat
exchange by convection.
The power device provided by ST-Microelectronics is dedicated to package thermal resistance
measurements and contains only a power resistor acting as electrical heather and a temperature
sensing diode whose sensitivity is about 1.85 mV/°C. The thermal resistance of the device-packagesubstrate system is easily statically measured from the ratio between the temperature drop between
the silicon chip and the heat sink and the electrical power dissipated in the heating resistor. Also the
thermal resistance of the device itself was experimentally measured.
The thermal resistance of the structure depends not only on the specific thermal conductivities of all
the layers but also on geometrical factors. It means that this value depends on the spreading of the
heat flux within the structure. Note that in the structure of fig. 6A the only unknown parameter is just
the thermal conductivity of the thin insulating layer since all the geometrical (thicknesses, lateral sizes)
and thermal factors of the standard materials are known. Therefore using the DJOSER program it is
possible to build the model (the effects of the device pins are supposed to be negligible) and perform
several simulations by changing the thermal conductivity of the insulator layer.
The figure 6C shows the result of the DJOSER simulations which is the plot of the maximum device
temperature (i.e. the device thermal resistance for 1 W of power dissipation) as a function of the
specific thermal resistivity (the corresponding thermal conductivities are reported in the plot as point
labels) used in the DJOSER models. The pursued conductivity value can be easily interpolated within
this plot at the experimental thermal resistance. However for a best accuracy, the device model was
previously modified by adding a proper thermal contact resistance between the silicon chip and the
lower copper frame so that the calculated thermal resistance of the model is exactly the same of that
obtained from the experiment.
Also note that, for this characterization only the maximum temperature in the silicon chip centre is
needed so that the simulation procedure is very fast since in this case the time consuming
temperature maps calculations are disabled.
3.3 Evaluation of the external heat spreader
One of the most important technical need concerning the power electronic device assembling in very
large range of applications is the design of a proper heat spreader for cooling the device and keeping
the maximum temperature inside the safe range. In particular this need is now becoming crucial for the
lighting systems in which the usual traditional lamps are replaced by groups of high efficiency LED
devices, thus gaining advantages in terms of compactness and lower energy consumption. However
the external cooling apparatus is always needed in applications for public lighting requiring high
luminance (especially for tropical countries with higher air temperatures) since the heat dissipation in
quiet air is very poor and the lamp cannot be provided with an active electrical refrigerating system;
therefore the use of an external metal heat spreader is a mandatory choose.
To perform the design of this component some practical formulas are generally provided by the
manufactures with which the maximum device temperature can be roughly foreseen. However the use
of these formulas does not allow to directly see the effects of the heat spreader presence on the
temperature distributions within the inner parts of the packaging structure and the effects of the quality
of the thermal connection between the heat spreader and the substrate.
The DJOSER software provides the possibility to simulate the presence of a heat spreader on the
bottom or top surfaces of the whole assembling structure, taking into account the quality of the contact
with the heat spreader (by setting a proper thermal contact resistance at the interface) and in the same
time to still obtain the corresponding temperature maps at all the structure interfaces.
The figure 7A shows an assembled power device with a metal heat spreader at the bottom surface
2
exchanging heat with quiet air whose coefficient Ho is typically in the range 4-8 W/m °C. Although the
geometrical configuration of the heat spreader cannot be represented in the DJOSER model, however
its presence can be modelled using the below described strategy. The heat exchange by convection at
a surface in contact with a fluid is ruled by the following basic relationship:
Q = Ho ⋅η ⋅ As ⋅ (Tj − Ta ) ,
(4)
where Q is the heat flux exchanged, Tj and Ta are the temperature of the surface and the fluid
respectively, As is the total exposed surface of the spreader and η is a number lower than unit
representing the efficiency of the metal fins. In other words, the dissipating structure is able to
decrease Tj by increasing the area of the heat exchange process. However the equation (4) can be rewritten in the following way:
Q = H * ⋅ Ao ⋅ (Tj − Ta )
being
H * ⋅ Ao = Ho ⋅η ⋅ As ,
(5)
where Ao is the area of the flat interface and H* is an increased value for the convection heat
exchange coefficient, eventually also very unrealistic. Therefore the effect of an external heat spreader
having an effective area (η As) exchanging heat with a Ho coefficient is equivalent to that of a flat
surface having Ao area exchanging heat with the fluid with an increased H* coefficient. The figure 7B
FIG. 7. (A) Cross-section of an assembling structure with a bottom thermal dissipator. (B) Results of
the DJOSER simulations: plot of the device maximum temperature vs the normalized dissipator area.
shows the plot of the maximum temperature calculated by DJOSER within the silicon surface of
thedevice, having a small heat source area but high power density, as a function of the ratio (H*/Ho)
which is equal to the ratio (η As/Ao) and can be called “normalized dissipator area”. This type of plot
allows choosing the proper heat spreader characteristics in order to decrease the device maximum
temperature below a given safe value.
The DJOSER pre-processor is just provided with a routine for the automatic generation and running of
the input files for this analysis and the production of the plot of the figure 7B.
3.4 Multi-pyramidal applications: coupling LEDs with IMS substrates
Although the DJOSER program can be applied to simulate single pyramidal structures (a single stack
of rectangular layers), many real application cases may be addressed as “multi-pyramidal structures”.
It means that, as shown in the figure 8A, many devices are placed on the same multi-layered
substrate, all of which dissipate a given power, inject an heat flux on the common substrate and
therefore contribute to warm up the substrate and the other surrounding devices. This is the case, for
instance, of a lighting system using a matrix of power LEDs (see the figure 8B showing the view of a
device manufactured by LUXEON), all mounted on the same substrate.
However the thermal analysis of the whole system cannot be performed by taking into account only
one device.
There are two ways to still use DJOSER overcoming this impediment. The first one is provided by the
linear nature of the thermal system and consists of many simulation as the number of the devices on
the same substrate, each device located on the substrate on its own position.
The temperature map of the common substrate can be obtained by summing all the partial maps due
to the various devices. Furthermore, the temperature maps internal to a single device can be obtained
by simulating only the device, without the substrate, but imposing on its bottom surface the total
temperature distribution on that substrate area covered by the device itself. The solution provided by
this method is exact also in presence of convection heat exchange on any surface of the solid system.
The second method is more practical and fast but almost approximated.
The thermal analysis of the multi-pyramidal system can be carried out as shown in the figure 8C. The
structure is composed by only one device, chosen as that located in the worst position from the
thermal point of view (in the centre for the present case).
The other devices are represented by 2-D uniformly distributed heat source islands located on the
substrate at the positions of the other devices and equal to the heat fluxes injected by them. In this
way the temperature maps on all the layers of the structure, including those internal to the central
device, can be directly obtained with only one simulation run.
However the solution is exact if the whole structure or at least the device are adiabatic (does not
exchange heat with the ambient). This hypothesis can always be retained valid in the cases of
thermally not-resistive contact with the heat sink and in presence of poor values of the convection
coefficient as those corresponding to the quiet air.
As an application example of this latter strategy, the simulations corresponding to the coupling of
seven LEDs to an IMS substrate are reported.
The IMS substrates have 1.6 thick aluminium (AL6082) with thermal conductivity 170 W/m°C and 125
microns thick insulating layer with three different values for the thermal conductivity ki : 0.6 , 1.4 and
2.2 W/m°C.
The LED device, dissipating a net electrical power of 1 W and considered as adiabatic, was
represented by superposition of the semiconductor chip and of three different copper layers just for
faithfully reproducing the shape of the internal heat spreader.
The substrate was supposed to be in perfect contact with the heat sink (To = 0 °C).
The figure 9 shows the results and the comparison among the three simulation runs. The figures 9A
and 9B show the temperature colour-scaled maps on the top semiconductor surface (where the
maximum temperature is located, about 16.53 °C) and on the top of the insulating layer (Tmax = 2.68
°C) respectively. The two maps are referred to the sample with ki = 1.4 W/m°C.
The figure 9C shows the two-dimensional temperature distributions for the three cases and along the
medium horizontal axis of the semiconductor chip in the central LED.
The comparison among the curves clearly describes the dependence of the device self heating on the
thermal conductivity of the IMS insulating layer which is the most crucial factor of the mounting
system.
However the low maximum temperature values showed in the present example are mainly due to the
not-resistive contact with the heat sink. Much higher values could be found if the bottom aluminium
surface exchanges heat by convection.
FIG. 8. (A) View of the multi-pyramidal structure composed by power LEDs. (B) View of the power
LED by LUXEON. (C) Equivalent DJOSER model used for the thermal simulations.
FIG. 9. Results of the DJOSER simulations. Colour-scaled temperature maps for the top
semiconductor (A) and the insulator (B) (case of ki = 1.4 W/m°C). (C) Medium temperature horizontal
distributions on the semiconductor for three different values of the insulator layer thermal conductivity.
4 CONCLUSIONS
In the present paper the structure and characteristics of thermal simulation system for electronic
assembling structures was briefly presented and discussed.
This software tools, which in the past was presented to the scientific community, is mainly based on
the analytical resolution of the basic equations of heat transfer in a geometrical system which well
represents most of the mounting configurations of power electronic devices and their usual boundary
conditions. It was designed just with the aim to replace or to grant an alternative tool to the programs
using the traditional finite-element calculation strategy, while maintaining the same accuracy degree
and hence to spread the thermal analysis culture also in the academic and industrial environments not
traditionally involved in FEM analyses.
The successful realization of this aim was testified by the increased number of applications in which
the DJOSER program is currently called to operate, ranging from hybrid technology sensor prototypes
analysis [9] and flat thick film heathers for consumer electronics to the design of mounting structures
using highly conducive substrates such as IMS, both for automotive and lighting applications. This
activity is currently carried out not only by our academic laboratories but also within a close
collaboration with an industrial subject (EFFEI s.r.l. of Sesto Fiorentino, Florence, Italy) involved in the
electronic board production, assembling and design. This industry uses the software to offer thermal
analysis services to their customers, helping them in the thermal design and optimization of their
products.
As far as the didactic characteristics are concerned, it is very significant that the DJOSER program is
currently used as a learning tool within the Laurea degree courses not only in Electronics (Industrial
Electronic course) but also in Engineering Management (Applied Electronics course) which is devoted
to the preparation of engineers specialized in quality control of industrial processes.
Many applicative theses about the thermal analysis performed with the DJOSER program were
recently assigned to students belonging just to this second Laurea degree course.
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