ACT4: A High-Precision, Multi-frequency Electrical Impedance Tomograph
Ning Liu, Gary J. Saulnier, Jonathan C. Newell and Tzu-Jen Kao
Rensselaer Polytechnic Institute, Troy, NY 12180, U.S.A.
Abstract:
This paper describes the design, architecture and the performance of ACT 4, Rensselaer’s 4th generation
electrical impedance tomograph. ACT 4 has a modular design that can support up to 72 electrodes with
an excitation frequency that is selectable from a discrete set in the range from 300 Hz to 1 MHz. The
instrument is able to apply either voltages or currents to all the electrodes simultaneously and to measure
the resulting currents or voltages. The system can control both the phase and amplitude of the voltage or
current excitation and, likewise, measures real and reactive current and voltage values. The analog
electronics are supported with a distributed digital system, including a computer, Digital Signal
Processors (DSPs) and Field-Programmable Gate Arrays (FPGAs). The overall system architecture is
presented as well as details concerning the implementation of the FPGA firmware. Some preliminary
performance results using 32 electrodes are shown.
Keywords: Electrical impedance tomography, FPGA
1. Introduction
Electrical impedance tomography (EIT) is used to determine the electrical conductivity and permittivity
distribution within a body from electrical measurements made on its surface. The system described here
is RPI’s fourth generation adaptive current tomograph (ACT4) that can support up to 72 channels (each
channel interfaces with one electrode) with each channel having an independent voltage and current
source as well as an ammeter and voltmeter. Consequently, ACT4 can be used in either an applied
voltage or an applied current mode. The system applies sinusoidal excitation signals at 8 discrete
frequencies within the range from approximately 300 Hz to 1 MHz. We have 16 bits of control for both
the real and imaginary parts of the excitation signal, providing independent amplitude and phase control
for each channel. The sampling frequency is approximately 1 MHz as determined by the analog-todigital converters (ADCs) used in the analog electronics in the electrode support modules (ESM) [1].
The instrument behavior and performance are largely determined by the system software and firmware,
making it possible for it to be programmed for specific functions. The sections below will describe the
system architecture, with particular emphasis on the firmware used in the FPGA devices.
2. System Architecture
The ACT4 consists of a host computer and custom-made instrument hardware as shown in Figure 1. A
Hammerhead DSP board (Bittware, Inc.), containing four Analog Devices ADSP-21160 DSPs, occupies
one PCI slot in the host computer. This Hammerhead board will be used to perform image
reconstructions. A Bittware Reef PMC+ daughter board, containing one ADSP-21160 DSP and one
Xilinx XC2V1000 Virtex-II FPGA, resides on a Mezzanine connector on the Hammerhead board. The
host computer interfaces with the custom instrument hardware using two 68-lead SCSI-III style
connectors that link the FPGA on the Reef board with a Master FPGA in the hardware, which, in turn,
interfaces with a 12-slot VME64x backplane. The Master FPGA resides on one of several identical
“digital boards” in the system. Each digital board has a Xilinx XC2V2000 Virtex-II FPGA, two PROMs
to store the FPGA, and a set of backplane transceivers. The digital boards each contain 8 mezzanine
locations and five different kinds of modules presently can be populated onto these locations - electrode
support modules, a calibration module, interface modules, a calibration multiplexer module, and a safety
module. These modular exchange capabilities provide easy reconfiguration and future expansion. The
FPGAs on digital boards other than the one used to interface with the host are called “slave FPGA”s.
1
The hardware mentioned above, plus linear and switching power supplies, an isolation transformer,
cooling fans, and electromagnetically compatible (EMC) subrack, are all contained in a 40” H x 19” W
x 20” D outer enclosure. Figure 2 shows photographs of the ACT 4 system.
MBLT
Xilinx Virtex-II FPGA XC2V2000
56 x 18 Kbits (1008 Kb) Block RAM
336 Kbits Distributed RAM
can be only access locally
Xilinx Virtex-II FPGA XC2V2000
56 x 18 Kbits (1008 Kb) Block RAM
336 Kbits Distributed RAM
can be only access locally
DSP1
Slave
FPGA
ESM(0)
DSP2
PCI
User
Interface
PCI
CON B
DSP3
PMC
Reef
DSP
Reef
FPGA
Master
FPGA
MBLT
VME
Bus
CON A
DSP4
MBLT
Slave
FPGA
ESM(8)
MBLT
Slave
FPGA
calibration
Reef PMC+ Board
ADSP-21160
Xilinx Virtex-II FPGA XC2V1000
256 MB SDRAM 40 x 18 Kbits (720 Kb) Block RAM
Memory can be
160 Kbits Distributed RAM
assessed only by local
can be only access locally
DSPs. But can be called
from PC by DLL
functions
Hammerhead
Recontructor
Quad Analog Device
ADSP-21160
256 MB SDRAM
Memory can be assessed only
by local DSPs. But can be called
from PC by DLL functions
Figure 1: System architecture
Figure 2: ACT 4 System Hardware. Left: Complete unit. Center: Digital board with two interface
modules, one calibration module and one ESM. Right: Coaxial cables on the front of the digital boards.
3. Signal Generation and Voltmeter
A total of 8 ESM modules are located on a single digital board and are controlled by a single slave
FPGA that provides a unique digitized excitation waveform to the digital-to-analog converter (DAC) on
each ESM, interfaces with the ESM ADCs and exercises the ESM control lines.
A direct digital synthesizer (DDS) is used to generate a sinusoidal signal for the system. This DDS is
implemented in the FPGA using the IP Core from Xilinx [2]. The phase increment is used to set the
output frequency, since the phase is advanced by this amount during each clock interval. Uniformly
sampled sinusoidal amplitudes are stored in the lookup table. The sine and cosine outputs of the lookup
table are sent to eight of complex modulators, each of which multiplies them by the constants, Ai and Bi,
where i is the channel number, and sums the result. With this approach, we can produce 8 signals of the
same frequency and different phases and amplitudes using a single DDS.
2
We choose a matched filter (MF) as the basic voltmeter structure since it has the maximum output signal
to noise ratio among all linear filters for a deterministic signal embedded in additive white noise. The
MF structure can also be derived as a Maximum Likelihood Estimator (MLE) assuming the dominant
noise source is additive, white, and Gaussian. Details concerning the algorithm can be found in [3].
4. FPGA Implementations
4.1. Backplane Protocol
The VME64x backplane is used for communication between the Master and the Slave FPGAs. The
protocol is a modified version of the standard “A24:MBLT” VME64 read/write cycle. The protocol
includes the use of data lines, address lines, and system control lines.
4.2. Pattern Control and Data Collection
Two 68-conductor SCSI-III style connectors link the Reef FPGA on the Reef board to two interface
modules in the ACT4 hardware which connect to the Master FPGA. Using LVDS protocol, these two
can transfer 68 signals. Before taking data, the DSP on the Reef board initializes the hardware by
downloading all the necessary parameters into the Master FPGA which, in turn, sends them to the Slave
FPGAs. There are two modes for taking the data, single-shot and continuous mode. In single-shot mode,
only one channel generates a signal and only one measurement is made. This mode is used for hardware
debugging and calibration. In continuous mode, all the channels generate signals and make
measurements simultaneously, following a downloaded voltage/current pattern. For an n-electrode
system, we need n-1 patterns to reconstruct a frame of data. These n-1 patterns can be made to repeat
continuously, producing reconstructed images in real time.
The Master FPGA controls the timing in continuous mode through a set of global signals sent via the
backplane to the Slave FPGAs. It also retrieves the measurement data from the Slave FPGAs after each
excitation pattern is applied and temporarily stores this data in a local data buffer until it is uploaded to
the memory associated with the DSP on the Reef board and, finally, to the user interface.
4.3. Electrical Support Module Interface
An ESM contains all of the electronics necessary to support a single electrode. The DAC output
connects to a current source and voltage source through switching circuitry, and ultimately to a shield
driver and the electrode. Voltage and current measurement circuitry provides an input signal to an ADC
that interfaces with the Slave FPGA. A pair of SMB connectors on the front edge of the ESM permit
connection to the calibration module and to the electrode.
The Slave FPGA stores the initialization parameters in the register buffer and uses them to control the
relays and multiplexers. It also has the serial interface to program the digital potentiometers (digipots),
the parallel interfaces to drive the DACs, and the serial interfaces to communicate with ADCs. One DDS
described above generates sinusoid signals to be modulated for the DAC on each ESM. The matched
filters process the voltage data from ADCs and produce complex voltage measurements that are initially
saved in a register buffer to be collected by the Master FPGA through the backplane.
5. Instrument Calibration
The ESMs implement the Howland source/Generalized Impedance Converter (GIC) described in [4].
This source must be “tuned” to maximize the output impedance at the excitation frequency. To allow
operation at discrete frequencies in the range of 300 Hz to 1 MHz, this tuning process requires both the
selection of a set of component values suitable for the desired operating frequency using multiplexers
and, second, fine tuning through the adjustment of four digipots on each ESM. Each ESM has a
3
connection to the single calibration module that is used to measure the current source output impedance
and guide the tuning process (a bisection algorithm) to peak the output impedance values.
Precise voltage sources are an alternative to the conventional current source approach and are easier to
implement. These sources can either be used directly in a less optimal EIT system, or can be used to
apply a desired current pattern [5]. The voltage sources in ACT4 directly measure both the applied
voltage and the applied current. As with the current sources, all voltage sources connect to a single
calibration module so that they can be calibrated to a common reference. The calibration process reduces
the impact of stray shunt impedance, passive component variability, active component non-ideality, and
cable inductance. After calibration, a set of calibration parameters are obtained and stored for each ESM
module for each excitation frequency. These calibration values are applied to raw measurement data to
get the complex voltage and current values.
6. Preliminary Results
We are presently testing ACT4 in applied voltage mode with 32 electrodes. Figure 3 shows preliminary
static reconstructions at 10 kHz and 1 MHz for a saline-filled circular tank containing a phantom heart
and lungs. The real reconstructions are virtually identical at both frequencies while the reactive images
show some artifacts.

10 kHz


1 MHz

Figure 3: Preliminary ACT4 images
Acknowledgments
Supported by NSF Grant EEC-9986821 and Grant R01-EB000456-01A2, National Institutes of Health.
References
1. Ross, A. S., An adaptive current tomograph for breast cancer detection, Ph.D. dissertation,
Rensselaer Polytechnic Institute, Troy, NY, 2003
2. Direct digital synthesizer (DDS) v4.0 [Online], Xilinx Inc., Available:
http://www.xilinx.com/ipcenter
3. Liu, N., G. J. Saulnier, J. C. Newell, “A Multichannel Synthesizer and Voltmeter for Electrical
Impedance Tomography”, Proc. of 25th Annual International Conference of IEEE EMBS, pp
3110-3113, 2003
4. Ross, A. S., G. J. Saulnier, J. C. Newell, and D. Isaacson, “Current source design for electrical
impedance tomography,” Physiol. Meas. vol. 24, pp. 509-516, 2003.
5. Choi, M. H., D. Isaacson, G. J. Saulnier and J. C. Newell, “An iterative approach for applying
multiple currents to a body using voltage sources in electrical impedance tomography,”
Proceedings of IEEE-EMBS Conf. 25:3114-3117, 2003.
4