DSP-based PLL-controlled 50–100 kHz 20 kW highfrequency induction heating system for surface
hardening and welding applications
.
N.S. Bayındır, O. Kukrer
and M. Yakup
Abstract: A digital signal processor (DSP)-based phaselocked loop (PLL)-controlled highfrequency induction heating system is described. The rectifier and insulated gate bipolar transistor
(IGBT) inverter are controlled by a TMS320F240 DSP system, which has the hardware feature of
providing a dead-band delay independent of the frequency of operation. This feature, together with
the high speed of the DSP, allows the use of zero current resonant switching at a high power factor
for frequencies up to 100 kHz. Resonant operation of the inverter is maintained by a simple digital
PLL scheme implemented on the DSP. The frequency converter enables safe operation at all load
conditions with digital overcurrent, overvoltage and overtemperature protection features. The costeffective system described is operated successfully at outputs up to 19.8 kW at 72 kHz and 500 V.
1
Introduction
High-frequency induction heating furnaces are widely
used in applications such as surface hardening, welding,
metal to plastic or metal to glass bonding and curing.
The higher efficiency, very short heating times and local
heating capabilities of induction heaters have made them
superior to other heating devices. With the latest advances
in power semiconductor switching devices and microprocessors, high-frequency induction heating power supplies
are now more reliable and cost-effective and have higher
performances [1–4]. In [4] a pulse amplitude modulated
voltage source, series load resonant inverter has
been developed using high-power static induction transistors (SITs), which operates at a load-adaptive tuned
operating frequency that is slightly higher than the series
resonant frequency in order to achieve zero-voltage
soft-switching commutation. A phaselocked loop integrated
circuit (PLL-IC) is used to provide load resonant operation
based on the phaselocked loop principle. Due to the
difference between the switching frequency and the
load resonant frequency, the power factor has been
degraded by 5% and oscillations are observed at the
switching instants. Moreover with this method the delay
between the inverter output voltage and current waveforms
cannot be maintained at the same level at all frequencies
due to the change in component characteristics with
frequency. In [1], a half-bridge inverter circuit with series–
parallel resonance is described which does not use an
impedance matching transformer. Series and parallel
compensating capacitors are used to reduce the reactive
r IEE, 2003
IEE Proceedings online no. 20030096
doi:10.1049/ip-epa:20030096
Paper first received 29th April 2002 and in revised form 25th September 2002
N.S. Bayındır and O. K.ukrer are with the Department of Electrical and
Electronic Engineering, Eastern Mediterranean University, G. Magosa, Mersin
10, Turkey
M. Yakup is with the Technology Development Centre, Eastern Mediterranean
University, G. Magosa, Mersin 10, Turkey
IEE Proc.-Electr. Power Appl.
loading of the workpiece and also to increase the load
current with respect to the inverter current. However, the
method is valid for coil inductance values less than twice the
total series stray inductance in the circuit. Another
disadvantage is the use of an extra capacitor, which is
expensive at the frequencies in question. A comparison of
series and parallel inverter systems [5] has revealed that the
voltage source series resonant inverter offers better overall
performance than the parallel resonant counterpart with
respect to converter utilisation. Considering the results of
this comparison, the series resonant inverter topology has
been adopted in this project.
In this paper digital signal processor (DSP)-based PLL
control scheme is presented in which the phase difference
between the inverter voltage and current is minimised and
made independent of the operating frequency. The hardware dead-band feature of the DSP is used, in conjunction
with software-based PLL control, to achieve precise zerocurrent switching operation so that the di/dt stresses on the
insulated gate bipolar transistors (IGBTs) are minimised
and switching occurs with negligible oscillations. The DSPbased digital control approach enables easy implementation
of various monitoring and protection functions, in addition
to the built-in dead-band feature. Furthermore, a digital
implementation of the PLL scheme is more reliable than an
analogue implementation, where changing component
characteristics may degrade performance in time. Moreover,
in analogue implementations of PLL control the dead-band
time may vary with operating frequency, which then
degrades the power factor.
The design and constructional features of the whole
system are presented in this paper. Experimental work has
been carried out on the induction heating system to measure
the operational performance under various loading conditions. Experimental results indicate that the system operates
successfully with a power factor very close to unity. A
simulation model has been developed using Simulink, which
has been used to analyse and design the PLL control
system. A mathematical model of the system has also been
developed in discrete time, with which the stability of the
system can be assessed.
1
2
System description
Xf
The general layout of the frequency converter is shown in
Fig. 1, where it may be seen that the output power is
controlled by a three-phase controlled rectifier and that the
inverter is of the voltage-fed load resonant type. High-speed
IGBTs with fast anti-parallel diodes are used in the inverter.
RC snubbers are used to reduce the dv/dt stresses on the
IGBTs. A high-frequency impedance matching transformer
with a turns ratio of 5/1 has been designed and constructed
with an amorphous core on which the primary and
secondary coils are wound using Litz wire, and this is used
to isolate and match the impedances of the converter and
the induction heating coil. The induction heating coil and
the impedance matching transformer are water cooled. A
high-frequency compensating capacitor of value Cs ¼ 1 mF
(500 kHz, 600 V) is connected in series with the coil (Ls).
The inverter output voltage and the capacitor voltage are
measured by means of high-frequency voltage transducers
to provide the necessary inputs to the DSP for PLL control.
The inverter and coil currents are also measured to track
the load resonant operation and also to measure the
efficiency of the converter and of the impedance matching
transformer.
DSP
TMS320F240
optoisolator
impedance
matching
transformer
inverter
resonant load
(capacitor+
inductor)
vi
phase
detection
circuit
optoisolator
zerocrossing
circuits
vc
Fig. 2 Block diagram of PLL-based control system
Rf
Xf
XOR
Cf
Fig. 3
Phase detection circuit
initiate dead-band
routine
LF
+
T1
3-ph
supply
CF
T3
Vdc
T4
Ls(Rl)
wait for end of
conversion
T2
voltage
transducer
3-ph controlled
rectifier
start A/D
converter
Cs
voltage
transducer
DSP based PLL
control system
Fig. 1 General layout of high frequency induction heating system
3
acquire phase error
[eD (k)]
calculate new inverter period
Tc (k+1) = Tc (k)+KcD.eD (k+1)
DSP-based PLL control system
Tc (k+1) < Tmin
3.1
Tc (k+1) = Tmin
Control system description
A simple DSP-based PLL control algorithm has been
developed in which the dead-band delay is provided by the
special hardware feature of the TMS320F240 DSP system.
The digital implementation of PLL maintains resonant
operation over a wide range of frequencies from 50 to
100 kHz. A block diagram of the PLL system is shown in
Fig. 2. The capacitor voltage vc and the inverter output
voltage vi are measured with high-frequency voltage
transducers with negligible delay and the zero crossings of
these voltages are detected and compared in an XOR gate,
as shown in Fig 3. The output of the XOR gate is filtered to
yield a DC voltage (xf) proportional to the phase difference
between the inverter and capacitor voltages. This voltage is
isolated optically and applied to the analogue input of the
DSP, where digital implementation of the PLL scheme is
then realised. The flowchart of the PLL control algorithm
is shown in Fig. 4. The voltage input to the DSP, which is
proportional to the phase difference between the inverter
output and the capacitor voltages, is compared with a value
corresponding to 90 degrees and the switching frequency is
adjusted so that this difference is made zero. When this
condition is achieved, the capacitor and the inverter voltages
2
yes
no
Tc (k+1) > Tmax
yes
Tc (k+1) = Tmax
no
update counter
period in dead-band
Fig. 4 PLL control algorithm
are in quadrature, which ensures that the inverter voltage
and current are in phase.
The pulse width modulated (PWM) outputs of the DSP
are used to generate switching pulses for the inverter
IGBTs. The PWM periods determined by the PLL
algorithm are loaded into the timer control register
T1CON, which then starts generation of the PWM
IEE Proc.-Electr. Power Appl.
switching pulses. The dead-band delay between the switching instants of the IGBTs on the same leg of the inverter is
provided by the dead-band control register DBTCON,
which is set at 0.8 ms. This delay is adjusted by the special
hardware feature of the DSP, and is independent of the
processing delays. This feature of the DSP maintains a
constant delay at all frequencies, which is not possible in
analogue circuit implementations of PLL control due to the
variation of component characteristics with frequency
(particularly in the high-frequency range). The DSP
operates at a speed of 20 MIPS, which makes it possible
to control the system up to 100 kHz.
During experimentation, a lower frequency limit
of 50 kHz and an upper frequency limit of 100 kHz
were set on the control system so that the operating
frequency could never exceed these limits accidentally. The
switching signals are isolated and amplified before they are
applied to the gates of the IGBTs using a signal
conditioning circuit.
3.2
Mathematical model
An approximate discrete-time model of the system was
found to be useful in designing the control system. Referring
to Fig. 4, the PLL control is implemented in discrete-time
by the following equation:
T ðk þ 1Þ ¼ T ðkÞ þ Kc eðk þ 1Þ
ð1Þ
which corresponds to integral action.
In (1) T is the inverter voltage period (represented by Tc
in digital form in Fig. 4), Kc is the integral gain (represented
by KcD) and e is the error in phase difference (represented
by eD) defined as
eðkÞ ¼ xf ðkÞ 12
ð2Þ
where xf is the average value of the normalised LP filter
output (Fig. 5).
vc
vi
However, in transient operation xf should be related to uf
by the differential equation
dxf
1
1
f
ð4Þ
¼ x f þ uf
uf ¼
tf
tf
p
dt
where tf ¼ RfCf is the time constant of the filter.
Note that in (4) uf is a function of the frequency of the
inverter voltage (or its period) through the phase difference
f. Considering the steady state operation of the resonant
load of the inverter, the following relationship can be
obtained between f and T:
(
)
2p
R
C
l
s
1
T
ð5Þ
fðT Þ ¼ tan
1 ðo2p0 T Þ2
pffiffiffiffiffiffiffiffiffi
where o0 ¼ 1= Ls Cs ; Ls is the inductance of the heating
coil and Rl is its equivalent resistance.
It is assumed that the relationship (5) is approximately
valid during transient operation in which the period T
changes slowly. Furthermore, (5) is obtained by assuming
that the inverter output voltage is purely sinusoidal.
Equation (4) can be discretised as follows:
f½T ðkÞ
ð6Þ
xf ðk þ 1Þ ¼ axf ðkÞ þ b
p
where a ¼ eTs =tf , b ¼ (1–a), and Ts is the control sampling
time. Using (1), (2) and (6) the closed-loop system equation
is obtained as
f½T ðkÞ 1
ð7Þ
T ðk þ 1Þ ¼ T ðkÞ þ Kc axf ðkÞ þ b
p
2
Equations (6) and (7) are non-linear, since f is a non-linear
function of T(k). These equations can be linearised easily by
linearising (5) around the operating point, where the
inverter frequency is equal to the resonant frequency of
the load, to give (see Appendix, Section 7)
p
1
ðT T0 Þ
ð8Þ
fðT Þ ’ 2 pRl Cs
where T0 is the inverter period at the operating point.
With the following definitions of perturbation variables:
Dxf ¼xf 12
DT ¼T T0
ð9Þ
the linearised closed-loop equations of the system become
(see Appendix, Section 7)
1
XOR output
yðk þ 1Þ ¼ Ac yðkÞ
uf = xfss
0
In (10) y is the column vector y ¼ [Dxf DT]T and
2
3
a
1a
p2 tr
5
Ac ¼ 4
ð1aÞKc
aKc 1 p2 tr
Fig. 5
Waveforms for PLL operation
Normalisation here refers to a scaling such that the
maximum is unity (corresponding to 100% duty ratio of the
XOR output). Note that the period of the VCO output (T)
is updated instead of its frequency. This is found to be more
convenient since the inverter control program (dead band)
requires period information directly.
Now, it is clear that xf can be expressed in the steady state
in terms of the phase difference f as
xf ;ss ¼
f
¼ uf
p
where uf is the average value of the LP filter input.
IEE Proc.-Electr. Power Appl.
ð10Þ
ð3Þ
where tr ¼ RlCs.
Applying Jury’s stability test [6] to (10), the following
range of gain for stability is obtained:
1þa
0oKc o
ð11Þ
2p2 Rl Cs
1a
4
System modelling and simulation
At the design stage of the induction heating system, a
simulation model of the converter and the load was
developed using the SIMULINK package to estimate the
turns ratio of the impedance matching transformer, the
3
tt
time
clock
v_inv
relay2
LPF
XOR (ZCD)
15000
XOR
s+15000
e = x f -1/2
+
400
vi
vi , V; ic , A
200
ii
0
0.03495
0.03496
0.03497
0.03498
0.03499
0.03500
-200
-400
a
-600
800
600
400
vc
vi
200
0
0.03496
0.03498
0.03497
0.03499
0.03500
-200
inv.voltage
T
in1 out1
0.0
z-1
rate limiter
int. gain discrete-time
VCO+INV
integrator
hold0
600
vi , V; vc , V
compensating capacitor value and the IGBT ratings, as
well as the controller gain. The simulation model is shown
in Fig. 6. The system parameters are Lsp ¼ 122 mH, Csp ¼
0.04 mF, Rlp ¼ 11.1 O (referred to the primary side
of the impedance matching transformer), Ts ¼ 200 ms,
and tf ¼ 68 ms. Note that this model does not simulate
the PLL control algorithm as in the actual practical implementation, with the period T as the output of the
VCO (software version). Instead, the frequency of the
VCO output in this model is controlled by the VCO
input. However, the behaviours resulting from the two
approaches are expected to be similar for sufficiently small
deviations around the operating point. An equivalent gain
of Kc ¼ 5.0 ms has been used in the simulations, which is the
value that corresponds to the gain used in the experimental
system. Note that the theoretical limit for the gain from (11)
is Kco9.8 ms.
-400
Vi Vc
-600
load
-800
b
0.700
relay1(ZCD)
0.650
0.600
0.5
constant
1
Vi
+
sum
cap. voltage transf. ratio
xf
norm. filter volt.
a
1
×
s
prod1 int1
prod2
-K1/Cs
rate lim2
×
v_cap
xf
0.550
1/5
0.500
0.450
0.400
i_inv
inv. current
1
s
int2
R
0.350
start of transient
0.300
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
time, s
1
Vc
c
Fig. 7 Simulation results for induction heating system
Ls
a Inverter voltage (vi) and current (ii)
b Inverter voltage (vi) and capacitor voltage (vc) (referred to inverter
side)
c Transient response of filter output (xf) for a 20% sudden reduction
in the load L and R
rate lim1
b
Fig. 6 SIMULINK model for PLL-controlled induction heating
system
a Complete system
b Resonant load model
Referring to Fig. 6 the capacitor and inverter voltages
are passed through relays, which represent zero-crossing
detectors (ZCD), the outputs of which are applied to
the inputs of the XOR. The lowpass filter (LPF) output
is compared with the reference value of 0.5 and the error
is sampled by a first-order sample-and-hold, which
represents the analogue-to-digital conversion operation.
The discrete-time integrator implements the integral controller. The VCO output in this simulation is the square
wave inverter output voltage, which is applied to the
resonant load model. The rate limiter adjusts the rate of
change of the inverter voltage during switches to practical
values.
Fig. 7 shows sample simulation results for steady-state
and transient operation of the system. In the transient test
case, it is assumed that there are ramp changes in the
inductance and the resistance of the coil from 90 mH to
4
72 mH, and from 10 O to 8 O, respectively (Section 4). This
emulates a transient test on the actual system in which the
workpiece is pulled out by almost 20%. In Fig. 7c it can be
observed that the PLL control strategy keeps the coil
current in phase with the inverter voltage under all
operating conditions.
5
Experimental results
An experimental prototype of the proposed system has been
set up using a Fuji IPM inverter module (7MBP 100RA120), with short-circuit, overcurrent, overtemperature and
undervoltage protection logic. The system has been
operated at an output power of 19.8 kW, an operating
frequency of 72 kHz and an input voltage of 500 V. The
inverter output voltage and current, and the capacitor
voltage are presented in Figs 8 and 9. In Fig. 8c IGBT
collector–emitter voltages have been measured at 400 V,
which is the maximum range of the oscilloscope. The output
voltages of the PLL circuit (XOR and LP filter outputs)
were also measured and are presented in Fig. 10. A
transient test has been performed at a lower power of
IEE Proc.-Electr. Power Appl.
vi
ii
0
voltage: 200 V/div, current: 20 A/div, time: 2.5 µs/div
(i)
vi
ii
0
voltage: 200 V/div, current: 20 A/div, time: 1 µs/div
(ii)
a
0
vc
vi
0
voltage: 200 V/div, time: 2.5 µs/div
b
0
voltage: 50 V/div; time: 500 ns/div
c
Fig. 8 Experimental results for 19.8 kW output
a (i) Inverter voltage (vi) and current (ii). (ii) Inverter voltage and current, reduced timescale (1 ms/div)
b Inverter voltage (vi) and capacitor voltage (vc)
c Collector–emitter voltages of IGBTs on the same inverter leg
3.3 kW with a different coil, where the workpiece was
suddenly partially pulled out of the coil (by about 20%).
The transient change in the filtered output shows that the
PLL control system brings the system back to unity power
factor operation in about 50 ms. It is difficult to make a
comparison with the simulation result under similar
IEE Proc.-Electr. Power Appl.
conditions, since the exact conditions in the test cannot be
modelled in the simulation. However, the response time in
the simulation is around 30 ms, which roughly agrees with
the practical result. Note that in the simulation result the
transient starts at t ¼ 250 ms and comes to an end at
t ¼ 280 ms. Comparison of steady-state experimental and
5
ZCD
output
vi
ii
0
XOR
output
0
voltage: 2 V/div, time: 2.5 µs/div
a
voltage: 200 V/div, current: 20 A/div, time: 2.5 µs/div
Fig. 9 Inverter voltage and current for a dead-band time of 1.2 ms
simulation results reveals that the system design based on
the simulation model closely follows the predicted behaviour.
Referring to Fig. 8a, (i), it can be observed that
the inverter switches at exactly zero current which ensures
unity power factor. This also means that switching losses
are minimised as a result of zero current switching. Hence,
in efficiency calculations the switching losses can be
neglected and an estimate of the overall efficiency of the
inverter based on conduction losses only can be obtained,
using
2VCE;sat
100%
Z¼ 1
Vdc
b
start of transient
ð12Þ
as 98.9%. In (12) VCE,sat represents the saturation voltage of
the IGBTs.
Fig. 8a, (ii) displays the inverter current and voltage on
a much smaller time scale and shows that the current
and voltage waveforms are exactly in phase. It may also
be noted that the inverter switches in 1.2 ms. Furthermore,
the inverter voltage exhibits no oscillations during switching
intervals. This is the result of zero-current switching and
the very small leakage inductance of the impedance
matching transformer. The IGBT collector–emitter voltages
(for IGBTs on the same inverter leg) on a narrow time
scale are shown in Fig. 8c, where it is also clear that the
IGBTs switch in about 0.8 ms, which is consistent with
Fig. 8b. Note that the IGBTs on the same leg switch
almost simultaneously without giving rise to shoot-through,
which is again a result of zero-current switching. Fig. 8b
shows that the inverter and capacitor voltages are
phaseshifted by 901, which demonstrates that the
PLL scheme operates successfully. The effect of increasing
the dead-band duration on the inverter output voltage
is illustrated in Fig. 9, where the dead-band is adjusted
to 1.2 ms. The oscillations in the voltage during the switching
intervals are the result of the feedback diodes trying to turn
on as the load current reverses direction when the outgoing
transistors are turned off. During this transition period,
the incoming transistors remain off due to the increased
dead-band. It is evident that such oscillations give rise to
extra losses. Therefore, it can be concluded that the deadband duration is very critical in zero-current switching
applications.
6
voltage: 100 mV/div, time: 2.5 µs/div
voltage: 100 mV/div, time: 50 ms/div
c
Fig. 10
a XOR output (lower trace)
b Lowpass filter output in steady-state
c Lowpass filter output for transient case
6
Conclusions
A DSP-based PLL-controlled induction heating system has
been described in which zero-current switching of the
IGBTs and operation at unity power factor with negligible
oscillations on the inverter voltage are achieved through a
software-based PLL control scheme using a DSP which has
a hardware dead-band feature. The proposed DSP-based
IEE Proc.-Electr. Power Appl.
PLL controller is more flexible and precise than conventional analogue PLL controllers, allowing easy modification
of control parameters (such as dead-band time and
controller gain) via software, whereas in analogue implementations, which require hardware changes, these modifications would be far more difficult. The dead-band delay
can be kept constant at any predefined value, independent
of the operating frequency, using the built-in dead-band
circuitry. Experimental results reveal that the PLL control
scheme operates precisely as designed and no phase delay
was observed between the inverter output voltage
and current. Transient tests on the system have shown that
after a disturbance the PLL control system brings the
system back to unity power factor operation within a time
of 50 ms.
System parameters such as the turns ratio of the
impedance matching transformer, compensating capacitor
value and IGBT ratings, as well as controller gain were
obtained from a simulation model. Agreement between
predicted simulation results and experimental results have
validated the design.
The use of a DSP-based control system has the
added advantage that different control schemes requiring
different heating periods and different adaptations of the
induction heating system can be implemented with
modifications to the software alone and no changes to the
hardware.
7
Acknowledgments
6 KUO, B.C.: ‘Digital Control Systems’, 1st Edn. (Holt-Saunders
International Editions, Tokyo, 1981)
9 Appendix
The phase difference f can be linearised by means of the
following truncated Taylor series:
df
fðT Þ ’ fðT0 Þ þ
ðT T0 Þ
ð13Þ
dT T ¼T0
where T0 ¼ 2p/o0. The derivative can be evaluated from (5)
as
df
aðT 2 þ T02 Þ
¼ 2
dT
ðT T02 Þ þ a2 T 2
ð14Þ
where a ¼ 2pRlCs. When evaluated at T ¼ T0, this derivative
gives
df
2
1
¼ ¼
ð15Þ
dT T ¼T0
a
pRl Cs
By also noting that f(T0) ¼ p/2, (8) is obtained.
Substituting (8) and (9) into (6) gives:
1
1
Dxf ðk þ 1Þ þ ¼a Dxf ðkÞ þ
2
2
b p
1
þ
DT ðkÞ
p 2 pRl Cs
Simplification using the fact that b ¼ 1a then yields
The authors wish to thank the Eastern Mediterranean
University Technology Development Centre (DAU-TEKMER) for their financial support.
8
References
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IEE Proc.-Electr. Power Appl.
Dxf ðk þ 1Þ ¼ aDxf ðkÞ ð1 aÞ
DT ðkÞ
p 2 Rl C s
ð16Þ
Similarly, substituting (8) and (9) into (7) gives
1
DT ðk þ 1Þ ¼DT ðkÞ þ Kc a Dxf ðkÞ þ
2
ð1 aÞ p
1
1
þ
DT ðkÞ p
2 pRl Cs
2
which simplifies to
DT ðk þ 1Þ ¼ðaKc ÞDxf ðkÞ
ð1 aÞKc
þ 1 2
DT ðkÞ
p Rl C s
ð17Þ
Equations (16) and (17) can then be written in matrix
form as in (10).
7