Vol. 36, No. 1
Journal of Semiconductors
January 2015
Performance analysis of InSb based QWFET for ultra high speed applications
T. D. Subash1; Ž , T. Gnanasekaran2 , and C. Divya3
1 K.N.S.K
College of Engineering, Nagercoil-629901, India
of IT, RMK College of Engineering and Technology, 629401, India
3 Centre for IT & Eng, Manonmaniam Sundaranar University, 627012, India
2 Department
Abstract: An indium antimonide based QWFET (quantum well field effect transistor) with the gate length down
to 50 nm has been designed and investigated for the first time for L-band radar applications at 230 GHz. QWFETs
are designed at the high performance node of the International Technology Road Map for Semiconductors (ITRS)
requirements of drive current (Semiconductor Industry Association 2010). The performance of the device is investigated using the SYNOPSYS CAD (TCAD) software. InSb based QWFET could be a promising device technology
for very low power and ultra-high speed performance with 5–10 times low DC power dissipation.
Key words: QWFET; InSb; gate length; cut-off frequency; short-channel effects
DOI: 10.1088/1674-4926/36/1/014003
EEACC: 2570
1. Introduction
For wireless communication, microwave frequencies in
the L- and S-bands have dominated for surveillance radars both
in commercial and defence applications. An RF output power
on the order of hundreds to thousands of watts is needed for
X- and Ka-band transmitters for radars and X- and C-band
wireless communication systems. InSb has the highest electron mobility and saturation velocity of any known semiconductor (Table 1). Quantum field effect transistors (QWFET)
have emerged as a promising area for microwave power amplification in the field of wireless communications, from highways to electronic warfare. QWFETs are a designed node of the
International Technology Road Map for SemiconductorsŒ1 .
To realize devices beyond the 45 nm technology node,
high mobility materials are required to enhance performance
and to improve the on-current and to reduce the power absorptionŒ2; 3 .
Recently, higher indium concentration In0:7 Ga0:3 As and
InAs channel QWFETs have been experimentally demonstrated with their gate length (LG) down to 50 nm with excellent short channel performance and high speed response operating at a 0.5 V supply voltageŒ4 6 , albeit with a large separation between the source and drain metal electrodes (LSD
D 2 lm). QWFETs were primarily based on AlGaAs/GaAs,
AlGaAs/InGaAs, AlInAs/InGaAs and related epitaxial films
grown on GaAs or InP substrates. In the late 1990s, power
QWFETs grown on sapphire, insulating 4H-SiC, conducting
SiC, and even bulk GaN have demonstrated much larger output powers and have become promising contenders for a variety of high power amplification and switching applications. In
QWFETs based on GaN substrates, this carrier accumulation is
mainly due to polarization charges developed along the heterojunction in the high bandgap AlGaN side. This is in contrast to
the situation in other QWFETs, such as those on GaAs or InP
substrates. Here the accumulation is a result of carrier diffusion
from the heavily doped to the lightly doped region, the diffu-
sion being enhanced significantly by the bandgap difference
between the two regions.
This paper comprises the new design methodology using
InSb in Section 2. The results are discussed in Section 3, and
concluded in Section 4.
2. Device design
The basic AlGaN/GaN power QWFET is shown in Figure 1. The source–drain spacing is from 2 to 7 nm. The gate
length is from 0.25 to 5 nm, whereas the total gate width is
from 50 to 150 nm. The most commonly used substrates are
sapphire (Al2 O3 / and SiC. For the growth of GaN over a substrate, sapphire is cheaper than SiC. However, the low thermal
conductivity of sapphire presents a challenging effect in the
packaging of high power devices. SiC has a lower lattice mismatch with GaN or AlN and 10 times higher thermal conductivityŒ7 . Multilayer metalization schemes are used for the gate,
source and drain contacts. The gate contacts are the Schottky
type which were created using Ni/Au or Pt/Au layersŒ8; 9 . The
source and drain contacts are ohmic and employ Ti/Al/Ni/Au
or Ti/Al/Ti/Au layersŒ10 . The metallisation method used in
GaN devices is different from in GaAs devices for two reasons. Firstly, in GaN devices, it is difficult to create n++ surface
impurity doping during contact annealing. Secondly, the bar-
† Corresponding author. Email: tdsubash2007@gmail.com
Received 17 July 2014, revised manuscript received 13 August 2014
014003-1
Figure 1. Schematic cross sectional view of QWFET.
© 2015 Chinese Institute of Electronics
J. Semicond. 2015, 36(1)
Parameter
Energy gap
Electron effective mass
Electron mobility in pure material
Electron mobility at 1 10 12 cm
Electron saturation velocity
Electron mean free path length
Intrinsic carrier concentration
T. D. Subash et al.
2
Table 1. Channel material properties at 295 K.
Silicon
GaAs
In0:53 Ga0:47 As
1.12
1.43
0.75
0.19
0.072
0.041
1500
8500
14000
600
4600
7800
1.0 107
1.2 107
8 106
28
80
106
1.6 1010
1.1 107
5 1011
InAs
0.356
0.027
30000
20000
3 107
194
1.3 1015
InSb
0.175
0.013
78000
30000
5 107
226
1.9 1016
Unit
eV
—
cm2 /(Vs)
cm2 /(Vs)
cm/s
nm
cm 3
Figure 3. The effective carrier injection velocity versus DIBL.
Figure 2. Ids –Vds characteristics.
rier height increases with increasing the metal work function
in Schottky contacts on AlGaN. Passivation of the gate–drain
and gate–source by depositing SiO2 and Si3 N4 Œ11; 12 arrests
the degradation in maximum current and transconductance due
to the surface charges and traps occur in these regions.
An AlGaN/GaN power QWFET is encapsulated in packages similar to those developed for silicon power devices. Low
power packages include hermetic metal can packages, plastic encapsulations, plastic surface mount packages, and metalceramic packages for severs environmental conditions.
3. Results and discussion
The drain source voltage and current characteristics for different dielectrics at constant Vgs D 1 V, tins D 5 nm with InSb as
the channel material are shown in Figure 1, which is simulated
using the TCAD software. The performances were analysed using commercially available TCAD software, which is shown in
Figure 2. For all the dielectric materials, the saturation occurs
around 0.4 to 0.6 V. ZrO2 has a high saturation voltage around
0.6 V with the highest saturation current. The figure shows that
the drain current increases with an increase in drain voltage up
to the pinch-off voltage; beyond this point, there is no effect of
drain voltage over the drain current, as happens in conventional
MOSFETs.
In Figure 3, it is clearly shown that the effective carrier injection velocity increases as the electrostatic integrity
is aggravated. However, at a fixed DIBL value (100 mV/V),
the simulation result is about 6.9 times higher using veff for
In0:7 Ga0:3 As QWFETs than the one for strained Si nMOSFETs. This increase in injection velocity for III–V compound
semiconductors is a necessity in order to compensate for the
lower carrier density in the channel of III–V QWFETs due to
the reduced density of states in In0:7 Ga0:3 As QWFETs compared to Si MOSFETs.
Figure 4(a) shows that compared to conventional
In0:7 Ga0:3 As QWFETs (circle line), the scalability of all
three QWFETs is improved due to better device architecture
schemes. From this, double-gate In0:7 Ga0:3 As QWFET shows
the best scalability and electrostatic integrity.
Figure 4(b) shows a comparison of various architecture
gate lengths to SS.
A comparative analysis for various architectures of gate
length and Vt is shown in Figure 4(c).
Figure 5 shows the effective mobility as a function of gate
bias for In0:7 Ga0:3 As QWFETs for various gate lengths, such
as 50 nm, 100 nm and 150 nm. It is clear that the effective
mobility reduces as LG is scaled down.
The encapsulating SiN dielectric was selectively removed
only from the immediate T-gate electrode vicinity by taking
advantage of the enhanced reactivity of an HF-based wet etch
around the gate metal.
Figure 6 shows the drain bias dependence of fT and fmax .
4. Conclusion
In summary, for the first time we have designed InSb
QWFET down to 50 nm gate length with 5–10 times lower dynamic power dissipation comparable to today’s Si MOSFETs.
Based on this conclusion, InSb based materials have raised a
good candidate for ultra-high power transistor devices in micro
wave communication and radar applications.
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J. Semicond. 2015, 36(1)
T. D. Subash et al.
Figure 5. The effective mobility as a function of gate bias for
In0:7 Ga0:3 As QWFETs with 50 nm, 100 nm and 150 nm LG.
Figure 6. Drain bias dependence of fT and fmax .
Figure 4. (a) Logic figures of merit for various In0:7 Ga0:3 As QWFET
device architectures. (b) Gate length versus SS. (c) Gate length versus
Vt .
References
[1] http://www.public.itrs.net
[2] Yu B, Wang H, Joshi A, et al. 15 nm gate length planar CMOS
transistor. IEDM Technical Digest, 2001: 937
[3] Doris B, Ieong M, Kanarsky T, et al. Extreme scaling with ultrathin Si channel MOSFETs. IEDM Technical Digest, 2002: 267
[4] Kim D H, Alamo J A, Lee J H, et al. Logic suitability of 50-nm
In0:7 Ga0:3 As QWFETs for beyond-CMOS applications. IEEE
Trans Electron Devices, 2007, 54(10): 2606
[5] Kim D H, Alamo J A, Lee J H, et al. Performance evaluation of 50
nm In0:7 Ga0:3 As HEMTs for beyond-CMOS logic applications.
IEDM Tech Dig, 2005: 767
[6] Kim D H, Alamo J A, Lee J H, et al. Beyond-CMOS: impact of side-recess spacing on the logic performance of 50 nm
In0:7 Ga0:3 As HEMTs. J Semicond Technol Sci, 2006, 6(3): 146
[7] Chen Q, Yang J W, Blasingame M, et al. Microwave electronics
device applications of AlGaN/GaN heterostructures. Mater Sci
Eng B, 1999, 59: 395
[8] Zhang N Q, Keller S, Parish G, et al. High breakdown GaN
HEMTs with overlapping gate structure. IEEE Electron Device
Lett, 2000, 21: 421
[9] Wurfl J, Abrosimova V, Hilsenbeck J, et al. Reliability considerations of III-nitride microelectronic devices. Microelectron Reliab, 1999, 39: 1737
[10] Simin G, Hu X, Ilinskaya N, et al. Large periphery high-power
AlGaN/GaN metal–oxide–semiconductor heterostructure field
effect transistors on SiC with oxide-bridging. IEEE Electron Device Lett, 2001, 22: 53
[11] Green B M, Chu K K, Chumbes E M, et al. The effect of surface passivation on the microwave characteristics of undoped AlGaN/GaN HEMTs. IEEE Electron Device Lett, 2000, 21: 268
[12] Lee J S, Vescan A, Wieszt A, et al. Small signal and power measurements of AlGaN/GaN HFET with SiN passivation. Electron
Lett, 2001, 37: 130
[13] Florian C, Traverso P A, Feudale M, et al. A C-band GaAspHEMT MMIC low phase noise VCO for space applications using a new cyclostationary nonlinear noise model. IEEE MTT-S
International Microwave Symposium Digest (MTT), 2010: 284
[14] Srinidhi E R, Ma R, Kompa G. Application rules for accurate
014003-3
J. Semicond. 2015, 36(1)
T. D. Subash et al.
IMD characterization in GaN HEMTs. Microwave Conference
(GeMIC), German, 2008: 1
[15] Liu H Y, Chou B Y, Hsu W C, et al. Enhanced AlGaN/GaN
MOS-HEMT performance by using hydrogen peroxide oxidation
technique. IEEE Trans Electron Devices, 2013, 60(1): 213
[16] Sato J, Nagai Y, Hara S, et al. Analysis of performances of InSb
HEMTs using quantum-corrected Monte Carlo simulation. International Conference on Indium Phosphide and Related Materials
(IPRM), 2012: 237
[17] Florian C, Traverso P A, Filicori F. The charge-controlled nonlinear noise modeling approach for the design of MMIC GaAspHEMT VCOs for space applications. IEEE Trans Microw The-
ory Tech, 2011, 59(4): 901
[18] Casto M J, Dooley S R. AlGaN/GaN HEMT temperaturedependent large-signal model thermal circuit extraction with verification through advanced thermal imaging. IEEE 10th Annual
Wireless and Microwave Technology Conference, 2009: 1
[19] Liu H Y, Lee C S, Hsu W C, et al. Investigations of AlGaN/AlN/GaN MOS-HEMTs on Si substrate by ozone water oxidation method. IEEE Trans Electron Devices, 2013, 60(7): 2231
[20] Tang Z, Huang S, Jiang Q, et al. High-voltage (600-V)
low-leakage low-current-collapse AlGaN/GaN HEMTs with
AlN/SiNx passivation. IEEE Electron Device Lett, 2013, 34(3):
366
014003-4