International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 10
55
Investigation of Variable Frequency ISPWM
Control Method for an Asymmetric Multilevel
Inverter
R.Seyezhai
Assistant Professor
Department of EEE ,
SSN College of Engineering,
Kalavakkam – 603 110,
Kanchipuram Dt, Tamilnadu, India.
seyezhair@ ssn.edu.in
Abstract—Multilevel inverter is an effective and
practical solution for increasing power and
reducing harmonics of ac waveforms. Several
multilevel topologies are reported and the most
popular topology is Cascaded Multilevel Inverter
(CMLI). This paper focuses on asymmetric
cascaded multilevel inverter employing variable
frequency inverted sine PWM technique
(VFISPWM). This technique combines the
advantage of inverted rectified sine wave and
variable frequency carriers for a seven level
inverter for balancing the switch utilization. A
detailed study of the technique was carried out
through MATLAB/SIMULINK for switching
losses and THD. Furthermore, a PI controller is
used to control the MLI using the proposed PWM
technique. The results were verified experimentally
and FPGA processor is used for PWM. It was
noticed that the proposed modulation strategy
results in lower switching losses for a chosen THD
as compared to the conventional strategies.
Keywords:
Asymmetric Multilevel Inverter,
Variable frequency ISPWM, Switching Loss.
Dr.B.L.Mathur
Professor
Department of EEE ,
SSN College of Engineering,
Kalavakkam – 603 110,
Kanchipuram Dt,Tamilnadu, India
blmathur@ ssn.edu.in
I.INTRODUCTION
Multilevel inverters are mainly utilized to
synthesize a desired voltage wave shape from
several levels of dc voltages. Their main
advantaged are low harmonic distortion of the
generated output voltage, low electromagnetic
emissions, high efficiency capability to operate
at high voltages and modularity. Three
topologies have been reported for multilevel
inverters: Diode- clamped, flying capacitor and
cascaded H-bridge [1].The topology considered
for this work is the cascaded H-bridge inverter
which requires several independent dc sources.
Normally, each phase of a cascaded multilevel
inverter requires “n” dc sources for 2n+1 level.
For many applications, multiple dc sources are
required demanding long cables and this could
lead to voltage unbalance among the dc sources.
With an aim to reduce the number of dc sources
required for the cascaded multilevel inverter for
a motor drive, this paper focuses on asymmetric
cascade MLI that uses two unequal dc sources in
98810-2323 IJECS-IJENS @ International Journals of Engineering and Sciences IJENS
International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 10
each phase to generate a seven level equal step
multilevel output [2]. This structure is favourable
for high power applications since it provides
higher voltage at higher modulation frequencies
(where they are needed) with a low switching
(carrier) frequency. It means low switching loss
for the same total harmonic distortion (THD) .It
also improves the reliability by reducing the
number of dc sources.
For the cascaded multilevel inverter there are
several well known sinusoidal pulse width
modulation strategies [3].Compared to the
conventional triangular carrier based PWM, the
inverted rectified sine carrier PWM has a better
spectral quality and a higher fundamental output
voltage without any pulse dropping [4].
However, the fixed frequency carrier based
PWM affects the switch utilization in multilevel
inverters .In order to balance the switching duty
among the various levels in inverters, a variable
frequency carrier based PWM has been
suggested [5].
This paper however, presents a novel
variable frequency inverted rectified sine
modulation technique (VFISPWM) for a seven –
level inverter. This novel method combines the
advantage of inverted sine and multi frequency
carrier signals. The VFISPWM provides an
enhanced fundamental voltage, lower total
harmonic distortion (THD) and minimizes the
switch utilization among the various levels in
inverters. In this method the control signals have
been generated by comparing sinusoidal
reference signal with a high frequency inverted
sine carrier. The carrier frequencies are so
selected that the number of switching in each
band are equal. The proposed modulation
technique maximizes the output voltage and
gives a low THD of 5.92%. A PID controller is
employed to enhance the performance of the
asymmetric MLI using the proposed modulation
strategy. A comparative evaluation between the
VFISPWM and the conventional modulation is
also presented in terms of output voltage quality,
power circuitry complexity, and total harmonic
distortion (THD), weighted total harmonic
distortion (WTHD) and implementation cost.
56
Both the MLI circuit topology and its new
control scheme are described in detail and their
performance is verified based on simulation and
experimental results.
II. ASYMMETRIC CASCADED MULTILEVEL
INVERTER
The seven - level cascaded multilevel
inverter consists of two H-Bridges. The first HBridge H1 consists of a separate DC source Vdc,
whereas the second H-Bridge H2 consists of a
dc source Vdc/2 as shown in Fig.1. Let the output
of H-Bridge-1 be denoted as v1(t) and the output
of H-Bridge-2 be denoted as v2(t). Hence the
total
output
voltage
is
given
by
v(t)=v1(t)+v2(t).By alternately opening and
closing the switches S1,S4 and S2,S3 of H-Bridge1 appropriately, output of H1 v1(t) can be made
equal to +Vdc, 0 or -Vdc. Similarly the output
voltage of H-Bridge-2 v2(t) can be made equal to
–Vdc/2, 0 or +Vdc/2 by opening and closing the
switches of H2 [14].Hence v(t) takes values 3/2Vdc, -Vdc, -1/2Vdc, 0, +1/2Vdc, +Vdc, +3/2Vdc
as shown in the Fig.2.
Fig.1 Asymmetric Cascaded Multilevel Inverter
•
•
•
•
The advantages of the topology are:
Reduced number of dc sources.
High speed capability
Low switching loss
High conversion efficiency.
.
98810-2323 IJECS-IJENS @ International Journals of Engineering and Sciences IJENS
International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 10
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T H D ( % ) & W e ig h te d S w itc h in g L o ss
(% )
8
A m p lit u d e ( V )
6
THD(%)
4
Sw. Loss (%)
2
3950Hz
0
0
The proposed control strategy replaces the
conventional fixed frequency carrier waveform
[6] by variable frequency inverted sine wave.
The inverted sine PWM has a better spectral
quality and a higher fundamental voltage
compared to the triangular based PWM.But the
main drawback is the marginal boost in the
magnitude of lower order harmonics and
unbalanced switch utilization. This is overcome
by employing variable frequency inverted sine
carrier signals. In order to balance the number of
active switching among the levels is to vary the
carrier frequency based on the slope of the
modulating wave in each band. The frequency
ratio for each band should be set properly for
balancing the switching action for all levels. The
reference carrier frequency was chosen as
3950Hz as switching losses and THD both are
low as shown in Fig.3.
6
8 10
Fig.3.Reference Switching Frequency vs. THD
(%) & switching Loss (mJ / Cycle) of the
Conventional PWM Technique.
With the carrier reference frequency of 3950Hz
applied to the band-1,the new frequencies for
bands 2 and 3 are assigned proportional to their
respective slopes.
C
B
A m p lit u d e ( V )
III.PROPOSED VARIABLE FREQUENCY
INVERTED SINE PWM TECHNIQUE
(VFISPWM)
4
Switching Frequency (KHz)
Time (ms)
Fig.2. Output Voltage Waveform of Asymmetric
Cascaded Seven Level Inverter.
2
A
O
θ1 θ2 θ3
θ4
180
Angle- θ (Degrees)
Fig.4.Reference modulating wave – Three bands for
different carrier frequency shown.
98810-2323 IJECS-IJENS @ International Journals of Engineering and Sciences IJENS
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International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 10
58
In Fig.4. the modulating wave is defined as
(1)
θ1 = Sin 1 0 = 0 radians
θ 2 = Sin −1 (1 3) = 0.339 radians
θ 3 = Sin −1 (2 3) = 0.728 radians
(2)
(3)
(4)
θ 4 = Sin −1 (1) =1.5707 radians
(5)
Slope of C1 = 1.00
(6)
Slope of C2 = 0.8716
(7)
Slope of C3 = 0.404
(8)
Frequency of C1 = 3950Hz
(9)
Frequency of C2 = 3443Hz
(10)
Frequency of C3 =1596Hz
(11)
Using the slope values of the carrier band, the
new frequencies are calculated and the carrier
waveforms are shown in the Fig.5. Also, the new
frequency values are verified with the dwell time
calculation of the reference waveform [5].The
number of switching actions (8) is balanced for
all the switches in the proposed PWM technique
as shown in table I :
Table I: Switching Actions for the PWM
Techniques
Parameter
Proposed
VFISPWM
Conventional
PWM
Nsw
THD
48
5. 92 %
72
7. 98%
A m p lit u d e ( V )
The calculation of the slope values for the three
bands is shown below:
C1 = 1596Hz
C2 = 3443 Hz
C3 = 3950 Hz
Time (ms)
Fig.5.Carrier and Reference Waveforms for the
Proposed Variable Frequency ISPWM.
A m p lit u d e ( V )
V (t) = Sinθ
Time (s)
Fig.6.Generation of gating Pulses for
VFISPWM using MATLAB.
98810-2323 IJECS-IJENS @ International Journals of Engineering and Sciences IJENS
International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 10
The parameters chosen for simulation using the
proposed PWM technique is shown below:
S.
No
1
2
3
Parameters
Main DC source voltage
(Vdc)
Modulation Index (ma)
New Carrier Frequency
Values
200V
Frequency modulation
Ratio (mf )
Filter (Resonant Arm
Type)
1.00
3950Hz,3443Hz
& 1596Hz.
mf3 = 79, mf2
=69, mf1 =32.
LC ( L = 2.2mH
C = 220uF)
6
Rated Output Frequency
50Hz
7
Reference Voltage
200V
4
5
59
conventional method is the output voltage
quality, THD, WTHD and switching loss [9].
Fig.8.shows the block diagram for the pulse
generation using VFISPWM.Fig.7.and Figs.9. &
10 show the simulated output voltage waveforms
and harmonic spectrums of the conventional
ISPWM and the proposed MFISPWM for ma =
1.00 and Vdc = 200V. As it can be seen, the
proposed ISPWM technique has always lower
THD and the phase voltage waveform shows that
the top and bottom levels has less number of
switching
compared to
the conventional
ISPWM.
a. PI Control
A PI Controller (proportional-integral controller)
is a feedback controller which drives the plant to
be controlled with a weighted sum of the error
(difference between the output and desired setpoint) and the integral of that value. The function
of PI is to regulate the multilevel inverter so that
it stays close to the nominal operating point in
the presence of disturbances and noise. PI
controller settings kp and ki are designed in this
work using Zeigler- Nichols tuning technique.
The designed values of kp and ki are 0.0135 and
18.5 respectively.
Fig.7. Simulated Phase Voltage Waveforms for the
proposed VFISPWM.
IV.SIMULATION RESULTS
The cascaded seven-level inverter is simulated
using MATLAB/SIMULINK and switching
signals are generated using S-function block by
employing the proposed modulation strategy.
The simulation is carried out for different
modulation index and carrier frequency values
[8]. The performance parameters considered for
comparing the proposed PWM with the
Fig.8. Block diagram of gating pattern (VFISPWM).
98810-2323 IJECS-IJENS @ International Journals of Engineering and Sciences IJENS
International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 10
Fig.10. presents THD vs. ma graph. These results
show that the VFISPWM method gives harmonic
reduction for individual harmonic. The main
advantage of the proposed technique is that the
number of switching per cycle is same for all the
levels. For balancing the switching actions, the
choice of the carrier frequency is very important.
Hence, the VFISPWM scheme is more
favourable than the conventional ISPWM
technique for use in asymmetric multilevel
inverter[9].
THD vs ma
11
T H D (% )
9
M a g n itu d e (% ) o f F u n d a m e n ta l C o m p o n e n t
HFISPWM
8
7
6
5
4
0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
4.5
Modulation Index(ma)
Fundamental
Component
(143.5V)
4
3.5
Fig.11. Variation of THD with modulation index
for Fixed frequency (FF) and Variable
frequency (VF) ISPWM.
3
2.5
2
1.5
1
0.5
0
10
20
30
40
50
60
70
80
Harmonic order
Fig.9. Output Phase Voltage Spectrum for the
Proposed VFISPWM.
5
Fig.12. & 13. shows the simulated closed loop
dynamic responses of load voltage and load
current of PI controlled multilevel inverter when
the load changes from full load (10ohms) to no
load (10k) at t = 0.06secs. Fig.14. shows the
dynamic response of load current when the load
changes from no load (10k) to full load (10
ohms) suddenly at t = 0.04seconds with P
controller[10]. The filter type employed for MLI
is resonant arm type filter and the filtered output
voltage and current waveform is shown below:
200
4.5
Fundamental
Component
(141.2 V)
4
150
3.5
100
3
A m p litu d e ( V )
M a g n itu d e (% ) o f Fu n d a m e n ta l C o m p o n e n t
FFISPWM
10
5
0
60
50
2.5
2
0
-50
1.5
-100
1
-150
0.5
0
-200
0
10
20
30
40
50
60
70
Harmonic Order
Fig.10. Output Phase Voltage Spectrum for the
Conventional ISPWM.
80
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
Time (sec)
0.09
0.1
Fig.12.Transient response of MLI output
phase voltage with PI control.
98810-2323 IJECS-IJENS @ International Journals of Engineering and Sciences IJENS
International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 10
0.04
data1
0.03
A m p litu d e ( V )
0.02
0.01
61
The performance parameters considered for
evaluating the proposed modulation strategy are:
spectral quality of the output voltage, THD,
WTHD and switching loss [11, 13 -16] which is
shown in Table II.
0
-0.01
-0.02
-0.03
-0.04
0
0.01
0.02
0.03
0.04
0.05
Time (sec)
0.06
0.07
0.08
0.09
0.
Fig.13.Transient response of MLI output
current with PI control.
15
data1
S Parameters
.
N
o
1 Spectral quality
of the output
voltage
2
A m p litu d e (V )
Lower
Order
harmonics
(3,5, 7 ) are
higher
Lower Order
harmonics
(3,5,7 ) are
reduced.
7.98
5.42
0.104
3.29
0.076
2.06mJ
(Calculated
New
Frequencies
1596Hz,344
3Hz and
3950Hz)
1.62
3.69
1.70
3
0
4
-5
-10
0
Proposed
MFISPWM
THD (%)
10
5
Convention
al ISPWM
0.01
0.02
0.03
0.04
0.05
Time(Sec)
0.06
0.07
0.08
0.09
WTHD (%)
Switching
Loss(mJ /Cycle)
6.38mJ
(3950Hz)
0.1
Fig.14.Transient response of MLI output
current with PI control.
The steady state response of the MLI is shown
below:
5
THD(%)
(PI CONTROL)
Transient state –
R = 10KΩ to
10Ω
A m p lit u d e (V )
6
THD(%)
(PI CONTROL)
Transient state
R = 10Ω to
10KΩ
Time (ms)
Fig.15.Steady State response of MLI output
Phase Voltage.
It is obvious that VFISPWM technique shows a
better performance for the seven-level inverter.
The THD of the VFISPWM is shown with PI
control which minimizes the amount of
harmonics.
98810-2323 IJECS-IJENS @ International Journals of Engineering and Sciences IJENS
International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 10
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V.EXPERIMENTAL RESULTS
A seven-level cascaded inverter has been built
using smart power module (SPM - 600V, 23A)
IGBTs. One dc source (100V) was used for the
single – phase hybrid cascaded MLI and the
other source (50V) to generate seven levels. The
inverter was first controlled using fixed
frequency ISPWM with the following
parameters: ma = 1.00 and mf = 79. FPGA
SPARTAN processor is used to implement the
gating pattern and PI control. The inverters
output line- neutral voltage waveforms for all the
three phases are shown in Fig.16.
50.0V / div
50.0 v / div
Fig.17. Line – neutral voltage for
Hybrid MLI with VFISPWM.
50.0V / div
Fig. 18. Line –Line voltage for Hybrid MLI with
VFISPWM. (mf3 = 32, mf2 = 69, mf1 =79).
Fig.16. Line – neutral voltage for Hybrid MLI
with FFISPWM.
The prototype inverter (refer Fig.1.) was tested
using the proposed VFISPWM with different
carrier frequencies as discussed in section-IV of
this paper. Specifically, the top and bottom
bands had a frequency ratio of 36 while the
centre and intermediate bands had a frequency
index of 79 and 69. Fig.17. and Fig.18. shows
the inverter’s output line- neutral and line-line
voltage waveforms using the proposed control
method. This control method balances the
switching actions and gives a lower value of
THD compared to the conventional one.
The type of filter employed for the seven –
level inverter is the resonant arm filter and the
ouput of the controlled phase voltage of the
multilevel inverter is shown below:
Fig.19.Controlled output phase voltage of the MLI
using PI.
98810-2323 IJECS-IJENS @ International Journals of Engineering and Sciences IJENS
International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 10
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VI.CONCLUSION
Asymmetric cascaded multilevel inverter using
two unequal dc sources for each phase requires
minimum number of switching devices. An
inverted sine wave carrier frequency modulation
strategy gives maximum fundamental voltage for
a given THD. A variable frequency carrier
modulation strategy results in reduced switching
losses. Advantages of all the above three
methods have been exploited in the proposed
technique. The PI controller is tested for
regulating output voltage and minimizing
harmonics of the chosen seven level inverter.
The proposed system has lower THD and lower
switching loss as compared to that of
conventional multilevel inverter.
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98810-2323 IJECS-IJENS @ International Journals of Engineering and Sciences IJENS
International Journal of Electrical & Computer Sciences IJECS Vol: 9 No: 10
BIOGRAPHY
Mrs. R.Seyezhai obtained her
her M.E in Power Electronics &
Drives from Shanmugha College
of Engineering, Thanjavur in
1998. She has been working in
the teaching field for about 12
Years. She has published 50
papers in the area of Power
Electronics & Drives.
Dr.B.L.Mathur obtained his
M.Tech in Power Systems from
IIT, Bombay in 1964.He
completed his Ph.D. in 1979
from IISc, Bangalore. His Ph.D.
thesis was adjudged as the best
for application to industries in
the year 1979 and won gold
medal. He has been working in
the teaching field for about 44
Years. He has published 30
papers
in
National
and
International journals and 75 in
National
and
International
conferences.
98810-2323 IJECS-IJENS @ International Journals of Engineering and Sciences IJENS
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