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Chapter 7

JFET Biasing Circuits
◦ Fixed-Bias
◦ Self-Bias
◦ Voltage-Divider Bias

D-Type MOSFET Biasing Circuits
◦ Self-Bias
◦ Voltage-Divider Bias

E-Type MOSFET Biasing Circuits
◦ Feedback Configuration
◦ Voltage-Divider Bias
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
Non-linear relation between ID and VGS
◦ Complicates calculations

Graphical approach may be used
◦ Accurate enough for application
◦ Graph paper generator link on class website
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For all FETs:
For JFETS and D-Type MOSFETs:
For E-Type MOSFETs:
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
DC analysis
◦
◦
◦
◦

RG eliminated when IG = 0A
VS = 0V
VD = VDS
VG = VGS
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DC analysis
◦ VGS = -VGG
 WATCH ANNOTATION
◦
=
1−
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
Find
VGSQ
IDQ
VDS
VD
VG
◦ VS
◦
◦
◦
◦
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
VGSQ, IDQ
◦
◦
◦
◦
Choose an ID
Plot VGS = -IDRS
Plot Shockley equation
Intersection in Q-point
1=
2 = (− )(
1−
)
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
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VDS=VDD-ID(RS+RD)
VS=IDRS
VD= VDS+VS= VDD-VRD
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
Find
◦
◦
◦
◦
◦
◦

VGSQ
IDQ
VDS
VS
VG
VD
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VGS line can have
any slope
◦ Based on RS

Line will only pass
through origin if
VG = 0V
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IG = 0 A
ID responds to changes
in VGS.
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VG is equal to the voltage across
divider resistor R2:
Using Kirchhoff’s Law:

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Find intercepts
◦ VGS = Vg – IDRS
◦ VGS = 0 and ID = 0

Y=MX+B
◦ Find M using (y2-y1)/(x2-x1)
◦ Find B using y=MX+B
 Use one set of X and Y
◦ Plug back into Y=MX+B
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Plot the line that is defined
by these two points:
VGS = VG, ID = 0 A
VGS = 0 V, ID = VG / RS
Plot the transfer curve by
plotting IDSS, VP and the
calculated values of ID
To use a graphing calculator, use the values for the x and y
intersect for linear regression. Plot the regression equation and
find the intersect with the transfer curve.
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Using the value of ID at the Q-point, solve for the other
values in the voltage-divider bias circuit:
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
Find
◦
◦
◦
◦
◦
IDQ and VGSQ
VD
VS
VDS
VDG
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Circuit uses a voltage source on drain and
source
 Normally VSS = 0V, shown as ground
 Ensure Vss is considered when finding values
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=

=

(1 −
)
−
◦ Vss is the value of the source
◦ If source itself is not shown, potential at that point
is shown. USE THE SOURCE VALUE
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Find
◦
◦
◦
◦
◦
VGSQ
IDQ
VS
VD
VDS
IDSS = 6 mA
Vp = -4
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
Example – Common Source, Grounded Gate
◦
◦
◦
◦
◦
VGS = 0V
IDQ = IDSS
VDS = VDD – IDRD
VD = VDS
VS = 0V
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Depletion-type MOSFET
bias circuits are similar
to those used to bias
JFETs. The only
difference is that D-type
MOSFETs can operate
with positive values of
VGS and with ID values
that exceed IDSS.
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Plot the line that is defined by these
two points:
VGS = VG, ID = 0 A
ID = VG /RS, VGS = 0 V
Plot the transfer curve using IDSS, VP
and calculated values of ID.
The Q-point is located where the line
intersects the transfer curve.
To use a graphing calculator, use the values for the x and y
intersect for linear regression. Plot the regression equation
and find the intersect with the transfer curve.
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Plot the line that is defined by these two
points:
VGS = VG, ID = 0 A
ID = VG/RS, VGS = 0 V
Plot the transfer curve using IDSS, VP and
calculated values of ID.
The Q-point is located where the line
intersects the transfer curve.
To use a graphing calculator, use the values for the x and y
intersect for linear regression. Plot the regression equation and
find the intersect with the transfer curve.
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Find VGSQ and IDQ
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 ID

= 0 when VGS < VGS(TH)
When VGS>VGS(TH)
◦
= (
−
)
◦ ID(ON) and VGS(ON) given on
spec sheet
◦
=(
 Labeled in
(
)
)
A/V2
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Plot the line that is defined
by these two points:
VGS = VDD, ID = 0 A
ID = VDD / RD , VGS = 0 V
Using these values from the
spec sheet, plot the transfer
curve:
VGSTh , ID = 0 A
VGS(on), ID(on)
y1= ID(x-VGSth)2 (ID is in mA)
y2= Linear Regression of bias line
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Only thing that changes is the load line
◦ Y- intercept =
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
Find IDQ and VDSQ
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Plot the line and the transfer
curve to find the Q-point using
these equations:
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
Plot the bias line:
◦ VGS = VG , ID = 0 A
◦ ID = VG / RS , VGS = 0 V

Plot the transfer curve:
◦ VGS(Th), ID = 0 A
◦ VGS(on) , ID(on)

The point where the line and the transfer
curve intersect is the Q-point.
To use a graphing calculator, use the values for the x and y
intersect for linear regression. Plot the regression equation
and find the intersect with the transfer curve.
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For p-channel FETs the same calculations and graphs
are used, except that the voltage polarities and current
directions are reversed.
The graphs are mirror images of the n-channel graphs.
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
Question 2
◦ Vgg = 3 V
◦ Drawn correctly, but
confusing

Question 8
◦ Change VSS to -3

Question 16
◦ Marking on schematic is
wrong
-3V
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