UNIVERSITY OF CINCINNATI
September 23
03
_____________
, 20 _____
Pradeep A. Balaraman
I,______________________________________________,
hereby submit this as part of the requirements for the
degree of:
Master of Science
________________________________________________
in:
Electrical Engineering
________________________________________________
It is entitled:
Design, Simulation and Modeling of InP/GaAsSb/InP
________________________________________________
Double Heterojunction Bipolar Transistors
________________________________________________
________________________________________________
________________________________________________
Approved by:
Dr. Kenneth Roenker
________________________
Dr. Marc Cahay
________________________
Dr. Punit Boolchand
________________________
________________________
________________________
DESIGN, SIMULATION AND MODELING OF
InP/GaAsSb/InP DOUBLE HETEROJUNCTION
BIPOLAR TRANSISTORS
A Thesis Submitted to the
Division of Research and Advanced Studies
of the University of Cincinnati
in partial fulfillment of the
requirement for the degree of
MASTER OF SCIENCE
in the Department of Electrical and Computer Engineering and
Computer Science of the College of Engineering
September 2003
by
Pradeep A. Balaraman
B.E. in Electronics and Communications Engineering,
Tamilnadu College of Engineering, Bharathiyar University, Coimbatore,
India, April 2000.
Thesis Advisor and Committee Chair : Dr. Kenneth P. Roenker
Committee Members: Dr. Marc Cahay, Dr. Punit Boolchand
Abstract
Device modeling using a two dimensional, drift-diffusion approach utilizing a
commercial numerical device simulator has been used to investigate the operation and
performance of InP/GaAsSb heterojunction bipolar transistors (HBTs). GaAsSb lattice
matched to InP has an energy bandgap (0.72 eV) that is similar to that of InGaAs (0.75
eV) so that Sb-based HBTs have been proposed as a replacement for InGaAs-based
HBTs. In particular, the conduction band lineup is more favorable at the base-collector,
which makes the GaAsSb-based HBTs especially attractive for double heterojunction
bipolar transistors (DHBTs) where higher breakdown voltages are desired. In this work,
the results of device modeling will be compared initially with recent experimental reports
to validate the modeling approach. Then the design and operation of the devices will be
examined to investigate the factors controlling device performance in order to facilitate
improvements in device design. The degradation of device performance at high currents
due to the formation of a parasitic barrier in the collector region and the base push out
effects is examined. Finally, a device structure with improved high frequency
performance is presented.
Acknowledgements
I would like to sincerely thank my thesis advisor Dr. Roenker for his constant support and
guidance. I thank him in particular for his patience and brilliant ideas to help move the
research along when it got stuck many times. I thank Dr. Cahay and Dr. Boolchand for
their participation in my thesis defense.
I would like to thank my lab mates, Nitish and Donka, for helping me learn the
simulation software and Mohan, Aniket, Shivani, Dave, and Rama, for the their help and
support. Many thanks to my friends, Sathya, Prashanth, Mukesh, Priya, Chandy, Sheeda,
Vignesh, and the “Gang” at Tech office for making my stay at UC a pleasant and
memorable one. Special thanks to friends back home, Bhama, Gopal, Saravana, Senthil,
Subha, and Vinesh for their awesome and endearing company.
Finally, I would like to thank my family for their boundless love and support.
ii
Contents
Title Page
Abstract................................................................................................................................i
Acknowledgements.............................................................................................................ii
Contents..............................................................................................................................iii
List of Figures....................................................................................................................vii
List of Tables.....................................................................................................................xv
Chapter I Introduction
1.1 Introduction..................................................................................................1
1.2 Bipolar Junction Transistor..........................................................................2
1.3 Heterojunction Bipolar Transistors..............................................................6
.
1.4 Double Heterojunction Bipolar Transistors.................................................9
1.5 InP-Based Heterojunction Devices..........................................................10
1.6 InP/GaAsSb/InP Double Heterojunction Bipolar Transistors...................15
1.7 Advantages of InP/GaAsSb/InP DHBTs...................................................18
1.8 Motivation and Organization of the Thesis...............................................22
Reference:..........................................................................................................................23
Chapter II Simulation Software, Techniques and Material Properties
2.1 Introduction………………………………………………………….…28
2.2 Simulation Technique...…………………...……………….…………. 29
2.3 Device Physics and Models………………..…………….…………… 30
iii
2.3.1 Poisson’s Equation……..………………………………………... 30
2.3.2 Carrier Continuity Equations……………………………………..31
2.3.3 Transport Equations………..…………………………………... 32
2.4 Material Parameter Models………………………….………………... .33
2.4.1 Mobility Modeling……………………………………………...33
2.4.1.1 The Caughey-Thomas Model……….………………………... 34
2.4.1.2 Parallel Electric Field Dependent Mobility…….…………….35
2.4.2 Carrier Generation-Recombination Models…………………....35
2.5 Material Properties of GaAsSb………………………..………………..37
2.5.1 Crystal Structure and Lattice Matching…….………………….... 38
2.5.2 GaAsSb Energy Band Gap……………...…………..………….....40
2.5.3 Bandgap Offsets for InP/GaAsSb Heterojunctions……………....45
2.5.4 Effective Masses and Density of States………………….…….....49
2.5.5 Mobility………………………………………………….…….....53
2.5.5.1 Hole Mobility………………………………………………...... 53
2.5.6 Electron Mobility……………………………………………....... 57
2.5.7 Carrier Lifetimes……………………………………………........ 58
2.6 Material Properties of InP and InGaAs…………………...…………....60
2.6.1 Indium Phosphide…………………………………………….......60
2.6.1.1 Heavy Doping Effects in InP…………………….…………......61
2.6.2 InGaAs…………………………………………………………....63
2.7 Conclusion……………………………………………………………...66
Reference.....................................................................................................……..…....…67
iv
Chapter III Simulation of InP/GaAsSb/InP HBTs and basic results
3.1 Introduction………………………………………..……………….......70
3.2 Software Description…………………………....…..……………........70
3.2.1 Definition of HBT structure and Mesh Specification.……….......72
3.2.2 Physics-Based Models…….…………………………………......73
3.2.2.1 Hot-Electron Model………………………………………........74
3.2.3 Input Bias Setup and Output Result Extraction…..………….......76
3.3 Structure and Modeling of InP/GaAsSb/InP HBTs…………….….......77
3.4 High Current Effects………………………………………….…..........95
3.5 Current Gain Collapse at High Frequency………………………..........98
3.6 Conclusion………………………………………………………........105
Reference:………………………………………………………………………………106
Chapter IV Optimization of InP/GaAsSb/InP HBTs
4.1 HBT Performance Parameters..............................................................110
4.1.1 AC Current Gain..........................................................................110
4.1.2 Current Gain Cutoff Frequency (fT ).............................................111
4.1.3 Unilateral Power Gain and Maximum Frequency of Operation..114
4.2 Optimization of InP/GaAsSb/InP HBTs...............................................115
4.2.1 Optimization of the Base Layer...................................................116
4.2.2 Optimization of the Emitter Layer...............................................123
4.2.3 Collector Layer Optimization......................................................128
4.3 Optimized Structure..............................................................................134
4.4 Conclusions...........................................................................................143
v
Reference…………….....................................................................................................143
Chapter V Conclusions and Future Work
5.1 Conclusion............................................................................................144
5.2 Future Work..........................................................................................146
Reference:………………………………………………………………………………147
vi
List of Figures
Figure 1.1 Band diagrams of an npn homojunction bipolar transistor under (a) thermal
equilibrium (b) and in the normal, forward-active mode .................................4
Figure 1.2 Band diagrams of an Npn HBT under (a) thermal equilibrium and (b) in the
normal forward-active mode .............................................................................7
Figure 1.3 Comparison of material properties of InP, GaAs and Silicon .........................12
Figure 1.4 Conduction band profiles for a few design options for InP-based HBTs. [6]..14
Figure 1.5 Band lineup of InP/GaAsSb heterojunction ....................................................16
Figure 1.6 Comparison of reported fT and fmax values for InP HEMTs, GaInAs DHBTs
and InP DHBTs................................................................................................17
Figure 1.7 fT values vs. BVceo for InP collector DHBTs from literature (€).....................20
Figure 1.8 Normalized cut-off frequency dependency on collector current density for
various DHBT and SHBT technologies ..........................................................21
Figure 2.1 GaAsSb crystal structure where Sb is incorporated in some of the As sites....39
Figure 2.2 Lattice parameter versus compositio n plot for In1-x Gax Asy Sb1-y and
compositions (dotted line) lattice matched to InP...........................................40
Figure 2.3 Energy Band structure of the binaries GaAs (a) and GaSb (b)........................41
Figure 2.4 Plot of energy band gap versus composition for the quaternary In1-x Gax Asy Sb1-y
for the material lattice matched to InP (dotted line).......................................42
Figure 2.5 Variation of GaAs1-x Sbx bandgap with Sb content • Klem et al et al. [6] and
♦Merkel et al...................................................................................................43
Figure 2.6 Energy separation between L- valley of conduction band and top of the
valence band....................................................................................................44
vii
Figure 2.7 PL spectra for GaAsSb for various Sb concentrations...................…..........................45
Figure 2.8 Staggered Band line-up at InP/GaAsSb Heterojunctions.................................46
Figure 2.9 Band offsets of GaAsSb on InP........................................................................48
Figure 2.10 Calculated Band offsets in GaAsSb on InP based on results of Merkel et al
[6] (•) Ec b and (€) E vb.....................................................................................49
Figure 2.11 Empirical variation of hole effective mass with Sb content [9] (♦) Heavy
hole mass (€) Light hole
mass.........................................................................50
Figure 2.12 Variation of the electron effective mass with Sb Content .............................51
Figure 2.13 Temperature dependence of intrinsic carrier concentration: 1) x = 0(GaAs),
2) x = 0.3, 3) x = 0.8, 4) x = 1 (GaSb)...........................................................53
Figure 2.14 Hole Hall Mobility as a function of Sb in GaAsSb........................................54
Figure 2.15 Hall Mobility for holes as a function of carrier concentration for various Sb
compositions. Where different symbols correspond to the indicated Sb
composition ranges..........................................................................................55
Figure 2.16 Hole mobility variation with doping: experimental values (+) [14] and
calculated Caughe y-Thomson values (•)......................................................56
Figure 2.17 Electron mobility variation with doping: experimental values (+) [13, 16] and
calculated Caughey-Thomson values (•)......................................................58
Figure 2.18 Calculated carrier lifetime variation with doping (€) Hole lifetime, (•)
Electron life time..........................................................................................60
Figure 2.19 Photoluminescence spectra of InP..................................................................61
Figure 2.20 Bandgap narrowing in InP due to heavy doping............................................63
viii
Figure 2.21 Electron ( ) and hole (O) minority carrier lifetime models as a function of
doping level......................................................................................................64
Figure 3.1 An InP/GaAsSb/InP DHBT structure shown with mesh grid..........................73
Figure 3.2 The Staggered Bandgap line-up of InP/GaAsSb/InP HBTs.............................75
Figure 3.3 Schematic of the simulated InP/GaAsSb/InP DHBT structure........................79
Figure 3.4 Simulated structure of InP/GaAsSb/InP HBT..................................................80
Figure 3.5 Simulated conduction and valence band profiles for InP/GaAsSb/InP DHBT
with 200A0 base width and no applied biases..................................................83
Figure 3.6(a) Gummel-Poon plot of the InP/GaAsSb DHBT structure from Dvorak et al
for 400 A0 base width (C: 4 x 10-19 cm-3 ) and 1.5x24 µm2 ..............................85
Figure 3.6(b) Simulated Gummel-Poon characteristics of InP/GaAsSb/InP structure for
the device structure described in Figures 3.4 and 3.3 for Vcb=2.0 V.........86
Figure 3.7(a) Typical common-emitter characteristics for a small area 0.4x11µm2 emitter
device with a 250 Å base and a 2000 Å InP collector.....................................87
Figure 3.7(b) Simulated common-emitter characteristics for a 0.5x1 µm emitter device
(Fig 3.3) with a 200 A0 base and 2000 A0 InP collector...........................87
Figure 3.8(a) Frequency response of fabricated structure reported by Bolognesi et al. with
a 200 A0 thick base with a doping of 8x1019 /cm3 ..........................................89
Figure 3.8(b) Frequency response of the simulated InP/GaAsSb/InP HBTs (•) current
gain, (X) unilateral power gain.......................................................................89
Figure 3.9(a) Evolution of fT with JC for the InP/GaAsSb DHBT with a base width of
200A0 and collector width of 2000 A0 for a VCE=0.4V to 1.8V as reported by
Bolognesi et al.................................................................................................91
ix
Figure 3.9(b) Evolution of fT with J C for collector-emitter bias VCE = 0.4 to 1.8V for
simulated structure...........................................................................................91
Figure 3.9(c) Peak fT variation with VCE for simulated (•) and fabricated (s)
InP/GaAsSb/InP DHBTs.................................................................................92
Figure 3.10(a) fmax and fT dependence on JC for a 250 A0 base and 2000 A0 InP/GaAsSb
DHBT for various VCE biases..........................................................................94
Figure 3.10(b) Evolution of fmax vs collector current density JC for 200A0 bases and
2000A0 collector for the simulated InP/GaAsSb DHBT for various VCE........94
Figure 3.10(c) Reported fmax variation with collector-emitter bias VCE (•) for a 4x11 µm2
emitter, 250 A0 base and 2000 A0 Collector [9] and simulated peak fmax
values (? ) ....................................................................................................95
Figure 3.11 High frequency and Cbe behavior of a 200 A0 base and 2000 A0
InP/GaAsSb/InP device...................................................................................98
Figure 3.12 Variation of current gain with collector current density for VCE=1.8 V at 2
GHz...............................................................................................................99
Figure 3.13 Variation of maximum unilateral power gain with collector current density
for VCE=1.8 V at 2 GHz................................................................................99
Figure 3.14 Collapse of electric field and subsequent parasitic barrier formation in the
collector of InP/GaAsSb/InP DHBTs with Vbe varied from 0.6 V to 1.0 V and
VCE = 1.8V.....................................................................................................101
Figure 3.15 Critical current density for the onset of high current induced device
degradation versus based-collector voltage for the simulated and calculated
device behavior..............................................................................................102
x
Figure 3.16(a) Hole concentration for low and high current operation of a 200 A0 base
and 2000 A0 collector simulated InP/GaAsSb/InP DHBT, ‘B’ and ‘C’ indicate
the base-collector regions for VCE = 1.8V and for VBE from 0.6V to 1.1V...104
Figure 3.17 Conduction band barrier height versus collector current density for simulated
InP/GaAsSb structure given in Figure 3.3 for VCE =1.8 V............................104
Figure 4.1 Parameters affecting the high frequency performance of the HBT................112
Figure 4.2(a) fT Vs base-emitter voltage as a functio n of the base width for VCE=1.8V for
a fixed base doping of 4x1019 cm-3 ........................................................114
Figure 4.2(b) ft vs Collector Current density as a function of base width for VCE=1.8V
and VBE from 0.6V to 1.07V for a fixed base doping of 4x1019 cm-3 ......114
Figure 4.2(c) fmax vs base-emitter voltage for various base widths for VCE=1.8V and VBE
from 0.6V to 1.07 Volts for a fixed base doping of 8x1019 cm-3 ...............119
Figure 4.2(d) fmax vs collector current density for various base widths for VCE=1.8V and
VBE from 0.6V to 1.07 Volts for a fixed base doping of 8x1019 cm-3 .........119
Figure 4.2(e) Variation of peak fT and fmax with base width for a base doping of 8x1019
cm-3 , (+) Peak fT fmax from results by Bolognesi et al. [2] for similar device
structure.......................................................................................................120
Figure 4.3(a) fT versus emitter-base voltage for various doping levels for VCE=1.8V for a
fixed base width of 20nm............................................................................121
Figure 4.3(b) fmax versus emitter-base voltage for various doping levels for VCE=1.8V for
a fixed base width of 20nm............................................................................122
xi
Figure 4.3(c) Variation of peak fT and fmax with base doping for a fixed base width of
20nm, (+) indicates peak fT and fmax results from Bolognesi et al. [2] for
similar device structure..................................................................................122
Figure 4.4(a) Effect of emitter width variation on fT for VCE=1.8V for a fixed emitter
doping of 3x1017 cm-3 ....................................................................................124
Figure 4.4(b) Effect of emitter width variation on fmax for VCE=1.8V for a fixed emitter
doping of 3x1017 cm-3 ....................................................................................124
Figure 4.4(c) Variation of peak fT and fmax with emitter width for a fixed emitter doping
of 3x1017 /cm3 , (+) indicates peak fT and fmax results by Bolognesi et al. [2] for
similar device structure..................................................................................125
Figure 4.5(a) fT versus base-emitter voltage for various doping levels for VCE=1.8V for a
fixed emitter thickness of 700 A0 ...................................................................126
Figure 4.5(b) fmax versus base-emitter voltage for various doping levels for VCE=1.8V for
a fixed emitter length of 700 A0 ..................................................................127
Figure 4.5(c) Variation of peak fT and fmax with emitter doping for a fixed emitter width
of 700 A0 ........................................................................................................127
Figure 4.6 Calculated collector depletion thickness, fT and fmax, as a function of VCE...129
Figure 4.7(a) fT vs base-emitter voltage for several collector widths for VCE=1.8V for a
fixed collector doping of 3x1016 /cm3 .........................................................130
Figure 4.7(b) fmax vs base-emitter voltage for several collector widths for VCE=1.8V for a
fixed collector doping of 3x1016 /cm3 .........................................................130
Figure 4.7(c) Variation of peak fT and fmax with collector width for a fixed collector
doping of 3x1016 /cm3 .................................................................................131
xii
Figure 4.8(a) fT Vs Base emitter Voltage for various collector doping for a fixed collector
width of 2000A0 ..........................................................................................133
Figure 4.8(b) fmax Vs Base emitter voltage for various collector doping for a fixed
collector width of 2000A0 ...........................................................................133
Figure 4.8(c) Variation of peak fT and fmax with collector doping for a fixed collector
width of 2000A0 ............................................................................................134
Figure 4.9(a) Schematic of the Optimized InP/GaAsSb/InP HBT..................................135
Figure 4.9(b) Schematic of the InP/GaAsSb/InP HBT structure by Bolognesi et al.......135
Figure 4.10 Simulated Structure of Optimized InP/GaAsSb/InP HBT...........................136
Figure 4.11 Gummel-Poon simulations of optimized InP/GaAsSb/InP Structure..........136
Figure 4.12 Frequency response of the optimized InP/GaAsSb/InP HBT for VCE =
1.8V.............................................................................................................137
Figure 4.13 Frequency response of the optimized InP/GaAsSb/InP HBT for VCE =
1.8V.............................................................................................................138
Figure 4.14(a) Evolution of fT with JC for various VCE from 0.8 to 1.8 Volts.................140
Figure 4.14(b) Evolution of fmax with JC for various VCE from 0.8 to 1.8 Volts..............140
Figure 4.15 Maximum power and AC current Gain versus collector current density (l)
Current gain (n) Power gain for VCE = 1.8V...........................……............141
Figure 4.16(a) Peak fT variation with VCE for InP/GaAsSb/InP DHBT structure of
Bolognesi et al. [2] (g ), simulated fT for the same structure ( n) and peak fT
for the optimized device structure (o) given in Figure 4.9.........................142
xiii
Figure 4.16(b) Peak fmax variation with VCE for InP/GaAsSb/InP DHBT structure of
Bolognesi et al. [2] (g ), simulated fT for the same structure ( n) and peak fT
for the optimized device structure (o) given in Figure 4.9.........................142
xiv
List of Tables
Table 1.1 Evolution of InP/GaAsSb/InP DHBT device development...............................17
Table 2.1 Bandgap of GaAs0.51Sb0.49 44
Table 2.2 Effective Masses of Electrons and Holes for GaAs, GaSb and GaAsSb...........51
Table 2.3 Caughey-Thomas Parameters for Holes and Electrons.....................................58
Table 2.4 Electron and Hole Minority Carrier Lifetimes for GaAs, GaSb and Latticematched GaAsSb.................................................................................................59
Table 2.5 Minority Carrier Lifetime Model Parameters for InGaAs.................................64
Table 2.6 Caughey-Thomas Parameters for InP, InGaAs, GaAsSb..................................65
Table 2.7 Summary of Important Material Parameters for GaAs0.51 Sb0.49 InP
In0.53Ga0.47 As.....................................................................................................66
Table 3.1 Evolution of InP/GaAsSb/InP DHBT Device Development.............................78
Table 3.2 Summary of Important Material Parameters for GaAs0.51 Sb0.49 InP
In0.53Ga0.47 As..................................................................................................…....81
Table 4.1 Simulation results for Optimized InP/GaAsSb/InP structure..........................138
xv
Chapter I
1.1
Introduction
Silicon has been the dominant material of the electronics industry for the past five
decades and will continue to remain so in the foreseeable future. However, silicon-based
devices come under severe limitations like current gain degradation and lack of linearity
when they are extended to microwave frequencies. The silicon-based Bipolar Junction
Transistor commonly referred to as the BJT, can only be used in applications in the
frequency range up to a few GHz. At these freque ncies and above is where the excellent
high frequency performance characteristics of III-V based devices can be harnessed,
particularly in satellite, mobile and radar communications. With more of these
applications being adopted for consumer uses, the market for III-V based devices is
expected to continue to grow.
III-V-based npn bipolar transistors have achieved tremendous performance in terms
of the microwave frequencies of operation and higher current gains because of their
superior material properties, such as higher electron mobility, and unique bandgap
alignment when two different materials are used to form a heterojunction. Npn
Heterojunction Bipolar Transistors (HBTs) differ from the BJTs in the fact that the
emitter is replaced by a material with a larger bandgap than the base. This leads to a
lowering of the barrier for electron injection into the base, but an increased barrier for the
holes which prevents their back injection into the emitter, resulting in higher current
gains. As a result, the base can be made thinner and at the same doped higher than the
emitter to reduce the base resistance and further increase its high frequency performance.
The idea of the HBT is not new, but was actually conceived a long time ago by Shockley
1
and co-workers in 1948 [1, 2]. Historically, difficulties in growing high quality, relatively
defect free III-V materials have slowed the exploitation of this concept. However, with
recent advances in epitaxial growth technologies, such as Molecular Beam Epitaxy
(MBE) and Metal Organic Chemical Vapor Deposition (MOCVD), the full potential of
HBTs is now being realized.
While III-V based devices cannot hope to replace silicon in the sub-GHz range or in
terms of cost effectiveness, they have carved out niche markets above 10 GHz, where
higher speed and performance factors outweigh cost. Not only are III-V devices a
competition for silicon in these areas, but they are also useful in applications where it
would be impossible for silicon-based devices to compete, such as for very high
frequency (>100 GHz) applications. Recently, InP/GaAsSb/InP HBTs have demonstrated
state of the art performances, in fact one of the highest for any solid-state device with
cutoff and maximum oscillation frequencies of 300 GHz [3]. Numerical Computer
Assisted Design (CAD) simulation and modeling of such InP/GaAsSb/InP HBTs is the
focus of this thesis. In this chapter, we provide a brief introduction to HBTs and their
advantages over BJTs. We introduce the InP/GaAsSb material system, its advantages and
their applications in HBTs.
1.2 Bipolar Junction Transistors
It is important that we review the basic operation of the homojunction BJT before we
study the InP/GaAsSb/InP HBTs since understanding the operation of the BJT is essential
for discussing the performance of HBTs. The BJT consists of three main layers, namely
the emitter, the base and the collector all made of the same silicon material. The emitter
2
and the collector are doped of the same type, whereas the base layer sandwiched in
between is of the opposite type. The basic principle behind a BJT is that the current
flowing from the emitter to the collector can be controlled by small changes in the base
current [4]. For our current discussion here, we will assume an npn transistor, with the
emitter and the collector being of n-type and the base being p-type.
One of the dominant features of p-n junctions, i.e., the injection of minority carriers
across the junction under forward biasing, forms the basis for operation of the BJTs. In
the normal operating condition for npn transistors, the base-emitter junction is forward
biased at VBE (VBE>0) and the base-collector junction is reverse biased at VBC (VBC<0).
Under a forward bias, the minority carrier concentration in the base at the base-emitter
junction is amplified by the law of junction by a factor given by exp (qVBE/kT), where
VBE is the applied voltage to the base-emitter junction. For a transistor to operate
properly, the width of the base region WB should be should less than the diffusion length
Ln of the electrons [4, 5]. This is because the electrons injected into the base from the
emitter must diffuse across base to the collector without excessive recombination with the
majority carrier holes in the base. These minority carrier electrons when they reach the
base-collector junction are quickly swept across the collector by the high electric field in
the reverse-biased collector-base junction and constitute the collector current (see Figure
1.1).
3
Figure 1.1 Band dia grams of an npn homojunction bipolar transistor under (a) thermal
equilibrium (b) and in the normal, forward-active mode [4].
The band diagram of a BJT in the rmal equilibrium and normal operation are shown
in Figure 1.1. The dotted line in the figure shows the Fermi level in each region for the
transistor. We can see that in a normal BJT the emitter region is doped heavily and the
collector region is lightly doped. Under normal operation, two currents dominate the
transistor operation, the collector current that flows from the emitter to the collector and
the base current. This base current is normally due to the back injection of holes into the
emitter from the base. Solving the carrier continuity equations, the base current and the
collector current are given as follows [4, 5]
qAE DpE niE2
qV
exp( BE )
X E NE
kT
(1.1)
qAE DnB niB2
qV
IC =
exp( BE )
X B NB
kT
(1.2)
IB =
4
where AE is the emitter junction area, NE is the emitter doping level, XE is the emitter
thickness, DpE is the minority hole diffusion coefficient in the emitter, niE is the intrinsic
carrier concentration in the emitter, NB is the base doping level, XB is the base thickness,
DnB is the minority electron diffusion coefficient in the base and niB is the intrinsic carrier
concentration in the base.
A simple analysis of the above two expressions will reveal that in order for the
collector current to be greater than the base current, it is necessary that the emitter doping
level exceed the base doping level. In doing so, we have traded off an important transistor
design parameter. For keeping the base doping at a lower value means that the base
resistance will be high. This is can be compensated by widening the base, however, this
will in turn contribute significantly to base transit time of the electrons, thus lowering the
device’s maximum frequency of operation (fmax). Therefore, for a fixed base doping level,
the current gain of the BJT can be increased, initially, by increasing the emitter doping.
But, significant emitter bandgap narrowing occurs when emitter doping is around
NE~1018 /cm3 , causing the current gain to degrade. The very nature of the homojunction of
the BJT therefore gives us a mutually conflicting set of requirements, where the base
doping cannot be increased without sacrificing current gain. This limits the operation of
the BJTs to low frequency amp lifiers, filters and oscillators.
The performance of the HBT can be significantly better than that of the BJT, if we
dope the base high and at the same time comparatively reduce the emitter doping, which
is more feasible because of the wide band gap emitter in the HBT. This is where HBTs
have made tremendous progress in terms of frequency of operation in the range of 100’s
of Giga Hertz.
5
1.3 Heterojunction Bipolar Transistors
The idea for HBTs is not new, but actually as old as the bipolar transistor itself,
originally put forward by Shockley and co-workers along with his claim for the transistor
in 1948 [1, 2]. However, as Kroemer suggested in his now famous paper [5], the idea of
HBTs was ahead of its time waiting for the development of modern epitaxial growth
techniques for defect free growth of III-V compound semiconductor heterostructures.
Heterojunction Bipolar Transistors (HBTs), when appropriately biased, provide good
current amplification and are highly desirable for high-speed operation. In comparison
with conventional silicon Bipolar Junction Transistors (BJTs), HBTs exhibit higher unity
gain cutoff frequencies fT , lower base resistance, lower base-emitter capacitance and
higher Early Voltages [4]. One of the reasons HBTs ha ve these advantages over a simple
BJT is that the emitter injection efficiency no longer depends only on the relative doping
levels of the emitter and the base region. The presence of a base/emitter bandgap
difference adds a term that depends exponentially on the energy gap difference, which
dominates the emitter injection efficiency. For abrupt heterostructures, the current gain
has an exponential dependence on the valence band ∆Ev discontinuity for n-p-n devices
[4]. As a result, the doping of the base region can actually be increased above the emitter
layer doping and the base thickness reduced which results in the dramatic improvement
in the microwave performance (fT , fmax) of an HBT compared to a BJT.
Spectacular advances in material growth technologies have enabled precise control
of layer thickness, doping and the ability to change composition from one III-V
semiconductor to a different III-V semiconductor material system. Shown in Figure1.2 is
an abrupt emitter-base heterojunction in an Npn HBT [4]. Heterostructures utilize the
6
energy gap variations between two different semiconductors, such as the emitter and the
base in the HBT, in addition to the electric fields and forces acting on the electrons and
holes to control and distribute the flow of carriers. For the Npn HBT, electrons are
injected thermally into the base from the emitter, diffuse across the base and electric field
in the base-collector depletion regions sweep them into the collector at high speed. The
bandgap lineup of heterojunctions is such that the valence band discontinuity prevents
back injection of holes from the base into the emitter. This results in significant increase
in current gain without sacrificing the high frequency performance.
Figure 1.2 Band diagrams of an Npn HBT under (a) thermal equilibrium and (b) in the
normal forward-active mode [4].
Heterojunctions can be of two types, graded and abrupt. For abrupt heterojunctions,
two different semiconductors with different bandgaps are brought together and the
7
interface is abrupt, i.e. the composition changes abruptly. In graded heterojunctions, the
composition is gradually changed across the heterojunction and there is a suppression of
energy band spikes due the energy band edge discontinuity seen at the abrupt
heterojunction interfaces. However, we will discuss only abrupt junctions, as it directly
relates to this work. The alignment of the conduction and valence bands in Npn HBTs is
such that by limiting hole back injection into the emitter, the emitter injection efficiency
is close to the ideal value of unity, regardless of the doping levels of the emitter and the
base [5]. In most cases, the conduction band of the emitter lies above that of the base and
the current gain of the device is given by equation 1.3. [4] The valence band discontinuity
at the heterojunction is also important, as it controls the amount of back injection into the
emitter. The ratio of the electron to hole currents across the emitter-base heterojunction is
given approximately by [4]
In
N v
= βmax = E nb exp( ∆Eg / kT )
Ip
NB v pe
(1.3)
where ∆Eg is the difference in bandgap between the emitter and base, where NE is the
emitter doping, NB is the base doping and vnb and vpe are the thermal velocities of
electrons and holes in the base and emitter, respectively. This result assumes negligible
recombination in the base and ∆Ev = ∆Eg, so it gives the maximum possible current gain.
When ∆Ev ≠ ∆Eg then the emitter base energy bandgap difference increases the In /Ip ratio
by a factor of
exp( ∆Ev /kT) relative to that for BJTs and the valence band ∆Ev
discontinuity at the heterojunction replaces ∆Eg in (1.3) and is directly related to the
current gain as follows [4]
8
In
: exp( ∆Ev / kT )
Ip
(1.4)
So if the valence band discontinuity is sufficiently large, as it is for the InP/GaAsSb
HBT, a significant current gain can be expected even if NE=NB. For an abrupt
heterojunction bipolar transistor, an advantage of the potential barrier (spike) in the
conduction band at the emitter-base interface is that the barrier facilitates the injection of
the electrons into the base region with a high velocity (~108 cm/s) that exceeds the
saturation velocity. The result is a highly efficient and very fast, near-ballistic electron
transport through the base. Thus, an HBT can be designed for high frequency operation
using a highly doped base without compromising injection efficiency or current gain.
1.4 Double Heterojunction Transistors
While Shockley’s initial description of the HBTs stopped with having a wide
bandgap emitter, now we know that having a wide bandgap material for the collector can
have significant advantages as well, a few of which are listed below [5]:
1) The hole injection from the base to the collector is suppressed because of the wide
bandgap collector. This is particularly important if the transistors are being used for
digital switching operations. Use of a wide gap collector facilitates the use of higher base
doping and at the same time keeping the collector doping low. In addition, there is a
complete suppression of parasitic charge storage, combined with greatly reduced RCtime constant due to lower base resistance as a result of higher base doping.
2) Using the same material for the emitter and the collector produces a double
heterojunction transistor (DHBT), one at the emitter and the other at the collector
junction. This translates into a huge advantage when HBTs are incorporated into ICs
9
since the collector and emitter can be interchanged. Implementation of Emitter Coupled
Logic (ECL) becomes easie r by the use of DHBTs.
3) Specific material systems like the InP-based materials offer superior transport and
thermal properties than GaAs based materials. In fact, InP-based HBTs have
demonstrated some of the highest microwave performances and InP-based DHBTs have
additional benefits like enhanced breakdown voltages.
4) One of the most important advantages of the DHBTs, including InP/GaAsSb/InP
DHBT that we are going to study, is that they have a low turn-on voltage of ~0.4V
translating into higher power gain and power added efficiency, which is extremely
important for portable devices like mobile phones running on limited power sources like
batteries.
5) However, a significant drawback for npn DHBTs, is the fact that the ∆Ec at the basecollector junction can form a barrier to electron injection from the base into the collector
for material systems such as InP/InGaAs. This degrades the current gain and device
speed. One of the advantages of the InP/GaAsSb/InP system is that this barrier is nonexistent [6].
1.5 InP-Based Heterojunction Devices
The emergence of the 10 Gb/s optical communication systems and the drive for
hardware operating at 40 Gb/s has pushed the existing III-V technologies towards their
limits [6]. However, continuing growth in the field of broadband communications, fibre
optic transmissions and microwave direct digital frequency synthesis has demanded
continuing advances in compact, highly efficient and cost effective solid-state solutions.
10
To date, InP-based HBTs have demonstrated some of the highest fT and fmax frequencies
for any solid-state devices [7]. Even though the initial thrust in heterojunction technology
was based on GaAs devices, recent advances in MBE and MOCVD have enabled InP
devices to dominate at millimeter wave frequencies because of the following reasons:
1) Substrate thermal conductivity: InP has a higher substrate thermal conductivity
than GaAs (0.68 versus 0.46 W-cm/K) resulting in lower device heating [8].
2) Optical Integration: InP devices are compatible with long wavelength (1.3 and
1.55 µm) laser and LED sources. This allows for direct integration and tight
coupling of light sources and transmitter/receiver circuitry [8].
3) The lower surface recombination velocity of the InP-based HBTs (three orders of
magnitud e lower than that of GaAs) results in a reduction of surface leakage
currents and improved gain at low current densities, enhancing the ability to scale
down devices to smaller dimensions for LSI implementation [7]
4) InP based devices have lower turn-on voltages, significantly lower 1/f noise and
higher power added efficiency (PAE) than GaAs devices. [7]
5) At a clock rate of 50 GHz, for reasonable levels of power dissipation on-chip, InP
HBTs provide significantly more integration capability because of their ol wer
power dissipation per gate than GaAs and SiGe HBT technology [9] .
The following Figure 1.3 gives us a quick overview of the advantages of InP over
conventional semiconductor materials like GaAs and Si [9]. Figure 1.3(a) shows InPbased HBT, have lower turn-on voltages than Si BJTs and GaAs HBTs due to the smaller
11
bandgap of InGaAs. Figure 1.3(b) shows that InP HBTs have a higher breakdown voltage
at a given collector doping, while Figure 1.3(c) shows that InGaAs and InP have higher
electron mobilities than GaAs. Finally, Figure 1.3(d) shows that InP has a larger thermal
conductivity than GaAs, though less than that of Silicon. This entails huge advantages for
InP-based devices over GaAs-based ones in high frequency (>10 GHz) RF power devices
where most of the III-V devices find application, in terms of better thermal management
and long term device reliability.
Figure 1.3 Comparison of material properties of InP, GaAs and Silicon [9]
12
Almost all of the InP-based heterojunction devices are implemented using InGaAs as
the narrow gap material for the base semiconductor. InP/InGaAs-based single HBTs have
demonstrated outstanding properties with cut-off frequencies more than 200 GHz and
with extrapolated cutoff frequencies exceeding 1 THz [10]. This impressive performance
of the InP-based HBTs is mainly because of aggressive scaling and reduction in the
collector junction area by backside processing [10] and because of excellent material
properties of InGaAs in terms of mobility and electron saturation velocity. This poses a
very good question as to why switch to GaAsSb, when InGaAs is doing the job
admirably. However, we will shortly see in the following discussion where InGaAs fails
and GaAsSb steps in to save the day. The main drawback with the InP/InGaAs is that it
suffers from a low breakdown voltage because of the narrow InGaAs collector energy
gap of 0.75 eV [11]. Kurishima et al and Chor et al, [12, 13] proposed enhancing the
breakdown voltages by using an wide bandgap AlInAs or InP collector layers in the
double heterojunction transistor. But this advantage comes at the cost of a collector
current blocking effect caused by the positive conduction band discontinuity between the
InGaAs base and the wider band gap InP collector. For an InP collector, a blocking barrier
of 0.25 eV must be overcome between the base and the collector as shown by curve (a) in
Figure 1.4 where the base-collector discontinuity ∆Ec impedes the electron minority
carriers, dramatically reducing the device’s fT and the current gain. Various doping and
/or composition grading schemes have been developed to alleviate this blocking effect
[6]. In practice, sometimes the blocking effect is reduced and the current gain is improved
by using an undoped InGaAs spacer layer between the base and the collector as in curve
13
(b) in Figure 1.4 and curve (c) where compositional grading is employed. Curve (d)
shows the favorable band lineup for the InP/GaAsSb DHBT of interest here.
Figure 1.4 Conduction band profiles for a few design options for InP-based HBTs. [6]
The grading schemes set forth in [12,13,14] are difficult in the sense that they
introduce significant epitaxial growth complexity and impose stringent uniformity and
repeatability requirements on the epitaxial growth. Even these grading schemes do not
lend an easy or foolproof method for eliminating the collector-blocking effect at the basecollector interface, because high collector current densities cause a retarding potential,
eventually degrading the transistor performance [15]. The specifics of any grading and/or
doping schemes at the base/collector junction need to be considered carefully because
they can have a dominant impact on DHBT performance at high current densities [16]. In
14
contrast, the use of a GaAsSb base layer provides an elegant solution to the collector
blocking effect plaguing InGaAs-based DHBT designs. The staggered type II
heterojunction band lineup at GaAsSb/InP heterojunctions allows unhindered injection of
electrons from the GaAsSb base into the InP collector since the GaAsSb conduction band
lines up 0.10–0.15 eV above the InP conduction band edge near the lattice- matched
composition of GaAsSb [17], [18]. As a result, InP/GaAsSb DHBTs benefit from two
fundamental advantages over InP/InGaAs DHBTs :
1) The structure requires no graded transition layers at the collector- or emitter-base
junctions, thus simplifying the growth of the epitaxial layers and
2) C-doped GaAsSb features high doping efficiencies [19] and displays little or no
H-passivation effects [15].
Also the low diffusivity and the good donor properties of Carbon doping ensures that
the base-collector junction is precisely and permanently self-aligned to GaAsSb/InP
interface leading to stability and repeatability of device characteristics.
1.6
InP/GaAsSb/InP Double Heterojunction Bipolar Transistors
As discussed in the previous section, an excellent solution for the collector blocking
effect seen in InP/InGaAs DHBTs has been found by utilizing GaAsSb in place of
InGaAs for the base layer. The staggered (type-II) bandgap lineup at the base-collector
junction for GaAsSb/InP heterojunction shown in Fig.1.4 (curve d) is free from the
difficulties discussed above [20, 21]. The energy band lineup of the GaAsSb with InP
provides an elegant solution to the collector-blocking problem. At 300 K, the
GaAs0.51Sb0.49 conduction band edge is above that of InP by 0.15 eV and the valence band
15
discontinuity is 0.78 eV as shown in Figure 1.5 [6]. This results in a non-blocking
conduction band profile at the base-collector heterojunction, eliminating the current
blocking effect faced in conventional InGaAs DHBTs. There is no need for
compositional grading at all!
Figure 1.5 Band lineup of InP/GaAsSb heterojunction [3]
The initial thrust in exploiting this system was delayed due to concerns with low
mobility and high resistivity in GaAsSb. The earliest reported device using this material
system was by Bhat et al. [22] and McDermott et al. [15] in 1996. The ir devices had fT
and fmax performance of around 30GHz and 45GHz, respectively. These results
discouraged further development using this material system for a while, considering the
difficulty in growing GaAsSb layers with low resistivity. Also the mobility of GaAsSb is
roughly 50-60% of that in InGaAs for a given concentration. While there is a conduction
band barrier at the emitter-base junction impeding electron injection into the base from
the emitter, the effect is not fatal and high performance InP/GaAsSb DHBTs have been
reported [3]. Recent developments have shown impressive performance gains in terms of
16
cut-off and maximum frequency of operation. The following table gives a series of
performance benchmarks in the development of the device.
Table 1.1 Evo lution of InP/GaAsSb/InP DHBT device development
AC
Gain
dB
fT
(GHz)
fmax
(GHz)
Base/Collector
Thickness A0
Emitter Size
µm2
45
N/A
N/A
350-1500/3000
70X70
27
30
45
500/3000
2X20
50*
75
23
400/3000
5X12
>100
78
N/A
400/3000
5X12
39
305
230
200/2000
5X0.5
39
270
>300
250/2000
5X0.5
42
300
300
200/2000
0.4X11
>80
N/A
N/A
500/2000
20X20
Group
McDermott et
al
1996 [15]
Bhatt et al
1996 [22]
Bolognesi et al
1998 [23]
Hu et al
1999 [24]
Dvorak and
Bolgonesi et al
2000 [6]
Dvorak and
Bolgonesi et al
2000 [6]
Dvorak and
Bolognesi et al
2001 [3]
Rajavel et al
2003 [25]
* DC Gain
The MOCVD grown, Carbon doped, abrupt heterojunction, InP/GaAsSb/InP DHBTs
feature a very small VCE offset voltage < 0.1V and a low turn-on voltage of VBE of 0.4 V
at a current density of JC =1 A/cm2 , by taking advantage of the staggered band lineup at
the InP/GaAsSb interfaces [11]. Electrons are injected ballistically from the GaAsSb base
into the wideband gap InP collector where they travel with a saturated high drift velocity
and low rates of impact ionization. This is especially important as the minority carrier
17
electron mobility in the p-doped base is the order of 600-800 cm2 /Vs. This is low when
compared to similarly doped InGaAs layers with electron mobilities of 2000-3000 cm2 /
Vs in InP/InGaAs HBTs. This lower mobility necessitates the use of thinner bases for
GaAsSb than InGaAs to achieve comparable base transit times. However, to maintain an
acceptable base sheet resistance and high fmax a higher base doping is necessary. This
need for higher doping is solved by GaAsSb’s affinity for Carbon doping and low Hpassivation effects [20].
1.7 Advantages of InP/GaAsSb/InP DHBTs
The InP/GaAsSb staggered bandgap line-up has the added advantage, besides that of
having no collector blocking, the electrons from the base are launched into the basecollector depletion region with a high velocity exceeding their saturation velocity, a
phenomenon known as the velocity overshoot [4]. The massive valence band
discontinuity (~0.8 eV) at the emitter-base junction increases the emitter injection
efficiency by reducing the hole back injection from the base into the emitter. In addition,
the small energy gap of GaAsSb results in low emitter-base turn-on voltages, which make
the devices attractive for low-power, long-talk-time portable communication systems.
Analyzed from multiple points of view, the InP/GaAsSb/InP DHBT offers excellent
performance capabilities, by taking advantage of several bandgap engineering techniques.
The interesting part is that all these advantages come without resorting to any dopant or
compositional grading. The challenge is that the GaAsSb material system has not been
extensively studied and only a few have reported success in growing it [3,11,15,17,18].
Recently, Bolognesi et al. [3] have demonstrated InP/GaAsSb/InP HBTs with excellent
18
high frequency performance. These HBTs feature the best performance ever reported for
a DHBT in any material system with fT and fmax over 300 GHz with a AC current gain of
42 dB. They have overcome the speed advantage traditionally held by InP HEMTs and
InP/GaInAs HBTs, while maintaining good breakdown voltages and superior current
drive capability. A competitive analysis of the performance of the devices is given Figure
1.6 [26]. The figure illustrates that HEMTs generally lose their fmax advantage over HBTs
around 250 GHz, while InP/GaAsSb DHBTs close the significant cutoff frequency gap
between HEMTs and HBTs. The above consideration leads to the conclusion that
HEMTs may no longer offer significant intrinsic performance advantages over HBTs for
ultrahigh speed circuits at 80 Gb/s and beyond [26].
Figure 1.6 Comparison of reported fT and fmax values for InP HEMTs, GaInAs DHBTs
and InP DHBTs [26]
19
The collector breakdown voltage BVCEO is a major concern when evaluating the
performance of the HBTs. The use of a wide bandgap collector in InP/GaAsSb/InP HBTs
results in good breakdown voltages. Figure 1.7 shows that InP/GaAsSb/InP HBTs feature
some of the best fT vs breakdown voltage product for any of the InP based device [6].
Figure 1.7 fT values vs. BVceo for InP collector DHBTs from literature (n) M.W. Dvorak
et al (6)
One other big advantage of the InP/GaAsSb/InP HBTs is that it does not suffer from
the conventional Kirk effect and alloy potential blocking effect that leads to the current
degradation in other InP based HBTs. The use of a C-doped GaAsSb base layer enables
the fabrication of ultrahigh-speed InP collector DHBTs without the additional
complication of graded layers at the emitter-base and base-collector heterojunctions. The
favorable band alignment in InP/GaAsSb/InP DHBTs allows high collector current
densities required for high-speed logic applications, and eliminates the alloy potential
20
problems associated with graded interfaces under high current operation [27]. Figure 1.8
shows a comparison of the fT fall-off rates normalized to the peak fT of 300 GHz of
InP/GaAsSb/InP DHBTs [26]. In our case, the high-current degradation follows a
different mechanism from that of Kirk effect normally seen in AlInAs/GaInAs DHBTs
and GaInP/GaAs SHBTs. A high current induced thermionic barrier at the base-collector
junction of the InP/GaAsSb HBT reduces the electron exit velocity in the collector
leading to a fall in the fT and fmax performance [28]. However, this roll-off is pushed to
higher current densities in InP/GaAsSb DHBTs and the resulting DHBTs can be operated
at current densities approaching those found in high-performance SiGe/Si bipolar
transistors with the attendant reduction in dynamic emitter resistances and associated
charging delays [26].
Figure 1.8 Normalized cut-off frequency dependency on collector current density for
various DHBT and SHBT technologies [26]
More recently, Bove et al. [29] have reported a proof-of-concept demonstration
DHBTs using GaAlInAs as the emitter layer. This eliminates the small conduction band
21
spike seen in InP/GaAsSb/InP HBTs at the emitter/base interface. No microwave
performance evaluations have been reported. Even though using a GaAlInAs might have
superior transport properties in terms of its bandgap line- up with GaAsSb, the maturity of
InP growth techniques and its material advantages will likely allow it to outperform any
other device configurations for some time to come.
1.8 Motivation and Organization of the Thesis
With the advantages for GaAsSb-based HBTs as enumerated in the preceding
paragraphs, it is desirable to study and quantify the performance capabilities of the
InP/GaAsSb/InP DHBT and to optimize its design. Computer based simulation tools have
become an integral part of the modern design process, helping speed up the time to
market of integrated circuit products. CAD tools are useful for resolving design issues
like doping and layer thickness. Moreover, they can help us understand transistor
performance and offer deep insight into the physics behind their operation. By far, the
most important advantage is that simulation tools can drastically reduce fabrication costs
by providing the manufacturer with the optimum structured device. Ultimately, device
fabrication and characterization are required to finalize the device design.
This thesis is focused on the design and simulation of InP/GaAsSb/InP Do uble
Heterojunction Bipolar Transistors (DHBTs). The first chapter, as described above, has
given a brief overview of the operation of BJTs and HBTs, their differences in operation,
the advantages of a double heterojunction bipolar transistor as applied to InP/GaAsSb
material system and its advantages over InP/InGaAs DHBTs. Chapter 2 gives a brief
overview of the software use for simulation and summarizes the properties of InP,
22
GaAsSb and InGaAs used in the device modeling. In Chapter 3 an InP/GaAsSb/InP HBT
structure is defined, simulated and its performance compared with the published results.
The effects of various changes, like doping, base width and structure on the device
performance is analyzed in Chapter 4, and the optimum structure for best performance is
determined. Performance degradation due to high current effects is also examined.
Chapter 5 summarizes the results of the thesis and suggests future improvements and
progress that can be made.
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“Metalorganic Vapor Phase Epitaxy of High-quality GaAs0.5Sb0.5 and its Application to
Heterostructure Bipolar Transistors”, Appl.Phys.Lett., vol. 74, pp. 776-778, 1999.
[25] R.D. Rajavel, T. Hussain, M.C. Montes, M.W. Sawins, S. Thomas III, and D.H.
Chow, “Molecular Beam Epitaxial Growth and Characterization of InP/GaAsSb/InP
Double Heterojunction Bipolar Transistors”, J. of Crystal Growth, vol. 251, pp. 848–851,
2003.
[26] C.R. Bolognesi, N. Matine, M. W. Dvorak, O.J. Pitts, and S.P. Watkins, “Ultrahigh
Performance Staggered Line InP/GaAsSb/InP NPN Double Heterojunction Transistors”,
Jpn. J. Appl. Phys., vol. 41, pp1131-1135, prt.1, No.2B, 2002
[27] C.R. Bolognesi, N. Matine, M.W. Dvorak, X.G. Xu, J.Hu and S.P. Watkins, “ NonBlocking Collector InP/GaAsSb/InP Double Heterojunction Bipolar Transistors with a
Staggered Lineup Base-Collector Junction”, IEEE Electron Device Lett., vol 20, pp 155157 , 1999.
[28] C.R. Bolognesi, M. W. Dvorak, O.J. Pitts, S.P. Watkins, and T.W MacElwee,
“Investigation of High Current Effects in Staggered Lineup InP/GaAsSb/InP
26
Heterostructure Bipolar Transistor: Temperature Characterization and Comparison to
conventional Type-I HBTs and DHBTs” IEDM 2001, pp. 768-771, 2001
[29] P. Bove, H. Lareche, and R. Langer, “ InP/GaAsSb and (Al, Ga) InAs/GaAsSb
DHBT Material Grown in a Four Inches Multi-wafer MBE Machine” Indium Phosphide
and Related Materials Conference, 2002, IPRM 14th , pp. 607 -610, 2002.
27
Chapter II
Simulation Software, Techniques and Material Properties
2.1 Introduction
The core theme for this thesis is the use of Computer Aided Design (CAD) tools for
the simulation and modeling of HBTs. Simulation allows us to design, test, and evaluate
quickly semiconductor devices without physically fabricating them. This translates into
huge advantages in terms of cost reduction and vastly reduced time to market, as different
devices structures can be evaluated in a very short time. In addition, simulation packages
are powerful tools that can help us to obtain device performance parameters such as
potential, carrier and current profiles within the device during operation, which cannot be
measured experimentally.
The simulation procedure followed for this work is physics-based, that is based on
the processes occurring within the device and their description mathematically.
Semiconductor devices can be modeled in two ways; one is to determine the terminal
electrical properties of a device based on empirical results and model the device using
techniques like spline fitting. The other method is to study the carrier transport processes
taking place within the device. The later, physics-based simulation provides three major
advantages: 1) it is predictive, 2) it provides insight, and 3) it captures knowledge in a
way that makes it easier to understand the various phenomena acting within the device.
[1].
We use a physics-based approach to modeling of InP/GaAsSb DHBTs. In this chapter
we give a description of the software used for the simulation, the physics behind it and
28
the actual device physics models used. The material parameters used for the different
layers of the device are also summarized. In particular, the material properties of GaAsSb
needed for the simulation were derived from the published literature and are reported
here.
2.2 Simulation Technique
The simulation software package used for this work is a commercial device simulator
ATLAS, from Silvaco International [1]. ATLAS is a versatile, modular and extendable
software product for two and three dimens ional device simulation. Simulation is done by
discretizing the equations that describe the operation of a device onto to a two or three
dimensional grid, consisting of a large number grid points called nodes. The ATLAS
simulation package is built around physics-based models. These physics-based models
are basically a mathematical description of the various phenomena, such as carrier
generation, recombination and transport that are responsible for the operation of the
device. The models describe the dynamics of carrier generation, recombination and
injection as well as transport within different material regions of the device and coupling
between the regions. These models are quantified in differential equations and transposed
onto the grid to simulate the transport of carriers through a device structure. Electron and
hole concentrations are calculated, along with their spatial variation and dependence on
material properties as well as biasing. The simulator also predicts the electrical
characteristics of the device, for example the terminal currents that are associated with
the specified physical structures and different bias conditions. These results can be used
to characterize the DC and AC operation of the device and to provide insights into the
physical aspects of device operation, provided they include all the important device
29
physics. These models consist of a set of fundamental equations, which link together the
electrostatic potential, charge density and the carrier densities within a simulation
domain. An important advantage of this type of model is that it can not only be used to
predict the terminal current-voltage characteristics of the devices for comparison with
device measurements, but also to investigate the origins of the observed behavior and the
factors limiting the device performance.
2.3 Device Physics and Models
The simulation technique is a numerical one, which arrives at the terminal
characteristics of the device by solving the partial differential equations describing the
physics of the materials and the effects of potentials and heterojunctions on carrier
transport. These equations include Poisson’s equation, the carrier continuity equations
and the transport equations for each carrier (electrons and holes). These equations must
be solved simultaneously and self consistently in each region of the device. Here, a brief
description of the basic semiconductor equations involved is provided.
2.3.1 Poisson’s Equation
Poisson’s equation relates the electric field distributio n with the distribution in space
of the charge and is given in one dimension by [2]
dE( x) q
= ( p − n + Nd+ − N a− )
dx
εs
(2.1)
where E(x) is the electric field, ε s the dielectric constant of the semiconductor, p and n
are the carrier concentrations and N d+ , N a− are the concentrations due to ionized donor
and acceptor impurities, respectively all of which can be a function of position. Clearly,
30
the doping in each region of the device must be specified at the outset in order to describe
the electric field everywhere within the device. An alternate form of the Poisson equation
is obtained when the electric field E(x) in (2.1) is replaced by –dV/dx as given in (2.2).
Generally both the equations are referred to as the Poisson’s equation.
E (x ) = −
dV
dx
(2.2)
An important point that should be noted when working with HBTs is that the device is
composed of many layers of different semiconductor materials. So we have to take into
account the “quasi-electric” field contributed by the gradient of the electron affinity in the
case of compositional grading. Then the total electric field inside the space charge region
is the sum of the electric field contribution due to Poisson’s field and the quasi-electric
field.
E ( x ) total = E ( x ) poisson + E ( x ) q u a s i
(2.3)
2.3.2 Carrier Continuity Equations
The continuity equations for the electrons and holes are given by [1, 2]
∂n 1 ∂
=
• J n + Gn − R n
∂t q ∂x
(2.4)
∂p
1 ∂
=−
• J p +Gp − R p
∂t
q ∂x
(2.5)
where n and p are the electron and hole concentrations, J p and J n are the total electron
and hole current densities, G p and Gn are the generation rates for electrons and holes due
to optical absorption, Rp and Rn are the net recombination rates for electrons and holes,
respectively, and q is the magnitude of the charge on an electron. The rates of
31
recombination, Rn and Rp are proportional to the excess carrier concentration and are
given by Rn = (n-n0 /τn ) and Rp = (p-p0 /τp ) where τn and τp are lifetimes of the electrons
and holes, respectively.
2.3.3 Transport Equations
The hole and electron current densities J p and J n are important terms in (2.4) and
(2.5) and therefore they justify further elaboration. These two terms are derived from the
drift-diffusion model relating the carrier concentrations to the current density and are
given as follows [1, 2]
J p = q µ p pE ( x) − qDp
J n = q µn nE ( x ) + qDn
dp( x)
dx
dn ( x )
dx
(2.6)
(2.7)
where µn and µ p are electron and hole mobilities, and D p and Dn are hole and electron
diffusion constants. The first term involving the E(x) is called the drift current while the
second term refers to the diffusion current. By default, ATLAS solves both equations.
However, for some specific circumstances, it is sufficient to solve for only one carrier.
Device modeling consists of the solution to the above defined five equations (Poisson,
continuity and current density equations) subject to boundary conditions imposed by the
device geometry and biasing. The previously discussed set of five equations provides a
basic framework for device simulation once a device structure and its biasing have been
specified. These current density equations are based on transport models that are obtained
by applying approximations and simplifications to the Boltzman transport equation.
However, to completely and accurately define the device model, it is essential that each
of the parameters in (2.1) to (2.7) be further defined by secondary equations. For
32
example, the electron mobility maybe a function of position x if the doping is not
uniform, since the mobility varies with the doping level. In the simplest cases the material
parameters are just constants, but they must be specified for each material incorporated in
the device.
Other models incorporated in the simulation include ones for the carrier generationrecombination mechanism, band gap narrowing model at high doping density, density of
states for different materials and velocity saturation effects at high electric fields [1].
2.4 Material Parameter Models
Many properties of the materials are important for device modeling such as energy
bandgap, the effective mass, mobility, saturation velocity, and recombination lifetimes.
These parameters are typically dependent on the local concentration of the dopants and
the temperature as well as the composition. Material models are needed for device
modeling that incorporate these effects and are briefly discussed here.
2.4.1 Mobility Modeling
The carrier mobility is a parameter that characterizes the drift motion of the carriers
in the presence of an electric field. The electrons and holes are accelerated by electric
fields, but lose momentum because of various scattering process involving lattice
vibrations, impurity ions, material interfaces and other imperfections [3, 4]. The effects of
these microscopic phenomena are averaged and lumped together into the macroscopic
parameter called the mobility, which is a function of the local electric field, doping
concentration, and temperature. Though a variety of models are available for
33
characterizing the mobility’s behavior in low and high electric fields, we use two
empirical models that are widely used. These are
1) Caughey-Thomas doping dependent mobility model and
2) Parallel electric field dependent mobility model
Each of these models is described in more detail below.
2.4.1.1 The Caughey-Thomas Model
Also known as the analytic low field mobility model, this model specifies the
mobility dependence on doping and its variation with temperature. However, our
simulations are done at 300 K, so the temperature dependence of the mobility is not
employed. In its simplest form, the model is given by [3]
µn ( N ) = µmin +
µ max − µ min
N a
1+ (
)
Ncr
(2.8)
where N is the total dopant density, µ max , µ min are maximum and minimum possible
mobility, at low and high doping, respectively, NCr is the critical doping above which the
mobility degrades, and α is a fitting parameter. However, the Caughey-Thomas model [3]
does not take into account the mobility difference between majority and minority carriers,
as these undergo somewhat different scattering mechanisms. However, there is little data
to distinguish these, so a single mobility will be used. For each of the materials in the
InP/GaAsSb/InP HBT these parameters, for the mobility model for electrons and holes
for (2.8) must be specified. These are described for InP and GaAsSb later in this chapter.
34
2.4.1.2 Parallel Electric Field Dependent Mobility
As the electrons and holes are accelerated by the electric field, their drift velocities
initially increase linearly. However, these velocities begin to saturate at higher electric
fields ~105 V/cm. So the mobility becomes a function of the electric field strength. The
following expression is an empirical one widely used to describe the mobility’s variation
between low and high electric fields [3]
1
1
µn ( E ) = µn 0[
] BETAN
µ E
1 + ( n0 ) BETAN
VSATN
(2.9)
1
1
µ p ( E ) = µ p 0[
] BETAP
µ p 0E BETAP
1+ (
)
VSATP
(2.10)
where E is the parallel electric field, µn0 , µp0 are the low field electron and hole
mobilities, respectively, derived from the Caughey-Thomas model, VSATN and VSATP
are the saturation velocities, and BETAN and BETAP are fitting parameters. The values
for these for each of the semiconductor materials of interest are given in the following
sections.
2.4.2 Carrier Generation-Recombination Models
When we consider a semiconductor material whether doped or undoped, there
always exists a thermal equilibrium concentration of holes and electrons due to a balance
between thermal generation and electron-hole pair recombination due to continual
excitation due to processes like phonon and photon emissions. These processes are
responsible for the generation-recombination of electron hole pairs, and are the
mechanisms by which the carrier concentrations return to equilibrium. For undoped
material, the electron and hole concentrations are equal and given by
35
n0 = p0 = nie
(2.11)
where nie is the intrinsic carrier concentration given by
− Eg
nie = N c N v e 2KT
(2.12)
where Eg is the semicond uctor energy bandgap. Nc and Nv are the effective density of
states in the conduction and valence bands, respectively, given by
N c = 2(
N v = 2(
2π kT 3/2 *3/2
) mde
2
h
2π kT 32 *3/2
) ( mlh + m*3/2
hh )
2
h
(2.13)
(2.14)
where h is the Planck constant, mde is the density of states effective mass of the electrons,
and mlh and mhh are the light hole and heavy hole effective masses, respectively. A
detailed description of the effective mass values for the GaAsSb material system is given
section 2.5.4. For an n-type semiconductor, the thermal equilibrium concentrations for
electron and holes, respectively are given by
n0 ; N D+ ; N D
(2.15)
p0 =
nie2
n0
For heavy doping, the energy bandgap is reduced so nie is enlarged and the minority
carrier concentration p0 is increased [1].
The duration the electron hole pairs remain without recombining determines their
lifetime in the material. It is an important parameter because it can influence the current
gain in an HBT. ATLAS implements carrier lifetime modeling by using the ShockleyRead-Hall (SRH) recombination model where the lifetime is dependent on the impurity
concentration [1,4],
36
RSRH =
pn − n 2ie
ETRAP
− ETRAP
τ p [n + nie exp(
)] + τ n[ p + nie exp(
)]
kTL
kTL
TAUN 0
1 + N /( NSRHN )
TAUP 0
τp =
1 + N /( NSRHP )
τn =
(2.16)
where ETRAP is the difference between the trap energy level and the intrinsic Fermi
level, TL is the lattice temperature in degree Kelvin, TAUN0 and TAUP0 are the electron
and hole lifetimes at very low doping, N is the local doping, and NSRHN and NSRHP are
the doping levels beyond which the carrier lifetimes decrease. The parameters τn and τp
correspond to the carrier lifetime in the material for a doping level N.
2.5 Material Properties of GaAsSb
In order to precisely simulate and predict device behavior, it is necessary that we
work with accurate values of the material parameters. For the HBT under consideration,
three different materials are involved: InP, GaAs0.51 Sb0.49 and In0.53Ga0.47 As, the last two
being lattice matched to InP. The material parameters of InP and InGaAs have been well
documented, and included in the ma terials library of Silvaco, whereas it is not so in the
case of new materials like GaAsSb. As in the case of InP and InGaAs, GaAsSb is an IIIV compound semiconductor material. The material properties of Gallium Arsenide
Antimonide (GaAsSb) depend upon its composition, i.e. Antimonide content. The most
commonly used composition for HBTs is GaAs1-x Sbx where X =0.49, which gives the
composition that is lattice matched to InP. The advantage of this system over other
ternary material systems is due to its large valence and small conduction band
discontinuity when it forms a heterojunction with InP. When used as a base in n-p-n
37
InP/GaAsSb/InP HBTs, the large valence band offset of 0.81 eV and the favorable
conduction band offset of 0.15 eV eliminates the collector current blocking effect at the
collector base junction that degrades the performance in the InP/GaAsSb/InP that
degrades the performance in InP/InGaAs/InP double heterojunction HBTs [5].
The interest in GaAsSb is relatively new and it has only recently been seriously
exploited as a material for HBTs. As a result, its material parameters are not well known
or widely reported in the literature. When studying the material properties of GaAsSb, it
is frequently necessary that we start with the properties of the better known binaries of
GaAs and GaSb and infer the properties of GaAsSb by interpolation.
The material
properties summarized here are not comprehensive and only those properties needed for
device simulation are included. For example, the temperature dependence of the
properties is not described as all simulations are done at 300K with no device self- heating
due to current flow assumed. However, the temperature dependent properties of the
material have been reported elsewhere [6,7].
2.5.1 Crystal Structure and Lattice Matching
GaAsSb has a Zinc Blende crystal structure as shown in Figure 2.1. This follows
from that of the binaries that constitute GaAsSb, since GaAs and GaSb have the same
Zinc Blende structure. In order to grow defect free layers of GaAsSb, it is a necessary and
important condition that GaAsSb be latticed matched to InP. The lattice constant of InP is
5.8687A. The lattice constant of GaAs1-x Sbx varies with the composition x, where GaAs1x Sbx
can be considered as a ternary as part of the InGaAsSb material system.
38
Figure 2.1 GaAsSb crystal structure where Sb is incorporated in some of the As sites [2]
Figure 2.2 shows the plot of the lattice parameter versus composition for the
quaternary In1-x Gax Asy Sb1-y . For deducing the lattice constant of GaAsSb, we can start by
neglecting the composition of Indium in the quaternary to simplify to the ternary and use
Vegard’s law to arrive at the composition of Sb, i.e. x in GaAs1-x Sbx, that is lattice
matched to InP. Then we have, a(x) = 5.6532(1-x) + 6.09593x, [7] where 5.6532A and
6.09593A are the lattice constants of GaAs and GaSb, respectively. For the lattice
matched condition where a(x) =5.8687A, matched to the lattice constant of InP, the value
of x would be = 0.49, i.e. the composition of Sb in GaAsSb. Similarly, In0.53Ga0.47 As is
the composition of the InGaAs ternary which is lattice matched to InP.
39
Figure 2.2 Lattice parameter versus composition plot for In1-x Gax Asy Sb1-y and
compositions (dotted line) lattice matched to InP [8]
2.5.2 GaAsSb Energy Band Gap
The energy band diagram of the binaries GaAs and GaSb are shown in Figure 2.3
[7]. From the diagram we can see that both of them have a direct energy band gap. The
energy band profile for GaAsSb will be similar but with a different bandgap. Due to the
relatively new interest in the material, few references agree on the precise value of the
energy bandgap. Theoretically, the bandgap of GaAsSb can be deduced empirically using
Vegard’s law from that of the quaternary In1-x Gax Asy Sb1-y as shown in Figure 2.4 based
on the composition determined from the lattice parameter as described above. The
energy gaps of GaAs and GaSb are 1.42eV and 0.70eV, respectively. For our case
neglecting the Indium composition, we arrive at the value of 1.09eV for GaAs0.51 Sb0.49.
40
Figure 2.3 Energy Band structure of the binaries GaAs (a) and GaSb (b) [8]
Figure 2.4 Plot of energy bandgap versus composition for the quaternary In1-x Gax Asy Sb1-y
for the material lattice matched to InP (dotted line) [8]
41
The empirical reported variation of the bandgap for GaAs1-x Sbx with the
composition of Sb is shown in Figure 2.5 [6, 9]. The empirical relations reported for the
bandgap variations are shown in equations (2.17) (Klem et al [6]) and (2.18) Merkel et al
[9]).
Eg (x) =1.35x2 -2.05x+1.42
(2.17)
Eg (x) =1.2x2 -1.9x+1.52
(2.18)
Considering the above two equations, the one given by equation 2.17 is more acceptable
when determining the bandgap variation with composition, because it’s closer to
experimental values reported by Bo lognesi et al [5]. The experimentally measured
bandgap of MOCVD grown, undoped GaAs51 Sb49 has been reported as 0.72 ±0.01eV at
300K [5] where the energy band gap was measured using optical absorption. This
measurement agrees with the calculated value of Eg=0.720eV obtained from Klem et al’s
[6] empirical expression for Eg (x) at T=300K.
Figure 2.6 shows the experimental confirmation for the variation of bandgap with
composition at different temperatures. Curve 1 shows the energy separation between the
L-valley and top of the valence band, while curves 2, 3, 4 shows the variation in bandgap
with composition at 100K, 210K and 300K respectively. The bandgap value reported in
[5] is given preference because the group has built actual working devices using the
above composition. In the following Table 2.1 the different bandgap values reported by
various sources are summarized.
42
Figure 2.5 Variation of GaAs1-x Sbx bandgap with Sb content • Klem et al et al. [6] and
♦Merkel et al [9]
Figure 2.6 Energy separation between L- valley of conduction band and top of the
valence band Curve 1 [Rosenbaum and Woolley ], Curves 2-4; [Taylor and
Fortin], versus composition x. 2 - T=100 K, 3 - T=210 K, 1, 4 -T=300 K. [7]
43
Table 2.1 Bandgap of GaAs0.51Sb0.49
Energy gap eV
Source
1.09
Vegard’s Law
0.72
Bolognesi et al (5)
0.72
Klem et al (6)
0.8772
Merkel et al(9)
0.7396
Matine et al(10)
Figure 2.7 shows the 10 K PL peak positions of all investigated samples plotted
versus the Sb concentration [11].
It provides direct experimental evidence for the
bandgap of GaAsSb. Except for the lattice matched composition when Sb content = 0.49,
the material is either under tensile or compressive stress. The band energy diagram is also
a good way of predicting the lattice matched condition of GaAsSb grown on InP. For
example, GaAs1-x Sbx under tensile strain (x<0.49), the light hole band (lh) lies above the
heavy hole band (hh) at the center of the Brillouin zone, and therefore the transition
between the conduction band (cb) and the lh band forms the lowest band gap. For
compressively strained GaAs1-x Sbx, for values of x>0.49 the hh band is located above the
lh band which makes the cb-hh transition the lowest Bandgap. In the lattice matched case
the hh band and lh band are degenerated and band gap is identical to that of unstrained
GaAsSb, thereby establishing the lattice matched condition of GaAs0.51Sb0.49 .
44
Figure 2.7 PL spectra for GaAsSb for various Sb concentrations [11]
2.5.3 Bandgap Offsets for InP/GaAsSb Heterojunctions
We are very much interested in the bandgap offsets at the InP-GaAsSb
heterojunctions because it plays a major part in determining the performance parameters
of the npn HBTs, such as the cut-off frequency, the turn-on voltage, and the current gain.
Figure 2.8 shows that the InP/GaAsSb heterojunction is a type II heterojunction with a
conduction band offset ∆EC as 0.15 eV and the valence band offset ∆EV as 0.78eV as
reported by Bolognesi et al [5]. However, we also have slightly different values reported
by the same group [6], for ∆EC and ∆EV as 0.18eV and 0.81eV, respectively [5]. We
follow the later values for simulation, because they have been the most recently reported
45
values for the offsets reported by this group. Type II band alignment in GaAsSb/InP
heterojunctions has been proved experimentally by Hu et al. [12].
With a band gap alignment as shown in the Figure 2.8 the electrons are injected into
the GaAsSb base thermally, where as they are launched into the InP collector layer with
high initial velocity corresponding to the conduction band discontinuity ∆EC. Such a
mechanism is a beneficial factor affecting the electron transport in the base-collector
depletion layer and ultimately the high frequency performance of these devices.
Knowledge of the bandgap offsets is important because it helps us to model the device
accurately in numerical simulations. However, none of the recent reports for this material
system considers bandgap narrowing due to heavy doping effects. Because of bandgap
narrowing, the bandgap offsets might change resulting in somewhat different
performance of these devices. These effects become important considering the higher
operating current of these devices particularly at high frequencies.
Figure 2.8 Staggered Band line-up at InP/GaAsSb Heterojunctions [10]
46
Figure 2.9 shows how the offsets differ when GaAsSb is under tensile or
compressive stress due to non- latticed matched composition and conditions with InP [11].
This is interesting to note because by varying the band offsets we can control the turn-on
and the collector offset voltage for the HBT to some extent. The offsets are nothing but
energy differences between the corresponding conduction and valence band lineups at the
heterojunction interface. For Sb composition x>0.27, the conduction band offset becomes
negative i.e., Ec (InP) < Ec (GaAsSb) and thus GaAs1-x Sbx on InP shows a staggered typeII band alignment, as shown in Figure 2.9. The conduction band (cb) offset and valence
band (vb) offset offsets of strained GaAs1-x Sbx relative to InP can be curve fitted to
∆Ecb(x) = 0.13-0.49x (eV) and ∆Evb(x) = 0.43+0.64x (eV) for 0.2<x<0.7 [6], where ∆Ecb
= Ec (InP)-Ec (GaAsSb) and ∆Evb = Ev (GaAsSb)-Ec (InP). The band offsets are defined
as the energy difference between the respective conduction and valence band of the
semiconductor materials, when the heterojunctions are lined-up.
plotted in Figure 2.10.
47
The equations are
Figure 2.9 Band offsets of GaAsSb on InP [11]
We can see in Figure 2.10 that the ∆Evb varies more rapidly than ∆Ecb for variations
in Sb composition. The highest valence band discontinuity that can be reached is
0.878eV, whereas for conduction band discontinuity it is 0.213eV. While base push out is
certainly eliminated due to the large ∆Evb, its effect on high current fT roll-off is to be
studied for the specific case of InP/GaAsSb HBTs. If the large ∆Evb helps in achieving
higher current densities and so higher current gain and fT , then lattice mismatched
GaAsSb can be grown for the base region, keeping in mind that for achieving a minimum
base transit time, the thickness of the base must be small, i.e., 200-400A0 . Better device
performance certainly can be achieved by exploiting the unique bandgap lineup.
48
Figure 2.10 Calculated Band offsets in GaAsSb on InP based on results of Merkel et al [6] (•) Ecb
and (€) E vb
2.5.4 Effective Masses and Density of States
Very few results have been published reporting the hole and electron effective
masses for GaAsSb. The values presented here have been interpolated in part from that of
the binaries GaAs and GaSb. From these hole and electron masses, the density of states
can be deduced as a function of the Sb content. The empirical relationship for the electron
and the hole effective masses for GaAsSb reported by Ya Vul et al [7] are given as
follows
mΓ = (0.063-0.0495x+0.0258x2 ).m0
(2.19)
mh = (0.51-0.11x)m0
(2.20)
mlp = (0.082-0.32x) m0
(2.21)
where mΓ, mh, and mlp are the electron, heavy hole and light hole masses, respectively and
x denotes the Sb alloy content. Figure 2.11 shows the variation of the hole effective
49
masses with the Sb content. The curves were plotted us ing the empirical relation shown
in the above equations (2.20) and (2.21) [7]. Figure 2.12 shows the empirical change in
the electron effective mass with the Sb content as a function of the relation in equation
(2.19). The curve corresponds to the values traced using equation (2.19) and the dots
represent the experimental values. We can see that the theoretical and experimental
values for the electron effective mass are close together. However, there have been no
reported experimental values for the hole effective mass in the literature.
Figure 2.11 Empirical variation of hole effective mass with Sb content [9] (♦) Heavy
hole mass (€) Light hole mass.
50
Figure 2.12 Variation of the electron effective mass with Sb Content [7]
Table 2.2 Effective Masses of Electrons and Holes for GaAs, GaSb and GaAsSb
Parameter
GaAs [7]
GaSb [7]
GaAs 0.51 Sb0.49 [7]
Electron effective Mass m0
0.063
0.041
0.0449
Heavy Hole Mass m0
0.51
0.4
0.4561
Light Hole Mass m0
0.082
0.05
0.0663
Table 2.2 summarizes the effective masses of the binaries GaAs and GaSb and the
lattice matched composition of GaAsSb. It should be noted the values in Table 2.2 are all
empirical ones calculated using equations (2.19), (2.20), and (2.21). We can see from the
table that GaAs has higher electron effective mass than other two materials listed above.
However, this does not result in higher mobility for GaAsSb, as we will see because it is
51
reduced due to alloy scattering effects in the material. The hole effective masses fall
approximately midway between the binaries. The results for the lattice matched GaAsSb
shown in Table 2.2 were used in our device simulation.
Effective Density of States and Intrinsic Carrier Concentration
The effective density of states of the carriers in the conduction and valence bands are
essential parameters for device modeling since they determine along with the Fermi
energy the equilibrium in density of electrons and holes. For the lattice matched case of
x=0.49 using the electron and the hole effective masses given in Table 2.2, the effective
density of states can be determined as Nc=2.39X1017 /cm3 and Nv =4.65X1018 /cm3 for the
conduction and valence bands, respectively [7]. We can infer from the equations (2.13)
and (2.14) that these parameters vary with temperature. The intrinsic carrier density is
given by equation (2.12) at 300 K is given as 9.61X1011 /cm3 . This compares very well
with experimental values of around 1012 /cm3 [7]. From the equation (2.12) we can predict
an increase of intrinsic concentration ni with increasing temperature, as the effective
densities increase with temperature as seen in equations (2.13) and (2.14). In addition, the
energy bandgap also typically decreases as the temperature rises. This rise in ni has been
experimentally confirmed by results from Ya Vul et al. [7] as shown in Figure 2.13.
52
Figure 2.13 Temperature dependence of intrinsic carrier concentration: 1) x = 0(GaAs),
2) x = 0.3, 3) x = 0.8, 4) x = 1 (GaSb) [7]
2.5.5 Mobility
2.5.5.1 Hole Mobility
Carrier mobilities are important parameters for device modeling as they ultimately
decide how “fast” the device operates. For our case where the base of the InP/GaAsSb
HBT is P type, both the electron and hole mobilities are important. Measurements of hole
mobility in lattice matched GaAsSb by Watkins et al. [13] indicate a very low value (~50
cm2 /v.sec). This has been attributed to strong alloy scattering mechanisms which
dominates the hole mobility at doping levels up to the 1019 range. This importance of
alloy scattering is supported by the experimental Hall data for a series of layers grown in
the entire composition range from x=0 to x=1 which are summarized in Fig 2.14 [13]. All
the samples had measured Hall concentrations in the range from 1x1019 to 1x1020 cm-3 .
We can infer that the mobility is much lower for intermediate ranges of Sb content than
the binary endpoints shown in Figure 2.14. The hole Hall mobility i.e. the majority carrier
53
mobility, for the p-type base in an InP/GaAsSb/InP HBT is 40cm2 /Vs at 1x1019 /cm3 for
the lattice matched composition. For intermediate compositions, there is a slight tendency
towards somewhat higher mobilities on the Sb rich side. [13], [14].
Figure 2.14 Hole Hall Mobility as a function of Sb in GaAsSb [13]
Figure 2.15 shows the dependence of Hall mobility for holes on the carrier
concentration for a number of samples grown at various temperatures and Sb mole
fractions. The dependence of the Hall mobility on doping le vel is weak, because of the
strong alloy scattering effect. This is interesting because the mobility does not change
significantly even at high doping levels, though these results are for a limited range of
doping. As a result, the base can be doped highly to reduce the base sheet resistance,
without any significant reduction in the base transit time.
54
Figure 2.15 Hall Mobility for holes as a function of carrier concentration for various Sb
compositions. Where different symbols correspond to the indicated Sb
composition ranges [13].
For a given doping level and Sb composition, there are significant variations in the
values of hole mobility, reported in the literature. However, for a given Sb composition,
there are very few experimental results and over a limited range of doping, so a rigorous
fit could not be attempted to the Caughey-Thomas mobility model for the doping
dependence given by equation (2.8). As a result, the fitting parameters were chosen so
that the derived Caughey-Thomas model fits reasonably well with the experimental
values at the high doping end where the material will be used. The maximum and
minimum reported values for hole mobilities are 60cm2 /v-s at a doping of 5X1016 /cm3
[14] and 20cm2 /v-s at 1X1020 /cm2 [15], respectively. Using this and other intermediate
doping values from experimental results
as
55
a starting point, the Caughey-Thomas
equation can be solved for critical doping Nc and the constant α in the equation (2.8),
repeated here for convenience,
µ p ( N ) = µ min +
µ max − µ min
N
1 + ( )a
Nc
(2.8)
The curve fitted Caughey- Thomas model for mobility variation with doping is shown
in Figure 2.16. The data points with the (+) symbol represent a few of experimental
values chosen from the data in Figure 2.15 for doping greater than 1019 /cm3 . There is
good agreement with the experimental values towards higher doping levels, where the
doping is comparable to the doping values usually used for our base in InP/GaAsSb
HBTs.
Figure 2.16 Hole mobility variation with doping: experimental values (+) [14] and
calculated Caughey-Thomson values (•)
56
2.5.6 Electron Mobility
The electron mobility in GaAsSb differs depending upon the type of dopant used.
When N-type doping is attempted using diethyl telluride, the electron mobility varied
from 2246 to 750 cm2 / V s for a doping concentration from 2X1017 to 1.5X1019 /cm3 [15].
GaAsSb is usually doped n-type using Silicon with majority carrier mobilities around
500-700cm2 /V s, significantly lower than for a material doped to a comparable level
using diethyl telluride (DETe) [15]. However, it should be noted that, going by published
results, DETe doping was not done for any fabricated InP/GaAsSb HBT. This might be
due to concerns of dopant out diffusion from the thin base (200-400 Ao thick). The
variation of mobility with doping for n-type dopants using the Caughey-Thomas model is
shown in Fig 2.17. The model was fitted using the same principles outlined for
determining hole mobility. The data points with the (+) symbol indicate the experimental
values from the literature. No data was found for the minority carrier mobilities for
electrons in p-type material, so the majority carrier mobility was used. Table 2.3
summarizes the Caughey-Thomas mobility parameters used in the device simulation.
57
Figure 2.17 Electron mobility variation with doping: experimental values (+) [13, 16] and
calculated Caughey-Thomson values (•)
Table 2.3 Caughey-Thomas Parameters for Holes and Electrons
Hole
µmax
cm2 /V s
60
µmin
cm2 /V s
20
7.935x1018
Fitting
parameter ∝
0.45244
Electron
2246
750
1.8199x1017
1.0577
Mobility
Nc cm-3
2.5.7 Carrier Lifetimes
The minority carrier lifetime in the base region is also critically important to the HBT
device’s performance, influencing both current gain and cut-off frequency. The minority
carrier lifetimes for GaAsSb were calculated from that of the binaries GaAs and GaSb
[16, 17], since no experimental values have been reported for lattice matched GaAsSb
The values adopted for the binaries are the longest reported lifetimes in the literature for
58
these binary materials. For our composition of the alloy lattice matched to InP, the values
were calculated using Vegard’s law for n-type and p-type material, respectively. The
values used are incorporated in the Shockley-Read-Hall recombination model (RSH
Model) are listed in Table 2.4.
Table 2.4 Electron and Hole Minority Carrier Lifetimes for GaAs, GaSb and Latticematched GaAsSb
Material
Electron Lifetime TAUN0(s) Hole Lifetime TAUNP0 (s)
GaAs [16]
5x10-9
3x10-6
GaSb [17]
2x10-7
1x10-8
1.005x10-7
1.53x10-6
GaAs0.51Sb0.49
(Vegard’s Law)
The critical doping NSHRN and NSHRP for which the lifetime falls-off in n and p
type GaAsSb is 2e17 and 5e17 cm-3 , respectively. Then the variation of the lifetimes τn
and τp with doping for latticed matched GaAsSb was calculated using equation (2.14)
(RSH Model) and are plotted in Fig. 2.18.
RSRH =
pn − n 2ie
ETRAP
− ETRAP
τ p [n + nie exp(
)] + τ n[ p + nie exp(
)]
kTL
kTL
TAUN 0
1 + N /( NSRHN )
TAUP 0
τp =
1 + N /( NSRHP )
τn =
59
(2.14)
Figure 2.18 Calculated carrier lifetime variation with doping (€) Hole lifetime, (•)
Electron life time
2.6 Material Properties of InP and InGaAs
2.6.1 Indium Phosphide
Indium Phosphide (InP) forms the collector and emitter material of the
InP/GaAsSb/InP HBT studied here. InP is a well known direct bandgap material with a
bandgap energy of 1.344eV [18]. Because of its application in almost all the III-V based
devices and lightwave circuits, its properties have been extensively documented. We will
not go into the details, but we will briefly summarize the mobility parameters relevant to
our simulation along with that for InGaAs. Deducing the minority carrier lifetime for InP
poses more of a challenge because it is a strong function of material quality and
processing history. Hence, the default Silvaco material library values have been used for
simulation. These values are summarized in the table to follow.
60
2.6.1.1 Heavy Doping Effects in InP
Here we will briefly take a look at the effects of heavy doping in InP. This is important
because of its effect on gain and reliability of the device. Heavily doped n-InP has been
extensively studied by optical techniques, particularly the method of photoluminescence
spectroscopy. The dominant feature in these spectra is the Burstein-Moss shift. Band
filing manifests itself in the photoluminescence measurements as a broadening of bandto-band transition peak and an accompanying shift of that peak to higher energies as the
(~1016 /cm3 ) doping level increases [18]. This effect can become visible even at low
doping levels because of the low electron effective mass. Qualitatively, the cause of the
shifting and widening of the band-to-band peak is due to the electronic transitions from
states deep within the conduction band to states near the top of the valence band.
Figure 2.19 PL spectra of InP [18].
61
Here we characterize a series of five samples n-InP doped in the range of 2x1016 cm-3
to 4X1018 cm-3 to study the effect of doping such as bandgap narrowing.
Photoluminescence measurements were made at room temperature (RT=294 K). The
photoluminescence spectra are shown in Fig. 2.19. The RT data shows a single broad
peak located slightly above the intrinsic bandgap. As the doping increases, the band filing
effects manifests itself as described earlier as a broadening of the B-B peak coupled with
a shift to higher energy.
Detailed knowledge of the bandgap narrowing is important because it affects many
critical parameters such as intrinsic carrier concentration, absorption co-efficient,
emission spectrum and heterojunction band discontinuity, all factors used in device
design. The band gap reduction often used in electrical device design is a non-physical
quantity, which accounts for the degeneracy effects as well as physical band structure
changes.
In view of the use of hetero- interfacial band offsets for barrier formation, an
understanding of the effects of doping upon band structure, and especially upon the
fundamental bandgap, is essential for optimal device design. A significant modification
of the InP band structure occurs due to carrier-carrier, carrier- impurity, and impurityimpurity interactions. The net result is to lower the energies of the conduction band states
and raise the energies of the valence band states: the effect is therefore referred to as
bandgap narrowing. However, practically no work has been done on the heavy doping
effects in GaAsSb because of the relatively new interest in this material system.
There are seve ral methods by which the extent of bandgap narrowing can be obtained
from experimental photoluminescence data. There are several method by which this can
be done namely by studying the luminescence peak energy, spectral line-shape fitting,
62
extrapolation of the low energy side of the spectrum, and direct observation of the extent
of the band tail [18]. We will now characterize the bandgap narrowing only by using the
last method. Fig. 2.20 shows the values obtained.
Figure 2.20 Bandgap narrowing in InP due to heavy doping [18].
The bandgap narrowing is in the range of 0.08eV at ~5x1018 /cm3 for heavily doped
samples when calculated by band tailing method.
However, the exact allocations of the
narrowing in the valence and conduction bands are not known. We can make an educated
guess as to where this occurs. As a result of increasing doping, the valence band moves
up and the conduction band comes down, we can expect a decrease in valence band offset
∆Evb and an increase in the conduction band offset ∆Ecb.
2.6.2 InGaAs
InGaAs serves as the material for the emitter cap and sub-collector region. InGaAs has
some of the highest reported mobilities among III-V materials. Detailed description of
63
these parameters is elaborated in the reference by Levinshtein et al [18], and Datta et al
[19]. As discussed before, the minority carrier lifetimes are a strong function of doping
and is modeled using the empirical expression [19],
τ ( N ) = 10 β −γ log N
(2.22)
where ß and γ are fitting parameters summarized in Table 2.5 for InGaAs along with
maximum lifetime values for electron and holes. Figure 2.21 shows the plot of electron
and hole lifetimes as a .function of the doping level [19].
Table 2.5 Minority Carrier Lifetime Model Parameters for InGaAs
Parameters
Holes
Electrons
τmax (ns)
10
0.3
ß
22.4
12.6
γ
1.2
0.73
NC (cm-3 )
8X1017 8X1017
Figure 2.21 Electron ( ) and hole (O) minority carrier lifetime models as a function of
doping level [19].
64
The mobility parameters of InP [17, 19] for the Caughey-Thomas model described in
section 2.4.1.1 are given in the following Table 2.6 along with that for InGaAs [18, 19]
and GaAsSb. The mobility values for GaAsSb follow from the discussions earlier in the
chapter.
Table 2.6 Caughey-Thomas Parameters for InP, InGaAs, GaAsSb.
Mobility Parameters
MU1N.CAUGH (cm2 /v-s)
InP
[18,19]
300
InGaAs
[18,19]
3372
GaAsSb
MU2N.CAUGH (cm2 /v-s)
4917
11599
750
MU1P.CAUGH (cm2 /v-s)
20
75
20
MU2P.CAUGH (cm2 /v-s)
151
331
60
ALPHAN.CAUGH
0.0
0.0
0.0
ALPHAP.CAUGH
0.0
0.0
0.0
BETAN.CAUGH
-2.3
-2.3
-2.3
BETAP.CAUGH
-2.2
-2.2
-2.2
GAMMAN.CAUGH
-3.8
-3.8
-3.8
GAMMAP.CAUGH
-3.7
-3.7
-3.7
DELTAN.CAUGH
0.46
0.76
1.057
DELTAP.CAUGH
0.96
1.37
0.45244
574
NCRITN.CAUGH(cm-3 )
6.4e17
8.9e16
1.8190e17
NCRITP.CAUGH(cm-3 )
7.4e17
1.0e18
7.935e18
65
Table 2.7 Summary of Important Material Parameters for GaAs0.51Sb0.49 InP
In0.53Ga0.47 As
Parameter
Symbol
GaAs 0.51 Sb0.49
InP
In0.53Ga0.47 As
Permittivity
ε r/ε0
14.4 [7]
12.35
13.88
Energy Gap
Eg(eV)
0.72 [5]
1.344
0.74
Electron affinity
χ(eV)
4.09 [7]
4.38
4.58
Electron
effective mass
Light hole
m */m
n
o
0.04494[7]
0.08
0.041
m */m
lh
o
0.06632[7]
0.089
0.45
Heavy hole
m */m
hh
o
0.4561 [7]
0.6
0.052
Electron
µ
n
5400cm2 /Vs
12000cm2 /Vs
200cm2 /Vs
300cm2 /Vs
2.3875x1017 cm-3 [7]
1.1x1019 cm-3
7.7x1018 cm-3
4.6456x1018 cm-3 [7]
5.7x1017 cm-3
2.1x1017 cm-3
Mobility
Hole Mobility
µp
700cm2 /Vs @3x1017 cm3
[7]
40cm2 /Vs@5x1017 cm-3
[14]
Valence band
density of states
Conduction band
density of States
Nv
Nc
2.7 Conclusion
In this chapter, a brief overview of the simulation software was given along with the
physics-based models used in the simulation and analysis of the performance of the
device. The material properties of GaAsSb were investigated in detail, such as the band
energy gap, mobility, effective masses, lifetime and density of states. The bandgap offsets
66
of GaAsSb with InP was discussed with emphasis of its effects on device performance.
Finally important properties of InP and InGaAs are summarized.
References
[1] ATLAS User Manual, Vol. 1, Silvaco International, Santa Clara, CA, Feb’ 2000
[2] W. Liu, Handbook of III-V Heterojunction Bipolar Transistors, John Wiley and Sons
Inc., New York, pp 26-27
[3] D.M. Caughey and R.E. Thomas, “Carrier Mobilities in Silicon Empirically Related
to Doping and Fie ld”, Proc. IEEE 55, pp.2192-2193 1967
[4] D.J. Roulston, N.D.Arora, and S.G.Chamberlain, “Modeling and Measurement of
Minority Carrier Lifetimes Versus Doping in Diffused Layers of n +/- p Silicon Diodes”,
IEEE Trans. of Electron Devices, pp 284-291, Feb 1982.
[5] C.R. Bolognesi, N. Matine, M.W. Dvorak, X.G. Xu, J.Hu and S.P. Watkins, “ NonBlocking Collector InP/GaAsSb/InP Double Heterojunction Bipolar Transistors with a
Staggered Lineup Base-Collector Junction”, IEEE Electron Device Lett., vol 20 pp 155157 , 1999.
[6] J. F. Klem, D. Huang, H. Morkoc, Y. E. Ihm, and N. Otsuka, Proc. SPIE 877, 28
1988
[7] A. Ya Vul,”Handbook Series on Semiconductor Parameters” Vol 2, New Jersey,
World Scientific, 1999, 111-131.
[8] K.P. Roenker, “ECES 750 Semiconductors and Heterojunctions”, University of
Cincinnati, Class Notes, Fall 2000.
[9] K.G. Merkel, V.M Bright, M.A. Marciniak,
C.L.A Cerny, M.O. Manasreh,
“Temperature Dependence of the Direct Band Energy Gap and Donor-Acceptor
67
Transition Energies in Be-doped GaAsSb Lattice Matched to InP”, Appl. Phys. Lett., Vol
65, pp 2442-2443, 1994.
[10] N. Matine, M.W. Dvorak, S. Lam, C.R. Bolognesi, “Demo nstration of GSMBE
Grown InP/GaAsSb/InP DHBTs”,
IEEE Indium Phosphide and Related Materials
Conference Proceedings, pp 239-242, 2000
[11] M. Peter, N. Herres, F. Fuchc, K. Winkler, K.H. Bachemand J. Wagner, “Band Gaps
and Band Offsets in Strained GaAs1-y Sby on InP Grown by Metalorganic Chemical
Vapor deposition.” Appl. Phys. Lett., Vol 74. pp. 410-412, 1999
[12] J. Hu, X. G. Xu, J. A. H. Stotz, S. P. Watkins, A. E. Curzon, M. L. W. Thewalt, N.
Matine, and C. R. Bolognesi, “Type II Photoluminescence and Conduction Band Offsets
of GaAsSb/InGaAs and GaAsSb/InP Heterostructures Grown by Metalorganic Vapor
Phase Epitaxy,” Appl. Phys. Lett., vol. 73, pp. 2799–2801, 1998
[13] S.P. Watkins, O.J. Pitts, C. Dale, X.G. Xu, M.W. Dvorak, N.Matine, and C.R.
Bolognesi, “ Heavily Carbon-Doped GaAsSb Grown in InP for HBT Applications”, J.
Crys. Growth, Vol 221. pp. 59-65, 2000
[14] V. Fink, E. Chevalier, O.J Pitts, M.W. Dvorak, K.L. Kavanagh, C.R. Bolognesi and
S.P. Watkins, “Anisotropic Resistivity Correlated with Atomic Ordering in P-type
GaAsSb”, J. Crys. Growth, vol 79, pp 2384-2386, 2001
[15] B.T. Mc Dermott, E.R. Gertner, S. Pittman, C.W. Seabury and M.F. Chang, “
Growth and Doping of GaAsSb via Metalorganic Chemical Vapor Deposition for InP
Heterojunction Bipolar Transistors”,
Applied Physics Letters, vol 68, pp1389-1388,
1996.
[16] Goldberg Yu. A. and N.M. Schmidt, “Handbook Series on Semiconductor
Parameters”, Vol. 1 World Scientific, London, 1999, pp. 40-97.
68
[17] M.Levinshtein, S. Rumyantsev and M. Shur, Handbook Series on Semiconductor
Parameters, Vol.2, World Scientific, London, 1996, pp. 169-190.
[18] R.M. Sieg, “A Photoluminescence Study of Heavily Doped Indium Phosphide”, M.S
thesis, Ohio State University, 1994.
[19] S. Datta, S. Shi, K. P. Roenker, M. M. Cahay, and W. E. Stanchina, "Simulation and
Design of InAlAs/InGaAs Pnp Heterojunction Bipolar Transistors," IEEE Trans. on
Electron Devices: Vol. 45, No. 8, Aug. 98, pp. 1634 - 1641.
69
Chapter III
Simulation of InP/GaAsSb/InP HBTs and basic results
3.1 Introduction
In this chapter, we model and analyze the structure and performance of
InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) using a commercial
numerical device simulator ATLAS from Silvaco Inc [1]. In the previous chapter, we
described the material parameters and models. Here we briefly explore how these models
are incorporated in the simulation software, which is followed by a brief discussion on
how the actual simulation is done. Next, we present some basic simulation results for the
InP/GaAsSb DHBT.
In this chapter, the D.C, small signal AC and microwave
performance of a specific transistor structure is evaluated and the results are compared
with the published results by Bolognesi et al. [2], thereby establishing the reliability of
the simulations. In the following chapter, we report simulation results for the
modification and performance optimization of the device structure.
3.2 Software Description
The ATLAS software package is a comprehensive and flexible tool for simulating the
electronic performance of arbitrary two dimensional device structures, which can be
composed of semiconductors, insulators, conductors and terminals. The simulation can be
performed to obtain not only DC, small signal AC and microwave analysis of the device
terminal behavior, but also analysis of the internal device parameter distributions, such as
the conduction and valence band energies, electrostatic potential, electric fields, electron
70
and hole concentrations and the current components. It also includes the interface physics
models, which are provided for all topology combinations, such as heterojunctions,
metal-semiconductor contacts and surfaces. These capabilities enable accurate simulation
of device parasitics, leakage currents and trapped charges.
The simulator consists of a device simulation sub framework ATLAS and a modular
set of application oriented tools like BLAZE, which is a 2-D device simulator for III-V
material devices and devices with position dependent band structure (heterojunctions).
The software also includes a Graphic User Interface (GUI) called TONYPLOT for
plotting the results. In addition, it has a two-dimensional fabrication process simulator
called ATHENA. Simulation of a device for its characteristics involves the following
methodology. Initially the device’s structure in two dimensions is described including all
the layer compositions, dopings and thickness as well as the location of the device
electrical contacts. Physical models are incorporated that specify the dependence of one
parameter on the other, such as carrier mobility on doping levels. Appropriate physicsbased models are then selected by including recombination models (Auger, ConSRH),
mobility models (Klaassen, Fldmob, Conmob), and bandgap narrowing models (BGN).
Then, the bias conditions are specified for performing the AC, DC and microwave
simulation. The two dimensional grid of mesh points for the calculations and the
appropriate numerical techniques for solving the differential equations can also be
specified. The device simulation process can be summarized as follows:
1. The physical HBT structure to be simulated is described,
2. The physical models to be used are specified, and
3. Input bias specification and the desired output device characterization extraction
values are set.
71
Each of these are discussed in more detail in the following sections and illustrated for our
InP/GaAsSb DHBT.
3.2.1 Definition of HBT structure and Mesh Specification
The physical structure of the device to be simulated is specified initially along with
the material regions and their properties. This includes specifying the composition,
doping and thickness of each region and the size and location of each of the device
contacts. We then proceed by specifying a two dimensional mesh of grid points over the
device structure. The meshes are defined in the ATLAS run file by using the statement
MESH for specifying the grid lines in the x and y direction. Defining of the mesh is a
very important part in the simulation procedure of the device, because the mesh grid
points are the places where the simulator solves the device equations and calculates the
parameter such as the electric potential and carrier concentration. Most of the
characteristics of the device are determined by what happens around the junctions and
the interfaces in the structure of the device. So it is important that our simulation be
accurate in these areas. For our simulation, this is achieved by making the mesh denser
around the emitter-base and base-collector junction areas where there is a rapid change
in carrier concentration and potentials as shown in Figure 3.1 for our InP/GaAsSb
DHBT. However for an excessive number of grid points, the simulator takes a much
longer time to arrive at a solution. So a balance must be found between excessive
simulation time and too coarse a mesh. Care should also be taken that the mesh is not too
dense, because it can overwhelm the simulations, resulting in convergence problems for
the equations. The optimum way for defining the mesh is that, it should provide
72
reasonably accurate results, whereas at the same time the simulator should be able to
solve the equations within a reasonable time and without any convergence issues.
Figure 3.1 An InP/GaAsSb/InP DHBT structure shown with mesh grid
3.2.2
Physics-Based Models
As described earlier in Chapter 2, the device characteristics are calculated using
physics-based models. The type of models used depends on the nature of the device being
simulated. In our case, for the HBTs, the most important models are the field and doping
dependent models for the mobility. The models used in the simulation are specified in the
MODELS statement of the ATLAS run file. The Caughey-Thomas model for the doping
dependency of the mobility is specified by the parameters “analytic” on the Model
statement. Similarly, the field dependent mobility model is activated by using the
73
parameter “fldmob”. The carrier recombination models (RSH Model) and the doping
dependent carrier lifetime models are activated by specifying “rsh” and “conrsh”
respectively on the models statement. All the previously mentioned models except for the
concentration dependent carrier recombination model “consrh” have been used in the
simulations. These models along with the parameters have been described in Chapter 2;
for a more detailed view of the syntax and the structure of the run file please refer to
Appendix A.
3.2.2.1 Hot-Electron Model
Some of the initial difficulties faced during the simulation runs were that of the low
values of fT and fmax for the simulated device when compared with the published
experimental results [2]. This we attributed to the low values of carrier mobility in the
GaAsSb base. However, the impressive high frequency performance of the device
reported in the literature has been attributed to the high velocity with which the electrons
are ballistically injected into the collector from the base [2]. This ballistic effect is due to
the small device dimensions (base width), high internal fields, and the conduction band
alignment at the base-collector heterojunction as shown in Figure 3.2. Because of these
properties the electrons injected into the collector have kinetic energies substantially
above kT, with a effective electron temperature Te larger than the lattice temperature T.
Though the Hot-Electron model incorporated into the simulation software was primarily
meant for modeling short channel effects in MOSFETs, we have included hot-electron
effects in our modeling of the InP/GaAsSb HBTs, since the basic underlying device
physics is the same.
74
Figure 3.2 The Staggered Bandgap line-up of InP/GaAsSb/InP HBTs [3]
Typically, hot-electron effects are included in HBTs by designing structures with a
wider band gap emitter than the base, as it is in our case. For very narrow base devices,
the transport process may not be diffusive since the carriers undergo relatively few
collisions in crossing the base. When the electrons are injected into the base over the
conduction band spike, they enter with excessive energy and velocity. Hence, the term
hot-electron effect is used. Normally incorporating the ballistic injection effects through
the hot-electron model reduces the base transit time by replacing the slow diffusive
motion by the faster ballistic propagation [3]. Hot-electron effect in InP/InGaAs HBTs
has been experimentally verified by Teissier et al. [4]. Electroluminescence spectroscopy
was used to directly investigate the transport of electrons through a relatively thicker base
(~150nm). Ballistic as well as quasi-ballistic transport was found to dominate the
75
transport process through the base even at room temperature. The ballistic effect was
found to become more pronounced as the base thickness was reduced. This observation
conforms to the reasoning that in a thinner base, the electrons undergo less collisions,
thus retaining their higher transport velocity. In our case, the base thickness used in all
the devices reported, is in the range of 200-500 A0 , much smaller than the 1500 A0 base
thickness used in the experimental device by Teissier et al. [4] to demonstrate the hotelectron effect. However, for our InP/GaAsSb DHBT there is no conduction band spike,
since the band alignment has the cond uction band edge for the GaAsSb base at a higher
energy than that for the implementation as shown in Figure 3.2. So there will be no hotelectron injection into the base. For our InP/GaAsSb DHBT, however, the hot-electron
effect will modify the transit time across the base-collector space charge region, since the
conduction band edge for the base is above that of the collector layer as seen in Figure
3.2. We can conclude that the dominant transport mechanism through the base of the
InP/GaAsSb DHBT and the reason for impressive fT and fmax performance in spite of the
low carrier mobility in the GaAsSb base is due the hot-electron effect in the basecollector space charge region. The hot-electron model is activated in the simulations by
using the parameter “hcte.el” in the models statement.
3.2.3
Input Bias Setup and Output Result Extraction
The bias conditions on the terminals of the device must be specified for each of the
electrodes. The simulation is initially done with no applied bias, so as to obtain an initial,
thermal equilibrium solution. The voltages applied on the terminals are then increased in
small steps so that the simulation proceeds without any convergence problems. The DC
biases are swept for the collector and the base terminal to obtain the Gummel plot of IB,
76
IC versus Vbe. For AC analysis, after obtaining the initial solution using the DC biases,
the AC bias is applied with a specific frequency. The frequency is then increased and the
AC analysis repeated. Subsequently, the microwave S-parameters can be calculated and
the performance results are extracted. Finally, the frequency of the analysis can be swept
and the device performance as a function of the frequency can be examined and the cutoff frequency fT and the maximum frequency of oscillation fmax determined. For detailed
instructions on applying bias and parameter extraction the reader is referred to the
ATLAS user manual [1].
3.3
Structure and Modeling of InP/GaAsSb/InP HBTs
The structure of the transistor examined in this simulatio n and studied is the one
reported by Bolognesi et al. [2]. This group has demonstrated devices with one of the
highest reported fT , fmax and breakdown voltages for the InP/GaAsSb/InP heterostructure.
The main reason for choosing their work as a bench mark is that they have reported a
series of fabricated devices with increasing performance measures. Table 3.1 shows a
series of reported results in the development of InP/GaAsSb DHBTs from several groups.
Bolognesi et al. [2] have reported partial results for different devices with various base
widths, doping, growth methods, and different emitter finger widths from 0.4µm to
several µm and different base junction areas. So an exact comparison of our simulations
results with their reported results is not possible. However, we will draw upon several
experimental results for comparison and validation of our simulation model. We examine
here in particular, a recent structure for which they have reported a more comprehensive
set of results [2].
77
Table 3.1 Evolution of InP/GaAsSb/InP DHBT Device Development.
AC Gain
Base/Collector
fT GHz fmax GHz
Emitter Size µm2
dB
Thickness A0
45
N/A
N/A
350-1500/3000
70X70
27
30
45
500/3000
2X20
50*
75
23
400/3000
5X12
>100
78
N/A
400/3000
5X12
39
305
230
200/2000
5X0.5
39
270
>300
250/2000
5X0.5
42
300
300
200/2000
0.4X11
>80
N/A
N/A
500/2000
20X20
Group
McDermott et al.
1996 [5]
Bhatt et al.
1996 [6]
Bolognesi et al.
1998 [7]
Hu et al.
1999 [8]
Dvorak and
Bolgonesi et al.
2000 [9]
Dvorak and
Bolgonesi et al.
2000 [9]
Dvorak and
Bolognesi et al.
2001 [2]
Rajavel et al.
2003 [10]
* DC Gain
The layer structure for the MOCVD-grown NpN InP/GaAsSb/InP abrupt double
heterojunction bipolar transistors (DHBTs) is shown in Figure 3.3. Bolognesi et al. [2]
have reported current gains of 40 dB, an fT of 300 GHz and an fmax of 300 GHz. The
devices have demonstrated outstanding dynamic performances over a wide range of
biases including the saturation mode [2]. The 2000 Å InP collector provides good
breakdown voltages of BVCEO = 6V; thinner (≈1500 Å) collectors allow operation at still
higher currents with fT = 200 GHz at a collector current density JC of 650 kA/cm2 .
78
Figure 3.3 Schematic of the simulated InP/GaAsSb/InP DHBT structure [2]
The device consists of a heavily doped, 3000 Å thick, InP substrate, an n+ (1 x
1019 /cm-3 ) 500 Å In0.53 Ga0.47As sub-collector, a 2000 Å n- InP collector (S: 3 x 1016 cm3
), a 200 (or 250) Å thick GaAs0.51Sb0.49 p+ base (C: 8 x 1019 cm-3 ), a 700 Å n InP
emitter (S: 3 x 1017 cm-3 ) and a heavily doped 500 Å InP/1000 Å InGaAs emitter cap as
shown in Figure 3.3 [2]. An important note here is that Bolognesi et al. [2] reported
results for two different structures, one with InGaAs layers for the sub-collector and the
emitter cap and the other structure with InP layers used throughout except for the base. It
is not clear what specific materials they used for the published results. For the purpose of
simulation we used InGaAs layers as shown in Figure 3.3.
The fabricated device was reported to have a double mesa structure with self-aligned
base contacts and an emitter area of 0.4 x 11µm2 as shown in Figure 3.4. For the purpose
of simulation, Silvaco assumes a default stripe length of 1µm. During extraction of
parameters from the simulations, the current values are properly scaled for comparison
with published results. The heavily doped InGaAs layers have been used for the SubCollector and the emitter contact layers to reduce contact resistance.
79
Figure 3.4 Simulated structure of InP/GaAsSb/InP HBT [after Bolognesi et al [2]].
The device contacts have been modeled as ohmic and with a base contact resistivity
of 2x10-7 Ωcm2 . This resistivity has been reported by Bolognesi et al [2] and has been
used in the simulations. The emitter and collector contact resitivities have not been
reported by the group and hence default resistivity values of 5x10-8 Ωcm2 have been used
in the simulations. The metal contacts have been placed 100 nm from the edges of the
mesas. The InGaAs Sub-collector region actually sits on a InP substrate (not shown here),
which was neglected for the purpose of simulation. Only half of the structure is taken into
account for simulation, because of the symmetry of the whole structure and the fact that
simulating the structure would take twice as much processing time. Due to the lack of
80
data on lateral contact dimensions, they have been chosen to conform to state of the art
values with 0.5µm emitter and base widths and 2µm wide collector contacts as shown in
Figure 3.4 [11]. It should be noted that the emitter width is slightly bigger than 0.4 µm
length used by Bolognesi et al. [2] in their device structure. However, as mentioned
earlier, current values are scaled to account for the difference in emitter widths. The
material parameters used in the simulation of the device are repeated from Chapter 2 for
convenience in Table 3.2.
Table 3.2 Summary of Important Material Parameters for GaAs0.51Sb0.49 InP
In0.53Ga0.47 As
Parameter
Symbol
GaAs 0.51 Sb0.49
InP
In0.53Ga0.47 As
Permittivity
ε r/ε0
14.4
12.35
13.88
Energy Gap
Eg(eV)
0.72
1.344
0.74
Electron affinity
χ(eV)
4.19
4.38
4.58
Electron
effective mass
Light hole
m */m
n
o
0.04494
0.08
0.041
m */m
lh
o
0.06632
0.089
0.45
Heavy hole
m */m
hh
o
0.4561
0.6
0.052
Electron
µ
n
700cm2 /Vs @3x1017 cm-3
5400cm2 /Vs
12000cm2 /Vs
40cm2 /Vs@5x1017 cm-3
200cm2 /Vs
300cm2 /Vs
2.3875x1017 cm-3
1.1x1019 cm-3
7.7x1018 cm-3
4.6456x1018 cm-3
5.7x1017 cm-3
2.1x1017 cm-3
Mobility
Hole Mobility
Valence band
density of states
Conduction band
density of States
µp
Nv
Nc
81
The unique bandgap line- up in the InP/GaAsSb DHBTs is exploited to achieve high
performance without grading or using different doping profiles to remove the conduction
band barrier at the collector junction seen in InP/InGaAs DHBTs. The bandgap profile
reported by Bolognesi et al. [3] is shown in Fig 3.2 for the InP/GaAsSb DHBT with 400
A0 base and a 3000 A0 collector. Since the conduction band edge for the GaAsSb is
above that for InP at the base-collector junction, electrons are injected into the collector
with an excess energy. These electrons are called hot electrons, which contribute to faster
than normal transport across the base-collector space charge region resulting in ballistic
transport. The conduction and the valence band discontinuity are ∆EC = 0.18 eV and ∆EV
= 0.78eV, respectively, at the base-collector heterojunction.
Using the layer structure given in Figure 3.3 following Bolognesi et al. [2], the
InP/GaAsSb/InP DHBT structure with self- aligned base and collector contacts was
simulated. The simulated energy band structure for a device with 200 A0 base width and
2000 A0 is shown in Figure 3.5. As can be seen, by comparison with that reported by
Bolognesi et al. [3] (see Fig 3.2), there is no conduction band spike at the base-collector
interface and there is a large valence band discontinuity at the emitter-base
heterojunction which effectively blocks hole back injection into the emitter. It is also
apparent that the lightly doped 2000A0 n-InP collector is completely depleted for zero
VCE.
82
Figure 3.5 Simulated conduction and valence band profiles for InP/GaAsSb/InP DHBT
with 200A0 base width and no applied biases.
The Gummel plot for the InP/GaAsSb DHBT as reported by Dvorak et al. [12] is
shown in Fig 3.6(a). The Gummel plot is a plot of the base and collector currents as a
function of Vbe when Vcb=0 V. We consider a slightly different structure by Dvorak et al.
[12] for comparison because of the non-availability of Gummel plots for the original
structure by Bolognesi et al. [2]. The primary difference in the structure is the larger
emitter area of 1.5X24 µm2 and the 400A0 GaAsSb base (C: 4x 1019 cm-3 ) of Dvorak et
al. [12]. For simulation, Silvaco assumes a emitter strip length of 1µm and hence the
simulated emitter area for our device is 0.5X1 µm2 . The simulated Gummel plot is
83
shown in Fig 3.6(b). The maximum collector current for the simulated structure was of
the order of a few milli-amperes, whereas for the fabricated structure it was of the order
of few tens of milli-amperes, which is expected due to the differences in emitter areas.
The trends of the curves are similar in these two plots. The maximum collector current is
reached for a base voltage of 0.8 Volts in both the cases.
For our simulation results, the base ideality factor ηb is 1.01 and the collector ideality
factor ηc is 1.115 for a forward voltage of Vbe=0.5V. This compares favorably with the
published results for the fabricated structure [12], which had ideality factors of ηb=1.09
and ηc=1.01. The ideality factor is a measure of which current component dominates the
total forward current. When the ideality factor is closer to 1, it means that the diffusion
current dominates, whereas when the recombination current dominates, η=2. Usually the
forward current consists of both the currents. For InP/GaAsSb DHBTs we see that the
ideality is closer to 1, meaning that the diffusion current dominates in the base and
reflecting the absence of a conduction band discontinuity at the base-emitter and basecollector heterojunctions. Recombination current usually dominates at smaller forward
biases (and current levels). At large biases (as 0.8 V), parasitic resistance and high
current effects causes the currents to tend to saturate.
84
Figure 3.6(a) Gummel-Poon plot of the InP/GaAsSb DHBT structure from Dvorak et al
for 400 A0 base width (C: 4 x 10-19 cm-3 ) and 1.5x24 µm2 [12]
Figure 3.6(b) Simulated Gummel-Poon characteristics of InP/GaAsSb/InP structure for
the device structure described in Figures 3.4 and 3.3 for Vcb=2.0 V
85
The common emitter characteristics reported for a 250 A0 base, 2000 A0 collector
InP/GaAsSb DHBT [2] are shown Figure 3.7(a). The transistor has common emitter
current gain of β=40-50dB, with breakdown voltages BV CEO > 6V, which can attributed
to the low electron multiplication co-efficient in the InP collector. Transistors fabricated
with 200 A0 base have similar characteristics, but with a higher current gain of around 80
dB. The simulated common emitter characteristics for the structure in Figure 3.3 are
shown in Figure 3.7(b). The simulations have been done in steps of 5µA base current,
considering the fact that the simulated device has a emitter stripe length of 1µm
compared to the 11µm used in the fabricated device [2]. The non- linearity of base current
in the saturation region of the Gummel plot, makes its difficult to simulated with 5µA
steps, hence at higher Ib bias we resort to a stepping of 10µA. The reported current of 490
kA/cm2 [2] could be reached by operating the device at higher base current bias, however
that would mean the onset of high current effects in the simulated device, considering its
smaller emitter stripe and the thinner 200A0 base. The calculated current gain is around
34 dB for the simulated device. This compares reasonably well with the 40-50 dB
Bolognesi et al. [2] reported for the 250A0 device, but not so for the device with a 200A0
thick base which has a 80 dB gain. The characteristics display a low collector offset
voltage which indicates that no blocking can take place at the base-collector junction, as
also evident from the device band diagram in Figure 3.5. Since, self- heating effects have
not been used in the simulation model, the transistor breakdown cannot be observed in
the characteristics.
86
Figure 3.7 (a) Typical common-emitter characteristics for a small area 0.4x11µm2 emitter
device with a 250 Å base and a 2000 Å InP collector [2].
Figure 3.7(b) Simulated common-emitter characteristics for a 0.5x1 µm emitter device
(Fig 3.3) with a 200 A0 base and 2000 A0 InP collector
87
The frequency response of the current and power gain of the fabricated structure
reported by Bolognesi et al. [2] are shown in Figure 3.8(a) for a device with a 200 Å thick
base and 0.4x11µm2 emitter. The transistor shows an fT =300GHz and fmax=300 GHz
obtained by extrapolating the current gain and Mason’s unilateral power gain U assuming
a -20dB/oct roll-off, with the peak AC current gain being 42 dB.
The simulated
performance of the structure is shown in Figure 3.8(b). For comparison, the simulated
structure had a maximum fT of 344 GHz and the peak current gain was 34 dB, similar to
Bolognesi’s results. The discrepancy in gain might be due to the fact that, the DC bias
point for the measurement was not specified in [2] and hence the characterization could
have been done at different bias points. The simulated structure was biased at VBE=0.8V
and VCE=1.8V. Also, it should be noted that fT and fmax for the fabricated devices were
extrapolated and frequencies from beyond 30GHz were not actually measured by
Bolognesi et al [2]. Also shown in Figure 3.8(b) is the simulated power gain versus
frequency from which we obtain an fmax of 295 GHz. This compares with the fmax of 300
GHz from the results by Bolognesi et al [2] for the same device, so there is good
agreement.
88
Figure 3.8(a) Frequency response of fabricated structure reported by Bolognesi et al. with
a 200 A0 thick base with a doping of 8x1019 /cm3 [2]
Figure 3.8(b) Frequency response of the simulated InP/GaAsSb/InP HBTs (•) current
gain, (X) unilateral power gain.
89
Figure 3.9(a) shows the variation of fT with DC biases (JC ) for various collectoremitter voltages VCE, as reported by Bolognesi et al. [2] for the fabricated device. A peak
fT of 300 GHz is obtained at JC=410 KA/cm2 for VCE = 1.8 V [2]. The cut-off frequency
goes through a maximum as function of JC because the base collector charging time τc
has a inverse dependence on the collector current. As a result, a transistor designed for
high frequency performance has to operate at high, but not necessarily excessive collector
current levels. At excessively large JC, the device performance degrades due to high
current effects (discussed below). Note that the peak fT increases with increasing VCE
since a larger VCE delays the fall-off at high current densities.
Figure 3.9(b) shows the evolution of fT with JC obtained for the similar, simulated
device as described in Figure 3.3, the primary difference being the use of a 0.5µm emitter
contact, while the fabricated structure had a 0.4µm emitter contact. The current density
was scaled using the emitter area of the simulated device to enable comparison with the
published results. While the simulated results overestimated the cut-off frequency at
lower current density, they realistically described the peak fT and its roll-off at high JC.
Similar to Figure 3.9(a), the peak fT increases with VCE and moves to a higher JC. A peak
fT of 344 GHz was achieved at a collector current density of 432 KA/cm2 for VCE = 1.8
V. It can be seen that even at low collector-emitter bias of 0.6 Volts, we are able to
achieve impressive high frequency performance of fT greater than 100 GHz. This low
VCE case corresponds to operating the transistor in saturation mode.
90
Figure 3.9(a) Evolution of fT with JC for the InP/GaAsSb DHBT with a base width of
200A0 and collector width of 2000 A0 for a VCE=0.4V to 1.8V as reported
by Bolognesi et al. [2].
Figure 3.9(b) Evolution of fT with JC for collector-emitter bias VCE = 0.4 to 1.8V for
simulated structure.
91
Figure 3.9 (c) Peak fT variation with VCE for simulated (•) and fabricated (s)
InP/GaAsSb/InP DHBTs.
Figure 3.9 (c) shows the plot of the peak fT as a function of JC versus VCE for both
the simulated and the fabricated structures. We can see that for both sets of results the fT
increases for increasing values of VCE and there is reasonable agreement between the two
sets of results. The excellent dynamic performance in saturation can be attributed to the
confinement of holes in the base because of the large valence band discontinuity ∆EV =
0.7–0.8 eV at the InP/GaAsSb interface at the base-collector junction, which prevents
hole injection from the P-type GaAsSb base into the collector when the base/collector
junction is forward biased [2].
92
The fmax characterization for the fabricated structure by Dvorak and Bolognesi et al.
[9] is shown in Figure 3.10(a) as a function of JC and VCE. This device has the same
structure for which the fT characterization was done earlier except for the 250 A0 base
was used [9]. The reported fmax reaches a peak of 300 GHz for a collector current density
of 250 KA/cm2 and VCE = 1.8 V. Figure 3.10(b) shows the variation of fmax with JC for
different base emitter voltages for the simulated structure with 200A0 base width. The
simulated fmax reaches peak value of 295 GHz at JC = 313 KA/cm2 for a collector bias of
1.8 Volts. The fall-off in fmax is related to that seen for fT and is predictable due to the
high current effects.
The responses of peak fmax as a function of JC to different collector bias VCE for the
fabricated and the simulated structure are illustrated in Figure 3.10 (c). The simulated
structure reaches a peak of 295 GHz for VCE = 1.8V, whereas, the fabricated structure has
a peak performance of 300 GHz at the same VCE. These simulation results are in excellent
agreement with the published results [2]. The increase in fmax at higher VCE biases is
normal, keeping with the fact that the collector-base capacitance decreases with
increasing VCE and fmax’s inverse dependence on Cjc.
93
Figure 3.10(a) fmax and fT dependence on JC for a 250 A0 base and 2000 A0 InP/GaAsSb
DHBT for various VCE biases [9]
Figure 3.10(b) Evolution of fmax vs collector current density JC for 200A0 bases and
2000A0 collector for the simulated InP/GaAsSb DHBT for various VCE.
94
Figure 3.10 (c) Reported fmax variation with collector-emitter bias VCE (•) and simulated
peak fmax values (? ) for a 4x11 µm2 emitter, 250 A0 base and 2000 A0
Collector [9]
3.3 High Current Effects
Although no classical base push out can occur in the InP/GaAsSb system due to the
hole confinement in the base region by the large valence band discontinuity ∆EV at the
InP/GaAsSb heterojunction, the onset of fT and fmax roll-offs seen in Fig 3.9 and Fig. 3.10
at very high JC are due to the band flattening in the collector [2]. However, this can be
offset to certain extent by operating the device at a highe r collector-base VCB and VCE
voltages. We can understand this trend by briefly analyzing the various transit time
components that contribute to the cut-off frequency fT . The cutoff frequency of the
transistor is related to the collector-emitter transit time τec by the equation [13]
95
fT =
1
,τ ec = τ e + τb + τsc + τc
2πτ ec
(3.1)
where, τec is the total HBT input response delay time, τe is the emitter charging time, τb is
the base transit time, τsc is the base-collector space charge transit time, and τc is the
collector charging time. The space-charge transit time, τsc, is the transit time for the
carriers to drift through the depletion region of the base-collector junction, quantitatively
given as in
τ sc =
X dep
(3.2)
2vsat
where Xdep is the base-collector depletion width where this assumes electron velocity
saturation. The emitter charging time τe is the time required to change the base potential
by charging up the capacitances through the differential base-emitter junction resistance,
τe =
C je
(3.3)
IC
where Cje is the emitter junction capacitance. The collector charging time τc is the time
required to charge up the base-collector junction capacitance, is given by,
τc =
C jc
(3.4)
IC
where Cjc is the collector junction capacitance. For JC corresponding to peak fT , the (τe +
τc) terms are small, so the τec term can be simplified as τec ≈ τb + τ sc. Now the dependence
of peak fT on VCE varies by the factor that dominates the remaining terms in the emittercollector transit time. The improvement in fT could be due to several things
1) τb may go down somewhat since the larger Xdep will make the neutral base
region slightly smaller.
96
2) If the space charge component τsc dominates the collector current charging
τc, then we would see a fall-off in fT with increasing collector-emitter
voltage. Since this is not the case, we could assume that the decrease in
collector capacitance reduces collector current charging time significantly to
offset any increase in τsc. This assumes that the collector region is fully
depleted. The conventional understanding is that peak fT is directly
proportional to VCE. An increase in VCE results in an increase in the basecollector depth Xdep, which reduces the collector junction capacitance,
leading to an increase in fT . For our device, the collector is fully depleted
even at zero bias because of the collector region is narrow (2000A0 ), so this
is not the explanation. The origin of fT increase with VCE is likely due to an
increase in the average electron velocity in the B-C space charge region.
This may also be related to the hot-electron effect described above.
3) Figure 3.11 from Bolognesi et al. [14] shows that
CBE is nearly constant
until the onset of high current effects at JC ≈ 3µA/(µm)2 corresponding to
the occurrence of peak fT .
97
Figure 3.11 High frequency and Cbe behavior of a 200 A0 base and 2000 A0
InP/GaAsSb/InP device [16].
3.4 Current Gain Collapse at High Frequency
Figures 3.12 and 3.13 show the variation of the AC current gain and unilateral power
gain, respectively, with collector current density. The gain values measured were the
maximum gains measured for VCE=1.8V at 2 GHz. The characterization was done at 2
GHz because this frequency is the upper limit of the band used in consumer applications
like mobile phones and automotive radars. The power gain reaches a peak of 34 dB at a
current density of 0.3 KA/cm2 before sharply degrading above 100 kA/cm2 . Similarly,
the AC current gain has a value of 34 dB that remains constant over several orders of
magnitude before falling off above 100 KA/cm2 .
98
Figure 3.12 Variation of current gain with collector current density for VCE=1.8 V at 2
GHz
Figure 3.13 Variation of maximum unilateral power gain with collector current density
for VCE=1.8 V at 2 GHz
99
The high current degradation in the type-II InP/GaAsSb DHBTs at high current
densities is not due to the conventional base push-out effect [15]. Base push-out does not
occur at the high current density because hole injection from the base into the collector is
blocked by the high valence band discontinuity (~0.78eV). As a consequence, a parasitic
barrier forms in the conduction band at the base-collector heterojunction (16, 17) that
impedes electron flow causing the collector current to saturate and the device gain and
speed to degrade. In brief, the origin of fall in current gain and the fT roll-off can be
described as follows:
1) The onset of fT roll-off at high collector current density is attributed to the collapse
of the electric field at the base-collector heterojunction as shown in Figure 3.14. The
‘critical current density’ at which the electric field collapses (and also at which fT reaches
its peak value) is given by [15]

2ε s (Vbc +Vbi ) 
J Crit = vs  qNC +

WC2


(3.5)
where NC is the collector doping level, WC is the collector thickness, vs is the average
electron velocity through the collector, Vbc is the base collector reverse bias, Vbi is the
collector junction built- in potential, q the electron charge and ε s is the permittivity of the
material. This equation shows that the current density which collapses the electric field at
the base-collector junction is linearly dependent on the base collector voltage Vbc. Figure
3.15 shows the dependence of the critical current density JC on Vbc for the simulated
device. The plot is reasonably described by the linear-like relation of 3.5, at least for
lower values of Vbe, suggesting that the onset of fT roll-off is associated with the collapse
of electric field. This has been experimentally confirmed by Bolognesi et al. [14, 15].
100
Complicating this phenomenon is the fact that because of the hole confinement in the
base due to the larger ∆EV at the base-collector junction and the excess electron build up
in the collector, at high current densities a charge dipole is induced which reverses the
electric field at the base-collector heterojunction which is seen in Figure 3.14.
Figure 3.14 Collapse of electric field and subsequent parasitic barrier formation in the
collector of InP/GaAsSb/InP DHBTs with Vbe varied from 0.6 V to 1.0 V
and VCE = 1.8V.
101
Figure 3.15 Critical current density for the onset of high current induced device
degradation versus based-collector voltage for the simulated and
calculated device behavior [15].
2) The hole and electron build up in the base-collector heterojunction is shown on
Figure 3.16 (a) and (b). This hole build up in the base causes the formation of a parasitic
barrier in the collector region of the InP/GaAsSb DHBT as shown in Figure 3.14 at
higher current densities after the electric field collapses. This barrier greatly reduces the
exit velocity of electrons leaving the base and leads to a drop in fT (15, 16, 17). The
parasitic barrier height rises with the current density as 133mV at JC = 550 kA/cm2 (see
Fig. 3.17). This barrier leads to electron charge storage in the base (see Fig 3.16(b)),
resulting in the reduction of the base exit velocity by a factor of ~ exp(-EB /K BT). These in
turn leads to a sharp increase in CBE as shown in Figure 3.13 and a drop in fT . The
measure of the parasitic barrier height in the conduction band for various values of JC is
plotted in Figure 3.17. The barrier does not occur at emitter-base biases Vbe up to 0.9V.
102
The effect can be partially offset by using higher doping levels in the collector [15].
However, the gains achieved by doping the collector higher are offset by considerations
of lower breakdown voltage at the junction and speed-related effects of the collector-base
capacitance. Although Bolognesi et al [15] explain that the high current degradation is
partly due to “Kirk- like effects”, in reality there is hole accumulation in the collector as
can be observed in Figure 3.16 (a), which is characteristic of the classical base-pushout or
Kirk effect. Therefore, the phenomenon here causing fall-off in the device performance is
a combination of parasitic barrier formation and the Kirk effects.
Figure 3.16(a) Hole concentration for low and high current operation of a 200 A0 base
and 2000 A0 collector simulated InP/GaAsSb/InP DHBT, ‘B’ and ‘C’
indicate the base-collector regions for VCE = 1.8V and for VBE from 0.6V to
1.1V.
103
Figure 3.16(b) Electron (b) concentration for low and high current operation of a 200 A0
base and 2000 A0 collector simulated InP/GaAsSb/InP DHBT, ‘B’ and ‘C’
indicate the base-collector regions, for VCE = 1.8V and for VBE from 0.6V
to 1.1V.
Figure 3.17 Conduction band barrier height versus collector current density for simulated
InP/GaAsSb structure given in Figure 3.3 for VCE =1.8 V.
104
3.5 Conclusion
In this chapter we have demonstrated reasonable agreement in performance of the
simulation results with the reported experimental results on the fabricated devices from
Bolognesi et al. [2, 3] for InP/GaAsSb DHBTs. The accuracy of the simulations depends
in part on the precision of the material properties adopted during the simulation. The high
frequency performance of the device matched closely the published results with the
simulation results being fT =344 GHz and fMAX=295GHz, with the published experimental
values of 300 GHz for fT and fMAX, respectively [2]. The variation of the simulated fT with
the collector current density agrees very well with the published values showing a fall-off
above 100 kA/cm2 . The current density for the peak fT was found to be 410 KA/cm2 for
the device reported by Bolognesi et al [2,3], whereas in our case it was 432 KA/cm2 . The
variation of the current gain and unilateral power gain with collector current density were
also along expected lines. The peak fT and fmax as a function of JC were examined versus
VCE and found to be in good agreement with the results reported for the experimental
devices. The reason for the fall off in device performance at high currents was shown to
be related to the formation of the parasitic barrier in the conduction band. Therefore, the
high current degradation is not due solely to the conventional Kirk (base pushout) effect,
but also due to the formation of a parasitic barrier in the conduction band of the collector.
The parasitic barrier height is a function of the collector current density, collector doping
and VCE.
Having verified the validity of the model of the InP/GaAsSb DHBT structure being
simulated, in the next chapter we investigate the optimization of the performance of the
device for high frequency operations. Also, we will briefly examine the physics behind
the factors affecting fT and fMAX. In summary, initial comparison of the model’s results
105
with the limited available experimental results shows good agreement so that use of the
model is appropriate for investigating epitaxial design for the device.
References:
[1] ATLAS User Manual, Vol. 1, Silvaco International, Santa Clara, CA, Feb’ 2000.
[2] C.R Bolognesi, M.W Dvorak, O.J Pitts & S.J Watkins, “300 GHz InP/GaAsSb/InP
Double HBTs with High Current Capability and BVCEO 6 V”, IEEE Electron Device
Letters, vol. 22, pp 361-364, 2001.
[3] C.R. Bolognesi, N. Matine, M.W. Dvorak, X.G. Xu, J.Hu and S.P. Watkins, “ NonBlocking Collector InP/GaAsSb/InP Double Heterojunction Bipolar Transistors with a
Staggered Lineup Base-Collector Junction”, IEEE Electron Device Lett., vol 20 pp 155157 , 1999.
[4] R. Teissier, J.L. Pelouard, F. Mollot, “Direct Measurement of Ballistic Electron
Distribution and Relaxation Length in InP-based Heterojunction Bipolar Transistors
using Ele ctroluminescence Spectroscopy”, Appl. Phys. Lett., Vol. 72, pp. 2730-2732,
1998.
[5] B. T. McDermott, E. R. Gertner, S. Pittman, C. W. Seabury, and M. F. Chang,
“Growth and Doping of GaAsSb via Metalorganic Chemical Vapor Deposition for InP
Heterojunction Bipolar Transistors,” Appl. Phys. Lett., vol. 68, pp. 1386–1388, 1996.
[6] R. Bhat, W-P. Hong, C. Caneau, M. A. Koza, C-K. Nguyen, and S. Goswami,
“InP/GaAsSb/InP and InP/GaAsSb/InGaAsP Double Heterojunction Bipolar Transistors
with a Carbon-doped Base Grown by Organo- metallic Chemical Vapor Deposition”,
Appl. Phys. Lett., vol 68, No (7), pp 985-987,1996.
106
[7] C.R. Bolognesi, N. Matine, M.W. Dvorak, X.G. Xu, J.Hu, S.P. Watkins, and M.L. W
Thewalt, “Nearly Ideal InP/GaAsSb/InP Double Heterojunction Transistors with
Ballistically Launched Collector Electrons”, Electronics Letters, vol. 34, no. 17, pp.
1700-1702, 1998.
[8] X. G. Xu, J. Hu, and S. P. Watkins N. Matine, M. W. Dvorak, and C. R. Bolognesi
“Metalorganic Vapor Phase Epitaxy of High-quality GaAs0.5Sb0.5 and its Application to
Heterostructure Bipolar Transistors”, Appl.Phys.Lett., vol. 74, pp. 776-778, 1999.
[9] M.W Dvorak, O.J. Pitts, S.P Watkins, C.R Bolognesi, “Abrupt Junction
InP/GaAsSb/InP HBTs with FT as high as 250 GHz and BVceo >6 V”, IEDM Tech Digest,
pp 178-181, 2000.
[10] R.D. Rajavel, T. Hussain, M.C. Montes, M.W. Sawins, S. Thomas III, and D.H.
Chow, “Molecular Beam Epitaxial Growth and Characterization of InP/GaAsSb/InP
Double Heterojunction Bipolar Transistors”, J. of Crystal Growth, vol. 251, pp. 848–851,
2003.
[11] J. W. Rodwell, M. Urteaga, T. Mathew, D. Scott, D. Mensa, Q. Lee, J. Guthrie, Y.
Etser, Suzanne C. Martin, R. P. Smith, S. Jaganathan, S. Krishnan, S.I. Long, R. Pullela,
B.Agarwal, U.Bhattacharya, L. Samoska, and M. Dahlstrom, “Submicron Scaling of
HBTs”, IEEE Trans. On Electron Devices, vol.48, pp 2606-2624, 2001.
[12] M .W Dvorak, T. Matine, C.R Bolognesi, “Design and Performance of
InP/GaAsSb/InP Double Heterojunction Bipolar Transistors” Journal of Vacuum Science
Technology A, vol. 18, pp 761-764, 2000.
[13] Liu, W.,“Handbook of III-V Heterojunction Bipolar Transistors”, John Wiley and
Sons Inc., New York, pp 26-27, 1998.
107
[14] C.R Bolognesi, M.W Dvorak, S.J Watkins, “InP/GaAsSb/InP Heterojunction
Bipolar Transistors”, IEDM Tech. Digest, pp. 343-351, 2002.
[15] C.R Bolognesi, M.W Dvorak, O.J Pitts, S.J Watkins, T.W Macelwee, “Investigation
of High Current Effects in Staggered Line- up InP/GaAsSb/InP Heterostructure Bipolar
Transistors”, IEDM Tech. Digest, pp 341-350, 2000.
[16] S. Tiwari and D. J. Frank, “Analysis of the Operation of GaAlAs/GaAs HBT’s,”
IEEE Trans. Electron Devices, vol. 36, pp. 2105–2121, 1989.
[17] S. Tiwari, “A New Effect at High Currents in Heterostructure Bipolar Transistor”,
IEEE Electron Device Letters, vol. 9, pp. 142-144, 1988.
108
Chapter IV
Optimization of InP/GaAsSb/InP HBTs
The basic modeling and simulation of the InP/GaAsSb/InP DHBTs was
discussed in the previous chapter. In this chapter, we build on the work done in earlier
chapters and optimize the InP/GaAsSb DHBT structure in terms of doping and epitaxial
layer thickness for better high frequency performance and current gain. The optimization
of the two parameters i.e., doping and layer thickness, is a challenging one, since
obtaining a better performance on one set of parameters, i.e. fT or fmax, doesn’t necessarily
mean optimum performance in terms of the other. We arrive at the best epitaxial design
for maximizing fT , fmax, power gain, and current gain by optimizing the conflicting effects
of varying the doping concentration and epitaxial layer widths.
In this chapter, we investigate the high frequency performance of the
InP/GaAsSb/InP DHBTs and briefly explain the various factors that affect fT and fmax.
Device structures with different epitaxial thickness and doping are simulated to arrive at
the optimum device for high frequency performance.
The low and high current
performances of the devices are examined as well as the effects of the operating
frequency. In addition, the effects of the velocity overshoot on high frequency
performance and the incorporation of it into the device model are elucidated. Finally, we
simulate the optimized device structure and present performance measures with improved
performance over the latest published results.
109
4.1 HBT Performance Parameters
In this section, we briefly summarize the parameters that characterize the high
frequency performance of the HBTs such as the cutoff frequency fT and maximum
oscillation frequency fmax and describe their relationship to the device’s structure. The
various factors that affect these parameters and the underlying physics are discussed. We
are interested in the above parameters because fT determines the switching speed of
digital circuits, whereas fmax is an important figure of merit in transistors designed for
power applications. Peak cut-off frequency is an important benchmark when HBTs are
used to design high-speed digital circuits. HBTs operating at high frequencies usually
operate at a high current density to obtain sufficient current gain and fT . However, for low
noise applications, such as LNAs in a wireless transceiver, lower current performance of
HBTs without excessively low gain and fT is critical. This is because the noise minima in
a HBT occur at low collector current densities. So it is essential that the HBTs have
sufficient gain and fT at low as well as high current densities.
4.1.1 AC Current Gain
The small signal current β ac is defined as the small signal collector current divided by
the small-signal base current, as given by (4.1). The small signals are nothing but AC
signals applied as input and measured at the output whose magnitude is very small when
compared to the DC operation point. The β ac is given as follows [1],
βac =
ic
βdc
=
ib 1 + jωβ dc (Cπ + C jc ) / gm
110
(4.1)
where ic is the small-signal collector current, ib the corresponding base current, β dc is the
DC gain of the transistor when no small signals are applied, Cp is the total input
capacitance, Cjc is the base-collector junction capacitance, gm is the transconductance of
the transistor and ω is the angular frequency of device operation. Clearly at high enough
frequencies, the AC current gain degrades due to the device’s internal capacitances.
4.1.2 Current Gain Cutoff Frequency (f T)
The cutoff frequency fT is defined as the frequency at which the AC current gain ßac
becomes unity. Also, the fT can be defined as the magnitude at which the forward current
gain h-parameter h21 reaches unity. However, it should be noted that the former definition
is tied to the applied collector-base voltage Vcb and more realistically represents the
performance of the transistor under different bias conditions. This definition is used in the
present work to extract the value of fT from the simulation runs. The cutoff frequency of
the transistor is related to the collector-emitter transit time by the equation [1]
fT =
1
,τ ec = τ e + τb + τsc + τc
2πτ ec
(4.2)
Where, τec is the total HBT input response delay time, τe is the emitter charging time,
τb is the base transit time, τsc is the space charge transit time, and τc is the collector
charging time. We will briefly discuss each of these transit times, and the weight of their
influence on the overall cutoff frequency. These transit times are affected by the various
capacitances and resistances of the transistor as shown in the equivalent small signal
circuit in Fig 4.1. [1]
111
Figure 4.1 Parameters affecting the high frequency performance of the HBT [1]
The emitter charging time τe is the time required to change the base potential by
charging up the capacitances through the differential base-emitter junction resistance,
τe =
ηkT
.(C je + C jc )
qI C
(4.3)
where, Cje and Cjc denote the junction capacitances for the base-emitter and basecollector junctions, respectively, η is the ideality factor for the collector current, IC is the
D.C collector current, and kT/q is the voltage equivalent of the temperature. We can see
from the above equation that the emitter charging time has an inverse dependence on the
collector current, as result of which the HBTs designed for high frequency operate at high
current levels. Also, the emitter charging time scales directly with capacitances Cje and
Cjc, meaning smaller device structures result in higher fT . These capacitances Cje and Cjc
also are related to the emitter and collector doping respectively, varying as the square
root of doping. In 4.1 Cje is contained in the total input capacitance Cπ and is usually
lower than Cjc because the collector junction area is usually larger than the emitter
junction area.
112
The base transit time τb is defined as the time required to discharge the excess
minority carriers in the base in the form of the collector current and is given as [1],
τb =
WB2
ηb .DnB
(4.4)
where WB is the width of the base region, DnB is the electron diffusion constant in the
base, ηb is a dimensionless parameter whose value is approximately 2, which depends on
the magnitude of the base quasi-electric field for compositional or dopant grading. This
transit time is important for PNP HBTs, since the low minority diffusion coefficient of
holes results in a significant base transit time. For the NPN HBTs, the base transit time
may be negligible when compared to the overall transit time. However, it becomes
significant when optimizing fT for high frequency operation since the peak fT occurs
when τec≈ τb+ τbc.
The space-charge transit time, τsc, is the transit time for the carriers to drift through the
depletion region of the base-collector junction, and is quantitatively given as [1]
τ sc =
X dep
(4.5)
2Vsat
Where Xdep is the thickness of the base-collector depletion region and vsat is the saturation
velocity of the electrons. When analyzing the transit times in a transistor, τsc is of
particular importance because it is frequently the largest contributor to the overall transit
time at peak fT . One of the reasons is that the collector is often the thickest part of the
transistor in order to maintain a reasonable breakdown voltage. Various schemes exist to
reduce τsc such as base-collector grading and band gap engineering. All these schemes
113
serve to keep the electric field below the critical level, so the electrons traveling through
the space-charge region exceed the saturation velocity vsat through a phenomenon known
as the velocity overshoot. In our case the electron velocity is established by the unique
band gap line up of the GaAsSb base and the InP collector, whereby the electron is
ballistically launched with a high energy into the collector. Therefore τsc can be
significantly reduced.
Finally, the collector charging time τc is the time required to charge up the basecollector junction capacitance, and is given by [1],
τ c = ( RE + RC )C jc
(4.6)
where RE and RC are the emitter and collector series resistances, respectively. If the HBT
is not designed properly, these resistances can significantly increase τc causing
degradation in device performance. The overall transit time can be summed up as follows
τ ec =
X
ηkT
WB2
.(C je + C jc ) +
+ dep + ( RE + RC )C jc
qI C
ηb .DnB 2vsat
(4.7)
We will examine in detail the effect of the various parameters in (4.7) on fT and fmax
while optimizing the different regions of the device structure.
4.1.3
Unilateral Power Gain and Maximum Frequency of Operation (fmax )
A transistor whose output is completely isolated from its input is said to be
unilateral and the process by which a lossless feedback network is added to the transistor
such that the overall two-port is unilateral is called unilateralization [1]. The unilateral
114
power gain of the transistor is the power gain after the transistor plus the lossless network
is made unilateral [1].
The maximum oscillation frequency is the frequency at which the unilateral power
gain of the transistor rolls-off to unity and it depends on the value of fT as [1]
fmax
=
fT
8π rbC jc
(4.8)
where rb is the base series resistance, Cjc is the collector junction capacitance and fT is the
cut-off frequency. So fmax rises with fT , but may have a different point of optimization for
a devices structure, for example base doping, than fmax.
4.2
Optimization of InP/GaAsSb/InP HBTs
The semiconductor industry has been able to make impressive advances in
technology, because it has been able to continuously improve the performance of its
devices. Faster and more efficient devices owe their existence to improvement in process
technology that has facilitated the fabrication of devices with ever-smaller dimensions.
For an III-V device to be more useful, maximizing its high frequency performance is a
key factor. With this perspective in mind, we proceed to optimize the device structure,
scaling the device’s dimension in the vertical and horizontal directions to maximize both
fT and fmax. With these primary objectives in sight, the device’s performance in terms of
the current and power gain as a function of the current density are also important. This is
particularly true for the kind of applications for which InP DHBTs will be used, i.e. in
LNAs and power amplifiers.
115
4.2.1 Optimization of the Base Layer
The base region of the transistor is the most important layer for the DHBT, in the
context that significant improvements in high frequency performance can be made by
efficient design of the base region. The fT of a transistor is affected by the transistor base
layer design mainly through the base transit time as given in (4.4). Considering this
quantitatively, τb is proportional to the square of WB. Therefore, maximization of fT calls
for reducing the base thickness towards zero. For zero base thickness, there is no base
region and contact, and so no bipolar transistor can be formed. As a result, from the fT
consideration alone, the goal is to make the base as thin as possible, keeping within the
epitaxial processing capabilities. However, decreasing the base thickness increases the
base resistance rb. This reduces fmax because of its direct dependence on the reciprocal of
the base resistance as given in (4.8). Therefore, optimization of the base layer involves a
compromise between maximizing fmax and fT . A balanced trade-off needs to be made
between the two parameters when deciding on the value of the base width.
Keeping all other design parameters constant as given in Table 3.3 in chapter 3, the
base width of the InP/GaAsSb/InP transistor was varied to study the effect on fT and fmax.
Figure 4.2(a) and 4.2(b) show the performance of the transistor in terms of the cut-off
frequency as a function of Vbe and JC, as the base width is varied from 10nm to 60nm for
a fixed doping of 4x1019 /cm3 . As we can see, the variation in fT is along expected lines,
going through a maximum as Vbe and JC increase. The peak fT achieved was 388 GHz at a
collector current density of 262 KA/cm2 and Vbe=0.92V for a base width of 30nm. As a
point of reference, Bolognesi et al [2] have reported a InP/GaAsSb DHBT with base
width as small as 20 nm with a fT of 300 GHz
116
Figure 4.2(a) fT Vs base-emitter voltage as a function of the base width for VCE=1.8V for
a fixed base doping of 4x1019 cm-3
Figure 4.2(b) ft vs Collector Current density as a function of base width for VCE=1.8V
and VBE from 0.6V to 1.07V for a fixed base doping of 4x1019 cm-3
117
Figure 4.2(c) and 4.2(d) shows the behavior of the fmax versus the base-emitter
voltage and collector current density, as the base width is varied. The peak value of fmax
rises as the base width is varied from 10nm to 60nm as shown in Figure 4.2(e). The initial
steep rise in fmax at smaller base widths (< 30 nm) is due to the fact that it is directly
related to fT as in (4.8). Hence, an increase in fT leads to a corresponding increase in fmax.
The peak fmax of 325 GHz observed here was achieved for a base width of 60 nm at
194.73 kA/cm2 .
Keeping in mind, the objective is the maximization of both fT and fmax, the base
width of 30nm serves as an excellent solution. The peak fT that can be achieved at this
base width is 388 GHz, whereas the fmax reaches a maximum of 320 GHz. Figure 4.2(e)
shows the variation of peak fT and fmax with base width. The fT actually dips for a base
width of 20nm. At lower base widths, the base resistance dominates, leading to a
decrease in fmax. It should be noted that other active layers have not yet been optimized.
118
Figure 4.2(c) fmax vs base-emitter voltage for various base widths for VCE=1.8V and VBE
from 0.6V to 1.07 Vo lts for a fixed base doping of 8x1019 cm-3
Figure 4.2(d) fmax vs collector current density for various base widths for VCE=1.8V and
VBE from 0.6V to 1.07 Volts for a fixed base doping of 8x1019 cm-3
119
Figure 4.2(e) Variation of peak fT and fmax with base width for a base doping of 8x1019
cm-3 , (+) Peak fT fmax from results by Bolognesi et al. [2] for similar device
structure.
The same epi-structure as before given in Table 3.3 is now investigated for the
effects of base doping on high frequency parameters. The base transit time is not a very
strong function of the base doping NB as given by the diffusion coefficients appearing in
τb [1],
DnB =
where µ
kT
µ
q
(4.9)
= µ(N) as given chapter 2. The diffusion coefficient in the base layer of the HBTs
saturates to a relatively low constant values at high doping levels. As a result, increasing
the doping has the advantage of decreasing the sheet resistance and at the same time
without subsequent increase in the base transit time. However, fT does increase somewhat
120
as the doping level gets higher as shown in Figure 4.3(c). This could be due to impurity
scattering in the base when it is doped to the material solubility levels. This is confirmed
by the simulations results for fT versus base doping shown in Figure 4.3(a). The peak fT
increases with doping and shifts to higher collector current density. This effect is
pronounced for doping of 3x1019 cm-3 , 7x1019 cm-3 and 1x1020 cm-3 . Similarly, fmax
increases with doping as predicted by (4.9) and is verified by the simulations as shown in
Figure 4.3(b). The peak fmax levels shift to lower current density as the doping is
increased. A doping of 7x1019 cm-3 is seen as optimum value for maximizing both fT and
fmax.
Figure 4.3(a) fT versus emitter-base voltage for various doping levels for VCE=1.8V for a
fixed base width of 20nm
121
Figure 4.3(b) fmax versus emitter-base voltage for various doping levels for VCE=1.8V for
a fixed base width of 20nm
Figure 4.3(c) Variation of peak fT and fmax with base doping for a fixed base width of
20nm, (+) indicates peak fT and fmax results from Bolognesi et al. [2] for
similar device structure.
122
4.2.2 Optimization of the Emitter Layer
Design of the emitter layer can be improved in a number of ways, such as by using a
graded or abrupt base-emitter heterojunction, by varying the layer thickness (XE) and
finally, by changing the doping level (N E). For the HBT under consideration, InPGaAsSb forms an abrupt heterojunction at the emitter-base region with a staggered band
gap line up. This bestows an advantage as previously discussed in chapter 1, by blocking
the hole back injection into the emitter from the base which improves the current gain.
Design of the emitter layer thickness is rather straightforward in the sense that it should
be thick enough to limit hole back injection and at the same time be able to keep the
emitter resistance RE within reasonable limits [1]. The impact of the emitter resistance on
τe is to increase τe and reduce both fT and fmax [1]. We can expect that the present
transistor would follow the same general trends, since the basic underlying physics
remains unchanged.
Figure 4.4(a) shows the simulation results for the effect of change in emitter width on
fT . The cut-off frequency shows some modest increase as the emitter width is increased.
Figure 4.4(b) shows the variation of fmax with emitter width. The increase in emitter width
increases the emitter transit time τe. Since τe constitutes a small proportion of the overall
transit time, the increase has minimal effects on fT and fmax. Figure 4.4(c) shows the
variation of peak fT and fmax with emitter width. The optimum emitter width based on the
simulation and experimental [2] results is chosen as 90nm.
123
Figure 4.4(a) Effect of emitter width variation on fT for VCE=1.8V for a fixed emitter
doping of 3x1017 cm-3 .
Figure 4.4(b) Effect of emitter width variation on fmax for VCE=1.8V for a fixed emitter
doping of 3x1017 cm-3 .
124
Figure 4.4(c) Variation of peak fT and fmax with emitter width for a fixed emitter doping
of 3x1017 /cm3 , (+) indicates peak fT and fmax results by Bolognesi et al. [2] for
similar device structure
Emitter doping plays a more significant role in the high frequency performance
of the device than emitter width. Emitter doping directly influences the base-emitter
junction capacitance Cje which appears in the fT equation in (4.3). Typically for a HBT
Cje >> Cjc, so at lower doping levels, Cje is lower and hence charges faster. Figure 4.5(a)
shows the effect of emitter doping on cut-off frequency as a function of collector current
JC. From a simple analysis of the graph we might infer that the lowest possible emitter
doping is desirable. However, at low emitter doping the transistor is susceptible to high
current effects. Hence, a higher doping is chosen so that the current density is reasonably
high and at the same time keeping τe low. From (4.8) we find that the fmax dependence of
on the emitter design is only through fT . Neither the base resistance nor the base-collector
125
capacitance is affected by variations in the emitter doping. Therefore, once the fT is
optimized for an emitter layer design, fmax is automatically optimized. The behavior of the
InP/GaAsSb/InP transistor was investigated for high frequency performance for various
values of emitter doping. Figure 4.5(b) shows the variation of fmax with emitter doping.
An emitter doping of 3x1017 /cm3 seems like a good value from the plot of peak fT and
fmax in Figure 4.5(c). However, using this value of doping in the final structure resulted in
high current degradation occurring at lower current densities than normal. The
simulations show that both fT and fmax are optimized for a emitter doping of 7x1017 cm-3 .
As discussed before, though the high frequency performance is better at the lower doping
levels, we settle upon a higher doping level to delay high current effects.
Figure 4.5(a) fT versus base-emitter voltage for various doping levels for VCE=1.8V for a
fixed emitter thickness of 700 A0
126
Figure 4.5(b) fmax versus base-emitter voltage for various doping levels for VCE=1.8V for
a fixed emitter length of 700 A0
Figure 4.5(c) Variation of peak fT and fmax with emitter doping for a fixed emitter width
of 700 A0 .
127
4.2.3
Collector Layer Optimization
The design of the collector layer is more complex when compared with the other two
layers, because the factors affecting its design are not only thickness and doping but also
the collector-emitter bias VCE. The collector depletion layer Xdep, controlled by VCE also
plays a major role in determining the high frequency performance of the HBT. The
design is further complicated by the fact that the time constants in the total transit time τec
have opposite dependencies on Xdep, and that depletion width is both a function of bias
voltage and current. However, the final decision boils down to the fact that whether we
need to optimize the fT , fmax performance or the collector breakdown voltage.
The choice of VCE directly influences the fT and fmax, in that an increase in VCE
increases Xdep, which in turn, diminishes the collector charging time τc and results in a
rapid increase in fT . Also, the space charge transit time τsc is directly proportional to Xdep.
So there is an optimum value of depletion width beyond which, the increase in τ sc more
than compensates for the decrease in τc and the cut-off frequency decreases as in Figure
4.7(c). However, fmax continues to increase because its Xdep dependency cancels out at
higher VCE bias. This increase is not indefinite and stops as soon as Xdep reaches the
collector width. So an optimum value of VCE would be to optimize both fT and fmax. For
InP/GaAsSb/InP HBTs the optimum VCE is 1.8V. These processes are illustrated in Fig
4.16 with reference to AlGaAs/GaAs HBTs [1]. The two time constants relating to the
collector design are given as
τ sc + τ c =
X dep
2vsat
+ ( RE + RC ).
128
Acε s
X dep
(4.10)
An interesting point to be noted here is that, the collector resistance RC is
dependent on the Xdep through the epitaxial resistance in the undepleted collector. So by
choosing a collector thickness equal to the depletion depth we can eliminate the portion
of collector resistance related to the undepleted collector. In view of the conflicting
effects of VCE on each of the transit time components in (4.10), we aim to minimize their
sum as a whole. As a rule of the thumb reducing the collector thickness, increases fT . We
cannot, however design a collector layer with the thinnest possible width, because for
many RF and high power applications, it is essential that the collector be thick enough to
ensure a high collector breakdown voltage. The fT and fmax simulation results for various
collector widths are shown in Figure 4.7(a) and 4.7(b). Figure 4.7(c) shows the variation
of peak fT and fmax with the collector width. Keeping in terms with the requirements
discussed above, a collector width of 0.2 micron is chosen as the optimum value.
Figure 4.6 Calculated collector depletion thickness, fT and fmax, as a function of VCE
129
Figure 4.7(a) fT vs base-emitter voltage for several collector widths for VCE=1.8V for a
fixed collector doping of 3x1016 /cm3
Figure 4.7(b) fmax vs base-emitter voltage for several collector widths for VCE=1.8V for a
fixed collector doping of 3x1016 /cm3
130
Figure 4.7(c) Variation of peak fT and fmax with collector width for a fixed collector
doping of 3x1016 /cm3
The collector region is usually doped lower than the base so that it can be fully
depleted for a given VCB. A good choice of NC can obtained from [1]
Nc =
2ε s (φcb + VCB )
2
qX C
(4.11)
This works out very well for maximizing fmax, because the collector junction
capacitance Cjc is directly proportional to the square root of collector doping. Hence a
lower collector doping ensures a higher fmax. However, there are two main disadvantages
to doping the collector at a lower value. Kirk effects tend to be pronounced at lower
collector doping because the effective base width increases at higher collector current
densities due to electric field reversal at the base-collector junction. This field reversal
can be delayed by higher doping until the higher collector current densities fully deplete
131
the collector layer.
The other disadvantage, as previously discussed would be the
lowering of the breakdown voltage, if lower doping is employed. At higher doping, there
would be more carriers to balance the field produced by a larger BVCEO. As we did with
all the design parameters we have to strike a compromise and pick a doping level that
ensure a high enough fmax as well as good breakdown voltages. From Figure 4.8(c) we see
that contrary to what we discussed fmax continues to increase with higher doping.
However, from (4.8) we see that any increase in Cjc is also cancelled by a corresponding
increase in fT . We can see from Figures 4.8(a) and 4.8(b) that for a doping of 2x1017 cm-3
both fmax and fT are jointly optimized. Also at this level of doping the current and power
gain is better than what could be achieved at a lower doping.
The design of collector layer is interesting in the sense that, once we determine the
desired Xdep for best high frequency performance, then XC can be set to the desired Xdep.
Also from the value of XC, the desired NC can be obtained from equation or through
simulations.
132
Figure 4.8(a) fT Vs Base emitter Voltage for various collector doping for a fixed collector
width of 2000A0
Figure 4.8(b) fmax Vs Base emitter voltage for various collector doping for a fixed
collector width of 2000A0
133
Figure 4.8(c) Variation of peak fT and fmax with collector doping for a fixed collector
width of 2000A0 .
4.3
Optimized Structure
The final InP/GaAsSb/InP HBT structure optimized for high frequency performance
is shown in Figure 4.9. This structure incorporates the best layer thickness and doping
concentration values as determined from the simulations discussed in the previous
sections. The changes to the transistor structure have been to the main active layers of the
transistor. The design values for the contact layers and the sub-collector are the same as
that of the original structure by Bolognesi et al [2]. The emitter and base layer thickness
have been inc reased to 900 A0 and 300 A0 , respectively. The base la yer doping remains
nearly the same at 7x1019 cm-3 vs 8x1019 cm-3 of Bolognesi et al. [2]. Both the emitter and
the collector doping have been increased. The collector doping is considerably more than
for the structure by Bolognesi et al. [2] with a doping of 3x1016 cm-3 . In order to enable
134
comparison of performance between the structures by Bolognesi et al. [2] at 2x1017 , the
bias values for the transistor has been kept at the same values. The structure of the
InP/GaAsSb DHBT is repeated here in Figure 4.9(b) for convenience from chapter 3. The
simulated layout of the schematic given below complete with the contacts is shown in
Figure 4.10. The Gummel characteristics are shown in Figures 4.11.
Figure 4.9 (a) Schematic of the Optimized InP/GaAsSb/InP HBT
Figure 4.9 (b) Schematic of the InP/GaAsSb/InP HBT structure by Bolognesi et al. [2]
135
Figure 4.10 Simulated Structure of Optimized InP/GaAsSb/InP HBT
Figure 4.11 Gummel-Poon simulations of optimized InP/GaAsSb/InP Structure
136
Figure 4.12 shows the frequency performance of the optimized structure at a Vbe and
VCE of 0.8 V and 1.8 V, respectively. The peak fT achieved was 440 GHz at 3.7 mA. The
AC current gain of 36 dB is closer to that of the original structure. As can be inferred
from the graph, we have achieved our optimization objective of increasing the high
frequency performance. Figure 4.13 shows the frequency performance of the optimized
structure at a Vbe and VCE of 0.8 V and 1.8 V respectively. The fmax performance followed
at 396 GHz at 2.62 mA. The performance parameters are summarized in Table 4.1.
The increase in fT is due to the cumulative effect of reduced collector and emitter
resistance resulting from increased collector and emitter doping. The fmax performance
has been enhanced due to the larger base width resulting in lower base resistance.
Figure 4.12 Frequency response of the optimized InP/GaAsSb/InP HBT for VCE = 1.8V
137
Figure 4.13 Frequency response of the optimized InP/GaAsSb/InP HBT for VCE = 1.8V
Table 4.1 Simulation results for Optimized InP/GaAsSb/InP structure.
Performance Parameter
Peak values
fT , IC
440 GHz, 3.7 mA
Fmax , IC
396 GHz, 2.62 mA
AC Gain, IC
34 dB, 0.118 mA
Power Gain, IC
32 dB, 0.48 mA
The evolution of fT with the collector current density for various collector-emitter
biases is shown in Figure 4.14(a) for the optimized structure. The general trend of the
138
curves is similar to the ones for the simulation of the original structure in Chapter 3 and
the published results [2]. A peak fT of 440 GHz was achieved at a collector current
density of 304.55 kA/cm2 for VCE = 1.8 V. The fT roll-off at higher current densities
around 300 kA/cm2 can be explained by considering the capacitance at the base-collector
junction. Cjc first dips with increasing current density and reaches a minimum value
corresponding to the peak fT bias occurring for the condition of zero electric field at the
base-collector junction. Further increases in the current density, reverses the electric field
at the base-collector junction, resulting in the formation of a small field induced
thermionic emission barrier. Even though the magnitude of this barrier EB is small, it has
a huge effect on the base charge storage. This reduces the effective base exit velocity by a
factor ~exp (-EB/KT) resulting in a sharp rise in Cjc and subsequently a drop in fT [3]. The
fmax performance vs the collector current density for various collector-emitter voltages is
shown in Figure 4.14(b). The fmax reaches a peak of 396 GHz at JC = 246 kA/cm2 for VCE
= 1.8V. fmax is dependent on VCE thru its effect on the depletion width Xdep. As the
collector-emitter bias is increased, the depletion width increases leading a drop in the
collector charging time τc.
139
Figure 4.14 (a) Evolution of fT with JC for various VCE from 0.8 to 1.8 Volts
Figure 4.14 (b) Evolution of fmax with JC for various VCE from 0.8 to 1.8 Volts
140
Figure 4.15 Maximum power and AC current Gain versus collector current density (l)
Current gain (n) Power gain for VCE = 1.8V
The above observations have interesting implications. The InP/GaAsSb/InP HBTs
reach their peak performance at zero electric fields at the base-collector junctions [3].
This suggests that InP/GaAsSb/InP HBTs would perform well even under low VCB
biases. Figure 4.15 shows the variation of the AC current gain and unilateral power gain
with collector current density. The gain values measured were the maximum gains
measured for VCE=1.8V at 2 GHz. The gains remain comparable to that of the original
structure discussed in section 3.3., even as we improved the high frequency performance.
Figure 4.16(a) and 4.16(b) compares the extracted peak fT and fmax values for the various
structures under consideration. The optimized structure shows substantial improvement
over that of the HBT fabricated by Bolognesi et al [2].
141
Figure 4.16(a) Peak fT variation with VCE for InP/GaAsSb/InP DHBT structure of
Bolognesi et al. [2] (g ), simulated fT for the same structure ( n) and peak fT
for the optimized device structure (o) given in Figure 4.9
Figure 4.16(b) Peak fmax variation with VCE for InP/GaAsSb/InP DHBT structure of
Bolognesi et al. [2] (g ), simulated fT for the same structure ( n) and peak fT
for the optimized device structure (o) given in Figure 4.9
142
4.4 Conclusions
Starting with the basic structure of the HBT suggested by Bolognesi et al. [2], the
HBT structure presented in the previous sections of this chapter has been optimized to
demonstrate improved fT and fmax performance. The thickness and doping concentration
of each layer of the active region of the transistor were investigated for increasing the fmax
and fT values. The optimized structure had a peak fT and fmax of 440 GHz and 396 GHz,
respectively. The peak current and power gain was 34 dB and 32 dB, respectively. The
performance improvement in the cut-off frequency was over 140 GHz above that for the
device structure by Bolognesi et al. [2]. However, we have to consider the fact that our
model over estimated the cut-off frequency by 44 GHz. The improvement in fmax
performance was 99 GHz over that of Bolognesi et al’s structure [2]. The improved
performance is mainly due the reduced resistances in the active layers of the device
resulting from higher doping used in the collector and emitter layers. The optimum values
were chosen without compromising other performance measures like the breakdown
voltage and gain.
Reference:
[1] Liu, W.,“Handbook of III-V Heterojunction Bipolar Transistors”, John Wiley and
Sons Inc., New York, pp 26-27, 1998.
[2] C.R Bolognesi, M.W Dvorak, O.J Pitts & S.J Watkins, “300 GHz InP/GaAsSb/InP
Double HBTs with High Current Capability and BVCEO 6 V”, IEEE Electron Device
Letters, Vol. 22, pp361-364, 2001.
[3] C.R Bolognesi, M.W Dvorak
& S.J Watkins, “InP/GaAsSb/InP Double
Heterojunction Bipolar Transistors”, Gallium Arsenide Integrated Circuit (GaAs IC)
Symposium, 2002, 24th Annual Technical Digest, pp265-268, 2002.
143
Chapter V
Conclusions and Future Work
5.1 Conclusions
In this work, we have investigated and simulated the performance of InP/GaAsSb/InP
Double Heterojunction Bipolar Transistors (DHBTs). The staggered bandgap line up
resulting from the use of GaAsSb as a base in the NPN InP DHBT bestows a huge
advantage in terms of removing the collector blocking effect commonly found in other
InP-based DHBTs and also in enhancing the collector breakdown voltage. The simulation
model for the transistor was developed, complete with its epitaxial structure, terminal
contacts, doping, and device physics models, along with the necessary biasing. The
material properties of GaAsSb were researched in detail, such as the band energy gap,
mobility, effective masses, carrier lifetime, and density of states and incorporated into the
device model used for simulation.
In order to validate the transistor simulation model, we initially compared the
simulation results with the reported experimental results of the fabricated devices from
Bolognesi et al. [1, 2] for InP/GaAsSb DHBTs. The simulated model had the same device
structure [1] to ensure accurate comparison of the results. The common-emitter
characteristics of the device were investigated. One of the unique features of this
transistor is its low turn-on voltage. The turn-on voltage of the simulated device matched
the published results with a turn-on voltage of 0.4V. For comparison of the commonemitter characteristics, the current values were properly scaled to reflect the difference in
the emitter area of the two devices. The high frequency performance of the device
matched closely the published results with the simulation results being fT =344 GHz and
144
fMAX=295GHz, in reasonable agreement with the published experimental values of 300
GHz for fT and fMAX, respectively [1]. The variation of the simulated fT with the collector
current density also agrees very well with the published values showing a fall-off above
100 kA/cm2 . The current density for the peak fT was found to be 410 KA/cm2 for the
device reported by Bolognesi et al [1,2], whereas in our case it was 432 KA/cm2 . The
peak fT and fmax as a function of JC were examined versus VCE and found to be in good
agreement with the results reported for the experimental devices. The origins of the falloff in the transistors performance at high currents were also investigated. The reason for
the fall off in device performance at high currents is due to the formation of the parasitic
barrier in the conduction band. Therefore, the high current degradation is not due solely
to the conventional Kirk (base pushout) effect, but also due to the formation of a parasitic
barrier in the conduction band of the collector. The parasitic barrier height is a function of
the collector current density, collector doping and the collector-emitter bias VCE. The
parasitic barrier formed is as large as 140 meV. Simulations also show that there is
significant hole accumulation in the collector at the higher base-emitter biases. The
parasitic barrier increases with VBE because the depletion electric field is opposite to the
barrier electric field. The forward bias decreases the depletion field leading to a increase
in the parasitic barrier height.
Once we validated the transistor model, the HBT structure was optimized to
demonstrate improved fT and fmax performance. The thickness and doping concentration
of each layer of the active region of the transistor were investigated. The optimized
structure had a thicker base layer at 30 nm and higher emitter doping of 7x1017 /cm3 . The
collector was also doped somewhat higher at 2x1017 /cm3 . The optimized structure had a
145
peak fT and fmax of 440 GHz and 396 GHz, respectively. The peak current and power gain
was 34 dB and 32 dB, respectively. The performance improvement in the cut-off
frequency was over 140 GHz above that for the device structure reported by Bolognesi et
al. [1]. However, we have to consider the fact that our model over estimated the cut-off
frequency for the original structure by 44 GHz. The improvement in fmax performance for
the optimized structure was 99 GHz over that of the original structure by Bolognesi et al.
[1]. The improved performance is mainly due the reduced resistances in the active layers
of the device resulting from highe r doping used in the collector and emitter layers and a
wider base width. The optimum values were chosen without compromising other
performance measures like the breakdown voltage and gain.
The InP/GaAsSb/InP transistors have a number of advantages as elucidated in earlier
chapters, ranging from easy integration with optical transceivers to the simplicity of their
fabrication. These advantages make it worthwhile to aggressively pursue the
development of these devices in spite of stiff competition from other technologies like
SiGe. Also, the low noise performance and the high linearity of the devices over a wide
range of frequencies make these devices attractive in high growth markets like cellular
base stations and multi-band cellular phones. [3]
5.2 Future Work
In this work, we have established the basics for the modeling and simulation of the
InP/GaAsSb/InP transistor. Other InP-based transistors [4] have been aggressively scaled
and have shown impressive performances in terms of high frequency performance.
However, the current device is only moderately scaled and hence there is still scope for
146
further performance enhancement. In addition, the simplicity of the device fabrication
with no complicated doping or grading schemes at the collector junction makes it very
attractive for use in a production system. The performance of a pnp InP/GaAsSb DHBT
could also be investigated for use in a complimentary configuration for uses in digital
applications. The high current degradation follows a unique phenomenon, in that it’s not
entirely due to base out or the formation of parasitic barrier but a combination of the
above to factors. Therefore, the main thrust of future investigations would be to analyze
the performance fall off at high currents in terms of doping and the biases.
Reference:
[1] C.R Bolognesi, M.W Dvorak, O.J Pitts & S.J Watkins, “300 GHz InP/GaAsSb/InP
Double HBTs with High Current Capability and BVCEO 6 V”, IEEE Electron Device
Letters, vol. 22, pp 361-364, 2001.
[2] C.R. Bolognesi, N. Matine, M.W. Dvorak, X.G. Xu, J.Hu and S.P. Watkins, “ NonBlocking Collector InP/GaAsSb/InP Double Heterojunction Bipolar Transistors with a
Staggered Lineup Base-Collector Junction”, IEEE Electron Device Lett., vol 20 pp 155157 , 1999.
[3] M. Inerfield, W. Skones, S. Nelson, D. Ching, P. Cheng, and C. Wong, “High
Dynamic Range InP HBT Delta-Sigma Analog-to-Digital Converters”, IEEE J. of SolidState Circuits, Vol. 38, pp 1524-1532, Sept 2003.
[4] J. W. Rodwell, M. Urteaga, T. Mathew, D. Scott, D. Mensa, Q. Lee, J. Guthrie, Y.
Etser, Suzanne C. Martin, R. P. Smith, S. Jaganathan, S. Krishnan, S.I. Long, R. Pullela,
147
B.Agarwal, U.Bhattacharya, L. Samoska, and M. Dahlstrom, “Submicron Scaling of
HBTs”, IEEE Trans. On Electron Devices, vol.48, pp 2606-2624, 2001.
148
Appendix A
Run file for Simulation of InP/GaAsSb/InP DHBT
go atlas
title Emitter-up InP/GaSbAs/InP HBT device simulation (August 2003)
#
# SECTION 1: Mesh specification
#
mesh space.mult=1.0
#
x.mesh loc=2.3 spac=0.1
x.mesh loc=3.0 spac=0.1
x.mesh loc=3.5 spac=0.1
x.mesh loc=4.0 spac=0.1
#
y.mesh loc=0.00 spac=0.03
y.mesh loc=0.18 spac=0.01
y.mesh loc=0.25 spac=0.02
y.mesh loc=0.30 spac=0.02
y.mesh loc=0.37 spac=0.02
y.mesh loc=0.40 spac=0.005
y.mesh loc=0.45 spac=0.005
y.mesh loc=0.64 spac=0.01
y.mesh loc=0.69 spac=0.01
# SECTION 2:
#
region num=1
region num=2
region num=3
region num=4
region num=5
x.comp=0.49
region num=6
region num=7
x.comp=0.53
Structure definition
material=air
material=InGaAs
material=InP
material=InP
material=GaSbAs
x.min=2.3
x.min=3.5
x.min=3.5
x.min=3.5
x.min=2.9
x.max=4.0
x.max=4.0
x.max=4.0
x.max=4.0
x.max=4.0
y.min=0.0
y.min=0.18
y.min=0.28
y.min=0.33
y.min=0.42
y.max=0.69
y.max=0.28
y.max=0.33
y.max=0.42
y.max=0.44
material=InP
material=InGaAs
x.min=2.9 x.max=4.0 y.min=0.44 y.max=0.64
x.min=2.3 x.max=4.0 y.min=0.64 y.max=0.69
#
elec num=1 name=emitter x.min=3.5 x.max=4.0 y.min=0.16 y.max=0.18
elec num=2 name=base x.min=2.9 x.max=3.4 y.min=0.40 y.max=0.42
elec num=3 name=collector x.min=2.3 x.max=2.8 y.min=0.62 y.max=0.64
CONTACT NAME=emitter CON.RESIST=5e-8
CONTACT NAME=base
CON.RESIST=2e-7
CONTACT NAME=collector CON.RESIST=5e-8
#
doping uniform region=2 n.type conc=1.0e19
doping uniform region=3 n.type conc=3.0e19
doping uniform region=4 n.type conc=3.0e17
149
doping uniform region=5 p.type conc=4.0e19
doping uniform region=6 n.type conc=3.0e16
doping uniform region=7 n.type conc=1.0e19
#
# SECTION 3: Set models and define material parameters
##
material material=GaSbAs eg300=0.72 nc300=2.3875e17 nv300=4.6456e18
affinity=4.19 permittivity=14.4
material material=InP eg300=1.35 nc300=5.7e17 nv300=1.1e19
affinity=4.38 permittivity=12.35
material material=InGaAs eg300=0.75 nv300=7.7e18 nc300=2.1e17
affinity=4.5 permittivity=13.88
# Emitter Contact n+ InGaAs region
material region=2 taun0=5.0e-9 taup0=1.0e-9 vsatn=2.5e7 vsatp=7.7e6
#Emitter Cap n+ InP region
material region=3 taun0=1e-10 taup0=1e-11 vsatn=2.0e7 vsatp=1e6
# Emitter
n- InP region
material region=4 taun0=1.0e-7 taup0=1.0e-8
vsatn=2.0e7 vsatp=1e6
# Base
P+ GaSbAs region
material material=GaSbAs taun0=1.005e-7 taup0=1.533e-6 taurel.el=0.48e11 taumob.el=0.3e-10 vsatn=2.0e8 vsatp=6.8e7
# Subcollector n InP region
material region=6 taun0=1.0e-8 taup0=1.0e-9
vsatn=2.0e7 vsatp=1e6
# Collector n+ InGaAs region
material region=7 taun0=5.0e-9 taup0=1.0e-9 vsatn=2.5e7 vsatp=7.7e6
#Setting Mobility Values
mobility material=InP analytic.n mu1n.caug=300 mu2n.caugh=4917
ncritn.caugh=6.4e17 deltan.caugh=0.46
mobility material=InP analytic.p mu1p.caug=20 mu2p.caugh=151
ncritn.caugh=7.4e17 deltap.caugh=0.96
mobility material=GaSbAs analytic.n mu1n.caug=574 mu2n.caugh=750
ncritn.caugh=1.8190e17 deltan.caugh=1.057
mobility material=GaSbAs analytic.p mu1p.caug=20 mu2p.caugh=60
ncritn.caugh=7.935e18 deltap.caugh=0.45244
mobility material=InGaAs analytic.n mu1n.caug=3372 mu2n.caugh=11599
ncritn.caugh=8.9e16 deltan.caugh=0.76
mobility material=InGaAs analytic.p mu1p.caug=75 mu2p.caugh=331
ncritn.caugh=1.0e18 deltap.caugh=1.37
150
#Setting Models
models consrh hcte.el fldmob conmob analytic evsatmod=1 temperature=300
fermidirac print
output con.band val.band
solve init
save outf=newhbtecap.str
tonyplot newhbtecap.str -set newhbtecap.set
# SECTION 4: Initial solution and collector bias ramp
method
newton trap autonr
output e.velocity
solve prev
solve v3=0.01 ac freq=1e6 direct
solve v3=0.025 vstep=0.025 electr=3 nstep=2
solve v3=0.1
vstep=0.05
electr=3 nstep=10
solve v3=0.65
vstep=0.05 electr=3 nstep=23
## Calculate Gummel plot
# 1 - emitter
2 - base
3 - collector
log outf=200basehbt_dcgain_90.log
method newton trap
solve
solve
solve
solve
save
v2=0.01 ac freq=1e6 direct
v2=0.025 vstep=0.025 electr=2 nstep=2 ac freq=1e6 direct
v2=0.1
vstep=0.1
electr=2 nstep=5 ac freq=1e6 direct
v2=0.65
vstep=0.05 electr=2 nstep=5 ac freq=1e6 direct
outf=originalhbt_90.str
tonyplot
tonyplot
originalhbt_90.str
200basehbt_dcgain_90.log
#
# Frequency domain AC analysis up to 100 GHz
#
log outf=200basecorrected_90.log s.param gains inport=base
outport=emitter width=50
load inf=originalhbt_90.str master.in
151
#
solve previous ac freq=1 direct
solve ac freq=10 fstep=10 mult.f nfstep=8 direct
solve
solve
solve
solve
ac
ac
ac
ac
freq=2e9 direct
freq=5e9 direct
freq=1e10 direct
freq=2e10 fstep=2e10 nfstep=23 direct
#
# AC current gain versus frequency
#
tonyplot 200basecorrected_90.log -set hbtex06_4_log.set
quit
152