EECE488: Analog CMOS Integrated Circuit Design
Set 7
Opamp Design
References: “Analog Integrated Circuit Design” by D. Johns and K. Martin
and “Design of Analog CMOS Integrated Circuits” by B. Razavi
All figures in this set of slides are taken from the above books
Shahriar Mirabbasi
Department of Electrical and Computer Engineering
University of British Columbia
shahriar@ece.ubc.ca
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EECE488 Set 7 - Opamp Design
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General Considerations
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Gain
Small-signal bandwidth
Large-signal performance
Output swing
Input common-mode range
Linearity
Noise/offset
Supply rejection
EECE488 Set 7 - Opamp Design
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1
One-Stage Op Amps
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EECE488 Set 7 - Opamp Design
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One-Stage Op Amp in Unity Gain
Configuration
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2
Cascode Op Amps
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Unity Gain One Stage Cascode
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3
Folded Cascode Op Amps
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Folded Cascode Stages
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Folded Cascode (cont.)
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Folded Cascode (cont.)
| Av |≈ gm1 {[(gm 3 + gmb3 )ro3 (ro1 || ro5 )]||[(gm 7 + gmb 7 )ro7 ro9 ]}
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Telescopic versus Folded Cascode
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Example Folded-Cascode Op Amp
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Single-Ended Output Cascode Op Amps
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EECE488 Set 7 - Opamp Design
Triple Cascode
Av app. (gmro)3/2
Limited Output Swing
Complex biasing
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Output Impedance Enhancement
Rout = A1 g m 2 ro 2 ro1
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Gain Boosting in Cascode Stage
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Differential Gain Boosting
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Differential Gain Boosting
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Differential Gain Boosting
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Two-Stage Op Amps
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Single-Ended Output Two-Stage Op Amp
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EECE488 Set 7 - Opamp Design
Two-Stage CMOS Opamp
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Popular opamp design approach
A good example to review many important design concepts
Output buffer is typically used to drive resistive loads
For capacitive loads (typical case in CMOS) buffer is not
required.
Cc
V in
A1
Differential
input stage
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– A2
Second
gain stage
EECE488 Set 7 - Opamp Design
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V out
Output
buffer
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Two-Stage CMOS Opamp Example
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Gain of the Opamp
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First Stage
Differential to single-ended
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Second Stage
Common-source stage
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Output buffer is not required when driving capacitive loads
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Gain of the Opamp
Third Stage
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Source follower
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Typical gain: between 0.7 to1
Note: go=1/ro and GL=1/RL
gmb is body-effect conductance (is zero if source can be tied to
substrate)
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EECE488 Set 7 - Opamp Design
Frequency Response
Q5
Vbias
300
vin+
Q1
300
vin–
Q2
300
v1
CC
v2
A3 ≅ 1
150
vout
i = g m1 vin
150
Q3
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A3
–A2
Ceq = CC ( 1 + A 2 )
Q4
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Frequency Response
Simplifying assumptions:
• CC dominates
• Ignore Q16 for the time being (it is used for lead compensation)
Miller effect results in
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At midband frequencies
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Frequency Response
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Overall gain (assuming A3 ≈1)
which results in a unity-gain frequency of
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Note: ωta is directly proportional to gm1 and inversely
proportional to CC.
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Frequency Response
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First-order model
20 log ( A1 A 2 )
– 20 dB/decade
Gain
(dB)
ω ta ≅ g m 1 ⁄ CC
Freq
0
ω ta
ωp 1
(log)
ωp 1
0
Freq
ω ta
Phase
(log)
(degrees)
– 90
– 180
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EECE488 Set 7 - Opamp Design
Slew Rate
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Maximum rate of output change when input signal is large.
Q5
Vbias
300
vin+
Q1
300
vin–
Q2
300
v1
CC
v2
A3 ≅ 1
–A2
150
Q3
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vout
i = g m1 vin
150
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A3
Q4
All the bias current of Q5 goes either into Q1 or Q2.
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Slew Rate
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Slew Rate
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Normally, the designer has not much control over ωta
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Slew-rate can be increased by increasing Veff1
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This is one of the reasons for using p-channel input stage:
higher slew-rate
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Systematic Offset Voltage
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To ensure inherent (systematic) offset voltage does not exist,
nominal current through Q7 should equal to that of Q6 when the
differential input is zero.
Q5
VDD
300
Vbias
Q6
300
I b ia s
Q1
Vin –
Q2
300
Vin +
300
Vo ut
300
150
150
Q3
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Q4
VSS
Q7
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Systematic Offset Voltage
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Avoid systematic offset by choosing:
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Found by noting
and
then setting
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N-Channel versus P-Channel Input Stage
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Complimentary opamp can be designed with an n-channel input
differential pair and p-channel second-stage
• Overall gain would be roughly the same in both designs
P-channel Advantages
• Higher slew-rate: for fixed bias current, Veff is larger (assuming
similar widths used for maximum gain)
• Higher frequency of operation: higher transconductance of
second stage which results in higher unity-gain frequency
• Lower 1/f noise: holes less likely to be trapped; p-channel
transistors have lower 1/f noise
• N-channel source follower is preferable (less voltage drop and
higher gm)
N-channel Advantage
• Lower thermal noise — thermal noise is lowered by high
transconductance of first stage
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EECE488 Set 7 - Opamp Design
Feedback and Opamp Compensation
Y
H (s)
(s) =
X
1 + βH (s)
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Feedback systems may oscillate
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The following two are the oscillation conditions:
| β H ( jω ) |= 1
∠β H ( jω ) = −180
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Stable and Unstable Systems
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Time-domain response of a feedback system
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One-pole system
H ( s) =
Y
( s) =
X
A0
1+ s
ω0
A0
1 + βA0
s
1+
ω 0 (1 + βA0 )
S p = −ω 0 (1 + β A0 )
Bode plot of the Loop gain
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Multi-pole system
0.1ω p 2 > 10ω p1
Bode plot of the Loop gain
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Phase Margin
-20 dB/decade
Loop Gain
(dB)
20 log (LG (j ω))
0
ωt
ωp 1
Freq
(log)
GM
(gain margin)
ωp 1
Phase
ωt
Freq
(log)
0
Loop Gain
(degrees)
–90
–180
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PM
(phase margin)
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Phase Margin
β H ( ω1 ) = 1× e − j175
Y
11.5
(s) =
X
β
Closed loop frequency response
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Phase Margin (Cont.)
PM = 180 + ∠βH ( ωGX )
Phase Margin = 45°
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Phase Margin (Cont.)
Phase Margin = 45°
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Phase Margin (Cont.)
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At PM = 60o results in a small overshoot in the step response.
If we increase PM, the system will be more stable but the time
response slows down.
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Frequency Compensation
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Push phase crossing point out
Push gain crossing point in
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Telescopic Opamp (single-ended) -example
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Compensation (Cont.)
• Assume we need a phase margin of 45o (usually
inadequate) and other non-dominant poles are at high
frequency.
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Compensation of a two-stage opamp
Miller Effect
f pE =
Ceq = CE + (1+ Av 2 )CC
1
2πRout [CE + (1+ Av 2 )CC ]
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EECE488 Set 7 - Opamp Design
Compensating Two-Stage Opamps
Q5
Vbias1
300
Q1
300
Q2
300
Vin-
Q6
VDD
Vin+
300
Vout2
Vbias2
Q16
Cc
300
150
150
Q3
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Q4
EECE488 Set 7 - Opamp Design
Q7
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Compensating Two-Stage Opamps
v
gm1 v
in
R1
1
C1
RC
CC
g
v
m7 1
R
2
C2
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Q16 has VDS16 = 0 therefore it is hard in the triode region.
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Small signal analysis: without RC, a right-half plane zero occurs
and worsens the phase-margin.
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Compensating Two-Stage Opamps
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Using RC (through Q16) places zero at
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Zero moved to left-half plane to aid compensation
Good practical choice is
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satisfied by letting
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Design Procedure
Design example: Find CC with RC=0 for a 55o phase margin
– Arbitrarily choose C’C=1pF and set RC=0
– Using SPICE, find frequency ωt where a –125° phase shift
exists, define gain as A’
– Choose new CC so ωt becomes unity-gain frequency of the
loop gain, resulting in a 55o phase margin.
Achieved by setting CC=CCA’
– Might need to iterate on CC a couple of times using SPICE
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Design Procedure
Next: Choose RC according to
– Increasing ωt by about 20 percent, leaves zero near final ωt
– Check that gain continues to decrease at frequencies above the
new ωt
Next: If phase margin is not adequate, increase CC while leaving
RC constant.
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Design Procedure
Next: Replace RC by a transistor
SPICE can be used for iteration to fine-tune the device
dimensions and optimize the phase margin.
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Process and Temperature Independence
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Can show non-dominant pole is roughly given by
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Recall zero given by
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If RC tracks inverse of gm7 then zero will track ωp2:
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Process and Temperature Independence
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Need to ensure Veff16/Veff7 is
temperature variations
Q11
Vbias
Q12
independent of process and
Q6
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300
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V
a
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CC
Q16
Q13
300
Vb
V
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Q7
b
First set Veff13=Veff7 which makes Va=Vb
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Process and Temperature Independence
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Stable Transconductance Biasing
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Stable Transconductance Biasing
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Transconductance of Q13 (to the first order) is determined by
geometric ratios only.
Independent of power-supply voltages, process parameters,
temperature, etc.
For special case (W/L)15=4(W/L)13
gm13=1/RB
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Note that high-temperature will decrease mobility and hence
increase effective gate-source voltages.
Roughly 25% increase for 100 degree increase
Requires a start-up circuit (might have all 0 currents)
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