1
1
2
3
1
3
2
ABSTRACT
A novel technique for implementing class AB differential input stages is proposed. It is well suited for low voltage operation, and can be applied to single-stage or two-stage
OTAs in continuous-time or sampled-data systems. In order to illustrate this approach a novel OTA is presented, combining the input stage proposed and local commonmode feedback with two resistors to obtain high slew rate and very low static power consumption. Measurement results from a 0.5voltages of r
P m CMOS implementation with supply
1 V show a slew rate of 50 V/ P s for an 80-pF load capacitance, and a static power consumption of only
120 P W. Silicon area for this OTA is 0.024 mm
2
.
is modest. At the same time, dynamic currents are automatically boosted when a large input signal is applied, with peak current amplitude well above the quiescent current level.
This paper proposes a novel principle for the design of class AB input stages, which leads to large dynamic currents and is compatible with low-voltage and micropower operation. As an application example, it will be employed in the implementation of a high-performance class AB OTA circuit suited for low-voltage and very low power operation, with rail-to-rail output swing and small, non-slew rate limited, settling time. To this end, the novel input stage is used in combination with a local commonmode feedback (LCMFB) technique [2]. LCMFB improves the Gain-Bandwidth product (GB) and provides additional dynamic current boosting. For this reason, the resulting topology can be coined as “super class AB”
OTA.
1. INTRODUCTION
Operational Transconductance Amplifiers (OTAs) are versatile building blocks widely employed for implementing switched capacitor (SC) and switched opamp filters, sample and hold stages, and data converter circuits [1]. Desired performance characteristics of this block are fast settling response, wide bandwidth, and large slew rate. Reliability issues in modern fine line technologies and extended battery lifetime in wireless applications impose additional constraints in terms of low voltage operation and very low power consumption.
These requirements are difficult to achieve with conventional class A configurations. In these topologies slew rate (SR) is limited by the quiescent bias current and it’s difficult to maintain dynamic performance with reduced power dissipation. Also reduction of supply voltage often leads to a decrease in dynamic range and reduced gain in single-stage topologies, as cascoded configurations become impractical.
A well-know alternative to face this stringent scenario is the use of class AB configurations [1]. These circuits have well-controlled quiescent currents, which can be made very low so that the static power dissipation
2. CLASS AB INPUT STAGES
2.1. Conventional Class AB Input Stage
The circuit diagram of Fig. 1a shows a popular class AB input stage [3]-[4]. It consists of two matched transistors
M
1
and M
2
cross-coupled by two constant voltage sources.
Under quiescent conditions, the two gate voltages of the transistors are maintained at the same common-mode level. In this case V
SG1
Q
=V
SG2
Q
=V
B
, so that both transistors carry equal quiescent currents, controlled by V
B
. If V
B
is slightly larger than | V
TH
| , very low standby currents can be achieved. If for instance V
INP
decreases, voltage at the source of M
1 decreases by the same amount, whereas the source voltage of M
2
is kept constant. Therefore, current through M
2
will increase whereas current through M
1
will decrease. The maximum swing of these currents is independent of the quiescent currents, and depends on the current driving capability of the level shifter implementation in Fig. 1a. A high performance level shifter is required to drive the sources of transistors M
1 and M
2
.
;‹,((( , ,6&$6

V
INM
V
B
V
B
M
1
I
1
(a)
I
2
M
2
V
INP
V
INM
V
CM
+V
B
I
1
M
1
V
B
V
CM
CMS
M
2
I
2
(c)
V
INP
V
INM
V
MAX
+V
B
I
1
M
1
V
B
V
MAX
WTA
M
2
I
2
(e)
V
INP
M
5
M
6
M
5
M
6
V
INM
I
BIAS
M
3
M
1
I
1
(b)
I
2
M
4
M
2
I
BIAS
V
INP
V
INM
I
1
M
4
M
1
V
CM
I
BIAS
M
3
M
2
I
2
V
INP
V
INM
I
BIAS
(d)
M
3
M
1
I
1
(f)
I
2
M
4
M
2
I
BIAS
V
INP
Figure 1. Different class AB input stages.
Using two floating batteries. (a) Basic diagram (b) Implementation
Using a floating battery and a common-mode sensing circuit. (c) Basic diagram (d) Implementation
Using a floating battery and a winner-take-all circuit. (e) Basic diagram (f) Implementation
The sources of these transistors are low-impedance nodes, especially when a large transconductance gain is required.
Moreover, this level shifting cell must source a large current when the circuit is charging or discharging a large load capacitance. It also has to be simple due to noise and supply voltage restrictions.
A very good choice is shown in Fig. 1b [3]-[4]. Each level shifter is built using two transistors ( M
3
, M
5
or M
4
,
M
6
) and a current source. We name these level shifters
“Flipped Voltage Followers” [5]. They have a very low output resistance (typically tens of Ohms) and fulfill all the aforementioned requirements.
2.2. Class AB Pseudo-Differential Pair
An alternative approach proposed by some of the authors in [6] is shown in Fig. 1c. A single floating battery is used to set the voltage at the common source node of the input differential amplifier. This voltage is the common-mode voltage of the inputs shifted by V
B
. Under quiescent conditions, the input voltages are identical and equal to the input common-mode voltage, hence V
SG1
Q
=V
SG2
Q
=V
B
.
Therefore, V
B controls the quiescent currents in a similar way to that of Fig. 1a. When a differential input is applied, an unbalance in the drain current is produced that is not limited by the quiescent current, and depends on the sourcing capability of the level shifter. A very efficient implementation of this level shifter is the FVF, and the resulting circuit is shown in Fig. 1d. The FVF bias current will be the quiescent current of the input differential pair, assuming that transistors M
1
, M
2
, and M
3
are matched.
A circuit is required to sense the common-mode input voltage (labeled as CMS in Fig. 1c) and to apply it to the gate of transistor M
3
, in order to make quiescent currents independent on the input common-mode voltage and to obtain a high Common-Mode Rejection Ratio (CMRR).
Some proposals for this circuit can be found in [6].
Typically, they are based on a capacitive divider in SC circuits or either resistive dividers or differential pairs in continuous-time applications.
2.3. Proposed WTA Class AB Input Stage
Fig. 1e shows a basic diagram of the alternative class AB input stage that we propose in this paper. It is based on a modification of the idea in Fig. 1c, where a Winner-Take-
All (WTA) circuit generating the maximum value of the input voltages replaces the common-mode sensing circuit.
Therefore, the voltage at the common source node is the maximum input voltage shifted by the constant voltage
V
B
. Under quiescent conditions, input voltages are equal so that the maximum value corresponds to the commonmode input voltage. Thus V
SG1
Q
=V
SG2
Q
=V
B
, and quiescent currents are well controlled and determined by V
B
like in
,

the circuit of Fig. 1c. The difference arises under dynamic conditions. If for instance the input voltage V
INP
decreases so that it is lower that V
INN
, the common source node tracks the maximum input voltage, i.e., V
INN
, and not the common-mode voltage of the inputs. Therefore, the resulting V
SG2
is larger than for the same input in Fig. 1c, and therefore a larger transient current level is obtained.
Fig. 1f shows a very efficient implementation of the
WTA circuit. The basic cell employed is again a FVF cell, thus benefiting from its large sourcing capability and low voltage operation. Two FVFs, formed by transistors M
3
-
M
5
and M
4
-M
6 and two current sources, are employed to generate a very low impedance node at the common source of M
1
and M
2
. In this case, again V
B
=V
SG3
Q
and the quiescent current is I
BIAS
, assuming that transistors M
1
, M
2
, and M
3
, M
4
are matched. Upon application of a large differential voltage, dynamic currents I
1
and I
2
are generated, where one of them may be significantly larger than I
BIAS
. Another advantage of the circuit in Fig. 1f is that transistors are not driven in the cutoff region when an input signal is applied.
3. APPLICATION EXAMPLE
In order to illustrate the operation of the input stage of
Fig. 1f, it is applied to build a low-voltage OTA, shown in
Fig. 2. The configuration proposed can be regarded as the result of two modifications to a conventional single-stage
OTA. The first one is the replacement for the class A input differential pair by the class AB input stage of Fig.
1f. The second modification is the use of local commonmode feedback [2] by the inclusion of two identical resistors R
1 and R
2
.
For common-mode inputs, current flowing through resistors R
1 and R
2 is zero, and voltages at nodes A and B are identical. Under these conditions quiescent currents are I
BIAS
. However, when a differential input signal appears, a signal current I
R
flows through both resistors, leading to a differential complementary voltage variation at nodes A and B. The maximum value of the voltage swings at nodes A and B will be given (assuming unitygain mirrors) by ' V
GS
MAX
= R
1,2
I
MAX
.
Current I
MAX
is the maximum dynamic current through the resistors, which is determined by the input stage. This voltage swing may lead to a large current swing in the NMOS transistors M
9
,
M
12
. Therefore, it leads to class AB operation in these transistors in addition to that provided by the input stage.
This combined effect leads to a higher slew-rate enhancement, and we can refer to the OTA as “super class
AB” to reflect this feature. Moreover, LCMFB also provides increased GB product [2]. Resistors can be implemented using MOS transistors in triode mode, saving area and allowing resistance adjustment.
M
7
M
9
M
5
M
3
I
BIAS
V
INM
A
M
10
M
1
R
1
M
6
M
4
I
BIAS
R
2
M
2
B
M
11
V
INP
M
8
V
OUT
M
12
Fig. 2. OTA with WTA class AB input
4. MEASUREMENT RESULTS
The OTA of Fig. 2 was fabricated in a 0.5P m CMOS
N-well process available through MOSIS, with NMOS and PMOS threshold voltages of about 0.67V and –0.96V, respectively. Fig. 3 shows a microphotograph of the circuit. Resistors R
1
, R
2
had values of 10 k : , and were implemented using interdigitized strips of non-silicided polysilicon. Die area occupied (excluding bonding pads) is 185 P m x 130 P m. The aspect ratios of transistors M
1
-M
4 were 50/1, and those of transistors M
5
M
8
were 240/1.
Transistors M
9
-M
12 were 120/1. Supply voltages were r 1V, and bias current I
BIAS
was set to 10 P A.
In order to measure the transient response the OTA was connected in unity gain configuration, and a 100-kHz square wave was applied at the input. The output terminal was connected directly to a bonding pad and no external buffer was employed, so the load capacitance corresponds to the pad, breadboard and test probe capacitance
(approximately 80 pF). Fig. 4 shows in solid line the output of the proposed OTA and the output of a conventional class A single-stage symmetrical OTA, fabricated in the same prototype for comparison purposes.
The input corresponds to the dotted waveform, almost undistinguishable from the output of the proposed OTA.
Supply voltage, load, and quiescent currents were identical for both OTAs. The slew rate obtained using the
OTA with the proposed input stage is 50 V/ P s, which represents an increase of more than 100 as compared to the conventional single-stage OTA with the same quiescent currents. Measurements on an OTA like the one in Fig. 2 but using a conventional class A differential pair showed a slew rate increase factor of 3 due to the LCMFB provided by R
1
and R
2
[2]. Therefore, the main contribution to the increase in slew rate is due to the novel class AB input stage proposed here. The static power consumption is only slightly increased (120 P W for the proposed OTA versus 80 P W for the conventional singlestage OTA). The measured 1% settling time (rising edge)
,

of the proposed OTA is 110 ns, whereas that of the conventional OTA is 3.1 P s. The measured unity gain bandwidth of the OTA of Fig. 2 is 650 kHz, and only 200 kHz for the conventional single-stage OTA with the same quiescent currents and load capacitance. The measured
THD of the OTA of Fig. 2 for a 100-kHz, 0.9-V peak-topeak input sinusoid was 0.7%. The noise level measured at 100 kHz was –132.5 dBV rms
/ Hz , almost like that of the conventional OTA. Table I summarizes the main performance parameters measured for the OTA of Fig. 2 in unity gain configuration and the corresponding values for the class A symmetrical OTA.
Although supply voltages of r 1 V were selected to have an input range of 1 V, measurements using supply voltages down to r 0.6 V were also performed, showing correct operation. However, in this case the input range available decreases by the same amount as the supply voltage does.
5. CONCLUSIONS
A novel technique for implementation of CMOS class AB differential input stages, based on the use of Winner-
Take-All circuits, has been presented. It leads to a significant increase in slew rate and fast settling, maintaining low noise and very low static power consumption. Measurement results of a class AB OTA using this technique confirm these benefits. This technique can find application in low-voltage low-power switched capacitor circuits and in buffers for testing mixed-signal circuits.
6. REFERENCES
[1] K. de Langen, J.H. Huijsing, “Compact low-voltage powerefficient operational amplifier cells for VLSI,” IEEE J. Solid
State Cir., vol. 33, no. 10, pp. 1482-1496, Oct. 1998.
[2] J. Ramirez-Angulo and M. Holmes, “Simple technique using local CMFB to enhance slew rate and bandwidth of onestage CMOS op-amps,” Electron. Letters , vol. 38, no. 23, pp. 1409-1411, Nov. 2002.
[3] J. Ramirez-Angulo, M. Deyong, and W.J. Adams,
“Applications of composite BiCMOS transistors,” Electron.
Letters , vol. 27, no. 24, pp. 2236-2238, Nov. 1991.
[4] V. Peluso, P. Vancorenland, M. Steyaert, and W. Sansen,
“900mV differential class AB OTA for switched opamp applications,” Electron. Letters , vol. 33, no. 17, pp. 1455-
1456, Aug. 1997.
[5] J. Ramirez-Angulo, R.G. Carvajal, A. Torralba, J. Galan, A.
P. Vega-Leal, and J. Tombs “The Flipped Voltage Follower:
A useful cell for low-voltage low-power circuit design,” in
Proc.
ISCAS 2002 , Scottsdale, AZ, pp. II 615-618, May 2002
[6] J. Ramirez-Angulo, R.G. Carvajal, A.Torralba, and C. Nieva,
“A new class AB differential input stage for implementation of low-voltage high slew rate op-amps and linear transconductors,” in Proc. ISCAS 2001 , Sydney, Australia, pp. I 671-674, May 2001.
P
Fig. 3. Microphotograph of the OTA of Fig. 2
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
0
Input
Output, class A
OTA
5
Output, class AB WTA OTA
10 15
Time (us)
20 25
Fig. 4. Measured transient response
30
T ABLE I. M EASURED P ARAMETERS OF THE OTAs (80-pF load)
SR+ (V/
Parameter
P s)
SR- (V/ P s)
1% Settling time (ns)
GB (kHz)
THD @ 0.9V
pp
, 100 kHz
(%)
Noise level @100 kHz
(dBVrms/ — Hz)
Static power ( P W)
Area (mm
2
)
Proposed
OTA
50
-42
110
650
0.7
-132.5
120
0.024
Class A
OTA
0.35
-0.4
3100
200
1
-133
80
0.011
,