DISS.ETHNo. 13463
An Industrial CMOS
Process Family for
Integrated Silicon
XL/11 k3 VyxVk3
A thesis submitted to the
SWISS FEDERAL INSTITUTE OF TECHNOLOGY ZURICH
for the
Doctor
of
degree
of
Natural Sciences
presented by
Thomas Müller
Dipl. Phys. Universität
Konstanz, Germany
Born April 12, 1965
in
Dresden, Germany
accepted
on
(he recommendation of
Prof. Dr. H. Balles,
Dr. G.
Kissinger,
supervisor
co-examiner
Dr. O. Brand, co-examiner
1999
Contents
Abstract
I
Zusammenfassung
3
Introduction: Silicon Microsensors
5
5
LI
Status and
1.2
Silicon Microsensor Fabrication
1.3
Smart Silicon Sensors
1.4
IC Process
1.5
Major Results
12
1.6
Outline of the Thesis
13
Perspectives
Technologies
6
8
9
Technologies
Adaptation of CMOS for Anisotropic Etching
with
2.1
Electrochemical Etch-Stop
Wafer Contact Network for the
Application
(ECE)
of the
16
Electrochemical Potentials
22
of the Wafer Back
2.2
Preparation
2.3
Implementation
of the
15
Adaptive Steps
into the Production Flow
26
MlCROMACHlNING
29
Using ECE
for
Micromachining Using
3.1
Setup
3.2
Micromachining
of
29
ECE
Fully CMOS Processed Wafers
34
37
Fabricated Devices
4.1
Silicon
37
4.2
N-well Based Island Structures
Diaphragms
41
4.2.1
Thermal Isolation of Circuits
4.2.2
Soft Contacts for
Improved
N-well Structure
41
Edges
44
Contents
Manufacturability and Yield
49
5.1
Function of Contact Network
49
5.2
Stress of Dielectric
53
5.3
Design
5.4
Polymer Coatings
Layers
Rules
54
57
Compatibility Issues Between Sensor-
and
IC
Device Technology
63
6.1
Quality
6.2
Nncleation and Growth of
6.3
Influence of Bulk
6.3.1
of Wet Etched Cavi ti es in Processed CMOS Wafers
Crystal
Back Mask
of
64
Oxygen Precipitates
Defects
Underetching
the
on
and
Quality
67
of Etched Cavities 74
Roughness
{111} Side-Walls
77
6.3.2
Generation of Bulk Microdefccts
6.3.3
Correlation Between Bulk
During
CMOS
Processing
Crystal Defects and Defects
in
Side-Walls
6.3.4
81
Morphology
of Craters in
{111} Side-Walls of Etched
Cavities
6.4
6.5
83
6.3.5
Analysis
6.3.6
Conclusive Remarks
External
of
Gettering
Anisotropically
Etched
(Quality
{100} Silicon Surfaces
of Wet Etched
Cavities)
for Wafers with Reduced Interstitial
6.4.1
Polysilicon
6.4.2
Back Side
6.4.3
Conclusive Remarks (External
Influence of
78
Oxygen
Back Sides
Concentration
88
90
93
Damages
Doping
87
99
on
Gettering)
104
Anisotropic Etching
105
Summary and Outlook
107
References
109
Acknowledgments
121
List
123
of
Abbreviations
Curriculum Vitae
125
/tlJjS 1 MAC 1
An industrial fabrication
technology
for
CMOS-integrated
silicon microscnsors
To this
end, commercial 2 pm and 0.8 pm CMOS device
technologies of Austria Mikro Systeme International AG, Unterpremstätten, Aus¬
developed.
has been
tria
were
adapted
anisotropic etching
adaptive
tact
prepare for
to
of silicon with
process steps include
post-processing micromachining using wet
an electrochemical etch-stop. The developed
the formation of
(1)
a
contact
network and
a con¬
application of the electrochemical potentials to the sensor struc¬
(2) the planari/ation of the wafer back, and (3) the deposition of the etch
on wafer back. Only standard submicron resolution photolithography and
field for the
tures,
mask
deposition steps
of advanced
CMOS
processing were used. Therefore, the
method can be applied to IC device technologies irrespective of their minimum
feature size or the wafer diameter used. Implementation into, e.g., 0.25 pm
device technologies processed on 200 mm wafers is possible with only minor
changes.
integrated microsystems were fabricated using the adapted CMOS pro¬
cesses and micromachining, e.g., ultrasonic sensors, force sensors for atomic
force microscopy co-integrated with fully differential low noise amplifiers, and
Several
chemical
A
new
sensor
systems for the detection of volatile organic compounds.
silicon wafer
oxygen and external
cesses.
tion
It
was
starting
material with reduced concentration of interstitial
gettering
found that bulk
strongly degrade
the
has been introduced for the
crystal
quality
defects
generated
adapted
CMOS pro¬
due to oxygen
of structures obtained
by
wet
precipita¬
anisotropic
etching. The reduction of the initial concentation of interstitial oxygen in the
wafer starting material from around 8-1017cmT3 to 6.0 6.9-1017cmT3 led to a
strongly improved quality of the fabricated structures due to low bulk crystal
defect generation.
-
Since wafer material with reduced
density
of defects has low internal
gettering
capability,
gettering
gettering capability of polysilicon back sides and mechanical damages at the wafer back were
investigated at
various stages of CMOS processes by monitoring the density of crystal defects at
the wafer back. Only crystal defects resulting from a hard mechanical damage
external
was
evaluated. The
1
Abstract
were
result,
of 6.0
found to be stable and
a
-
silicon wafer
6.9-10
starting
crrf° and
a
gettcring-active during
material with
hard mechanical
an
2
processing.
As
a
interstitial oxygen concentration
damage
cation of CMOS-integrated silicon microsensors
CMOS
was
using
the
employed
for the fabri¬
developed technology.
Zusammenfassung
In dieser Arbeit wird eine modifizierte CMOS Prozessfamilie
im Rahmen einer
Nachprozessierung
stellt werden können. Als
anisotropes
sem
integrierte
Fabrikationstcchnologic für die
Nassätzen mit einem elektrochemischen
Mikroscnsoren
herge¬
Mikrosensorcn wurde
Ätzstop eingesetzt.
Zweck wurde eine 2 (um und eine 0.8 pm CMOS
Mikro
von
der Wafer
mit der
vorgestellt
Technologie
Systeme International AG, Unterpremstätten, Österreich um
Zu die¬
der Austria
eine Reihe
Fabrikationsschritten erweitert. Die zusätzlichen Schritte umfassen (l) die
Herstellung
eines leitenden Netzwerkes auf den Wafern für die
den elektrochemischen
Ätzstop notwendigen Potentiale, (2)
Kontaktfeldes auf den Wafern für die elektrische
die
Verteilung
der für
Herstellung
Kontaktierung
eines
der Wafer wäh¬
Ätzens und (3) das chemische Polieren der Rückseite der Wafer sowie
das Abscheiden einer Siliziumnitridschicht als Ätzmaske. Um die Kompatibilität
rend des
der zusätzlichen Schritte mit anderen
Prozesstechnologien und die Prozessierbarkeit auf anderen Waferdurchmessern zu gewährleisten, wurden ausschliesslich
Standard Submikrometer-Photolithographie und -Depositionsschritte verwendet.
Eine Reihe von integrierten Mikrosensorcn und -Systemen wurde mit der entwikkelten
Sensorprozesstechnologie hergestellt, u.a. Ultraschallsensorcn, integrierte
Kraftsensoren für Rasterkraftmikroskope und chemische Sensorsysteine zur
Detektion leicht flüchtiger Gase.
Ebenfalls im Rahmen dieser Arbeit wurde ein
für die
Sensorprozesstechnologie
tung, dass
nass
sehr schlechter
gefunden,
die
entwickelt.
geätzte Strukturen
m
CMOS
neues
Silizium Wafer Startmaterial
Grundlage dafür war
prozessierten! Wafer
geometrischer Qualität sind. Als Ursache
die Beobach¬
Material
von
wurden Kristalldcfekte
Sauerstoffausscheidungen im Inneren der Wafer während der
Hochtempcraturschritte der Prozesse erzeugt werden. In IC Prozessen werden
Sauerstoffausscheidungen und Kristalldcfekte zum Gehern von Verunreinigun¬
an
gen benutzt. Eine
Sauerstoffgchalten
ten
Untersuchung
der
von
Wafern mit verschiedenen
in CMOS Prozessen
Sauerstoffkonzentration
Qualität
des Verhaltens
von
6.0-
ergab, dass Material mit einer reduzier¬
6.9-10l7cnfJ zu einer stark verbesserte
geätzten Strukturen führt. Da dieses Material
Defektdichte aufweist, ist die interne
Getterwirkung
stark
eine
geringe
abgeschwächt.
Darauf¬
aber
nur
hin wurden verschiedene Methoden des externen Getterns mit
Polysilizium-
3
Zusammenfassung
schichten
auf
der
Rückseite
der
Waler
(kontrolliertes Beschädigen der Rückseite
führen)
kung
untersucht. Bei diesen
Dichte
bleibt nach den
von
Wafer,
um
Damages
Kristall defekte einzu¬
Untersuchungen zeigte sich,
chung
für die
6.0
-
getteraktiven Defekten
Hochtemperaturschritten
starken mechanischen
4
der
mechanischen
mit
class die GetierWir¬
bei beiden Methoden im Verlauf der CMOS Prozesse stark nachlässt. Eine
signifikante
von
und
Damage.
Als
6.9-10
der Rückseite der Wafer
der Prozesse
Ergebnis
Sensorprozesstechnologie
an
nur
wurden in
Wafer mit einer
cirf° und einem harten mechanischen
ver¬
auf Wafern mit einem
Folge
dieser Untersu¬
Sauerstoffspezifikation
Damage eingesetzt.
1 Introduction: Silicon Microsensors
Introduction: Silicon
1
Microsensors
Status and
1.1
Perspectives
The world market for micro system
technology (MST) products
grow from $14 billion in 1996 to $38 billion in 2002 [1]. A
this market is held
In modern
by
sensors
automobiles,
a
for automotive
variety
of
is
employed
comfort for driver and passengers. Accelerometers
pretensioners [2].
ment around
counter
a
skirt, such
sensors
position
as
realized in the Electronic
to ensure
safely
and
used to detect crashes
or
and scat-belt
detect critical vehicle
move¬
transmission and brakes to
Stability Program (ESP)
under
development. Firing of
prevented using signals from these sensors.
a
passenger
suspension,
accelerometers
systems, such
are
employed to
initiate engine,
are
To enhance comfort for the occupants,
Low-g
share of
of Rob¬
for scat occupancy detection, child seat detection and out of
instants is
terns, active
to
[3]. Other safety applications using passive infrared and ultra¬
detection of
dangerous
significant
deployment of airbags
sensors are
its vertical axis and
ert Bosch GmbH
sonic
Yaw rate
expected
applications.
sensors
the roll-over of the vehicle and initiate the
is
as
and
parking
new
features, such
aid systems
were
as car
the
airbags
navigation
in
sys
introduced in the 90's.
employed in electrically controlled active suspension
Body Control (ABC) [4]. ABC compensates for the pitch
are
Active
and roll
during accelerating, braking or cornering of the vehicle by adjusting
damping rate of the shock absorbers. Ultrasonic transmitter/receiver systems
used for the measurement of the distance to
an
obstacle in
parking
the
are
aid systems
[5].
An advanced
microprocessor
controlled
engine management [6J requires sensors
to determine the state of the engine. Manifold absolute pressure (MAP) sensors
allow for the measurement of the partial vacuum in the intake manifold. Their
signal is used to detect the air mass flow into the engine in order to optimize fuel
5
1.2 Silicon Microsensor Fabrication
combustion. As
applied
are
In the
near
to
Technologies
part of exhaust gas catalytic
a
adjust
future,
a
the air/fuel ratio to
an
18,9]
systems, oxygen
will be
required
projects
like the
sensors
and ambitious
Highway System (AHS) [10].
Furthermore, monitoring of cabin air quality using chemical
detection of various gases, such
nals from these
sensors
of the air
damper flap
Car and
car
applications
can
supply
subsystem
fabrication
ing techniques
can
increasing
ment in
arc
are
substituting
1.2
sensors
initiate, e.g., automatic closing of the
of the vehicle
during
drive
Silicon microsensors
sensors
based
on
silicon
can
[11,12].
for the
sensors
meet
these
require¬
Silicon microsensor fabrication
measure¬
micromachining technology. Examples
crash-sensing [13], active suspension
sensors
using
a
technologies
use
rate sensors
are
vibrating cylinder [17].
Silicon Microsensor Fabrication
processing,
tunnel
a
[15,16]. Moreover, micromachincd yaw
conventional yaw rate
such
through
used for acceleration and pressure
micromachincd accelerometers for
[14], and MAP
increasing importance. Sig¬
technologies similar to intergrated circuit manufactur¬
to high volume production at low cost per device. Today,
share of the
automobiles
exhaust gas is of
be used to
mentioned above.
lead
as
for the
sensors
manufactures seek small and low-cost
ments. Sensor
an
sensors
value [7j.
optimum
of advanced distance
large quantity
for vehicle collision-avoidance systems
Automated
converter
Technologies
fabrication steps
common
in IC-
deposition, photolithography, and etching of thin films. In
addition, a number of specialized micromachining techniques have been devel¬
oped. They can generally be divided in micromachining at or close to the surface
of a silicon wafer or micromachining in the bulk of a silicon wafer.
In surlace
create the
above
to
or
as
micromachining, patterning of a grown or deposited layer is used to
sensing structure. In the case of a movable mechanical sensor, layers
underneath the micromechanical
free the
sensing
structure
layer
are
removed
(sacrificial layers)
[18].
Micromachining in the bulk offers the possibility to create three-dimensional sin¬
gle-crystal silicon microstructures for microsensor applications [19]. Especially
for mechanical sensors, single crystal silicon offers excellent material properties
120]. Bulk micromachining is usually performed by anisotropic or isotropic etch-
1 Introduction: Silicon Microsensors
ing reaching
into the interior of the wafer.
wafer front side
Wet
an
Fig.
common
bulk
with electrochemical
Silicon
1.1 shows
a
etdi-stop
micromachining technologies
electrochemical
lowing).
may be started either from the
the wafer back.
anisotropic etching
One of the
with
or
Etching
etch-stop
diaphragms for
at
p-n
junction (referred
sensors
pressure
schematic view of
Silicon
a
a
is wet
pressure
can
sensor
anisotropic etching
to
as
ECE in the fol¬
be fabricated this way.
fabricated
using
ECE. ECE
diaphragm (n-type epitaxial layer)
a#»wii»''*«tiw»Ä
P-doped
substrate
Pressure
Etched
cavity
P-N
Back mask
Fig.
(111) crystal
Cross-sectional
1.1:
pressure
cavity is
etch-stop
face
schematic
view
chip (pressure applied
sensor
created
of
a
bulk
micromachined
from the back of the
chip).
The
anisotropic etching with an electrochemical
at the p-n junction. (The deflection of the diaphragm due to
pressure is usually measured using piezoresistors located close to the
edge of the diaphragm).
is based
on
by
junction
the fact that the etch rate of silicon in aqueous
be influenced
by
a
potential
tion in silicon offers the
strongly
high
wet
between silicon and the
possibility
reduced etch rate while
to
keep
leaving
etching
the n-typc
etching
a
can
solution. A p-n
junc¬
potential
with
zone
the p-t>pe silicon at
etch rate. This way, the p-type material under
solutions
at a
potential with a
n-type layer can be seleca
7
1.3 Smart Silicon Sensors
tively
removed
resulting
in
diaphragm with the thickness of the n-type layer
[22,23]. During fabrication of a piezoresistive silicon pressure sensor, ECE is
commonly applied at the p-n junction between a n-type epitaxial layer and a
p-doped substrate wafer. After fabricating the necessary sensor components on
the wafer front, such as the implantation and the diffusion of the piezorcsistors, a
masking layer is deposited on the wafer back. The masking layer is structured by
double-sided photolithography and reactive ion etching (RIE) or wet etching
resulting in rectangular openings. Deep cavities arc etched in the wafer starting at
the mask openings. Common anisotropic etchants, such as potassium hydroxide
(KOH) or tctramethyl ammonium hydroxide (TMAH) solutions arc used. Etch¬
ing is automatically stopped at the lower surface of the n-type epitaxial layer.
Furthermore, single crystal silicon exhibits a strongly reduced etch rate in (111)
crystal direction in wet anisotropic etchants [211. Thus, all cavities have the form
of a truncated pyramid bound by 4 (11 l)-oriented crystal faces and one (lOO)-oriented crystal face.
a
Smart Silicon Sensors
1.3
A silicon
sensor
is
usually regarded
'smart1
(or integrated) when circuits for
amplification, compensation, and trimming of the raw sensor signal are co-inte¬
grated with the sensing structure on a single silicon chip [24]. This concept has
been demonstrated for pressure
lar
IC
in
sensors
already
in the late 70's
[25]. Today, bipo¬
with ECE are routinely employed for
technologies
high-volume fabrication of MAP sensors [26.27]. Other silicon sensors fabri¬
cated using this technology include, e.g., a piezoresistive acceleromcter [28].
combination
Compared to bipolar technologies, CMOS offers additional features for smart
sensors: complex logical circuits for signal conditioning, such as
digital signal
processors (DSP), analog/digital converters (ADC, DAC), microprocessor cores,
and memory
pressure
on
sensors
chip
can
based
be
on
co-integrated
smart
ECE
The
early 90's [29,30]. A
presented in 1995 [31].
instrumentation
amplifiers
and DAC's.
DSP and nonvolatile memory
recently 132].
8
sensing
CMOS technology and ECE
late 80's and
was
with the
for
structure.
were
Integrated
introduced in the
CMOS accelerometer fabricated
on-chip circuitry
Integration
compensation
of
a
of the
sensor
pressure
sensor
and calibration
using
includes
was
with
a
shown
1 Introduction: Silicon Microsensors
The
features of CMOS make the
special
opment of
chemical
concepts. As
new sensor
sensors are
subject
to
sible commercialization of the
thesis
was
focused
commercially
1.4
on
the
IC Process
The results
presented
example,
an
very attractive for the devel¬
electronic
noses
based
on
smart
extensive research [33]. In order to allow for pos¬
developed
integration
available CMOS
technology
sensor
of ECE
as a
systems, the work towards this
versatile
technology
sensor
into
technologies.
Technologies
in this thesis
the author and Austria Mikro
based
are
Systeme
on
the close collaboration between
International AG,
Unterpremslättcn, Aus¬
tria (AMSiAG) within the joint research project AMSYST funded by the Swiss
Priority Program Micro und Nano System Technology (MINAST) 134]. A num¬
ber of research
projects at the Physical Electronics Laboratory (PEL) were based
on the developed sensor technology, such as the MINAST projects PROXYST
(development of ultrasound based proximity sensors), FAMOS (development of
integrated force sensors for atomic force microscopes), and NOSE (development
of microsensors for the detection of volatile
technologies
The process
following.
Further details
technologies
boron-doped
of AMSiAG used
arc
Czochralski
wafers
were
of interstitial oxygen
organic compounds
during
this thesis
in
are
air).
described in the
available in
(CZ)
[35]. As starting material for all process
100 mm diameter, 525 pm thick,
grown,
used.
By part,
wafers with reduced initial concentration
used in order to
improve
the surface
quality of micromachined structures (see Chapter 6.3). In some cases, standard epitaxial (weakly
p-doped epitaxial layer on heavily p-doped substrates) were replaced by non-epi¬
taxial wafers with a resistivity of 14-24 Qcm.
were
For the first two wafer
runs
processed dining
this
thesis,
a
CMOS
(CBT, Device numbers (Dev.) 6927, 8331) process
nology
offers attractive features for MEMS
junction depths and an additional
Using the electrochemical etch-stop
ent
diaphragm
devices
in
thicknesses
deep
Chapter 4.2).
and
a
In
can
n-well
Fig. 1.2,
be
based
2.0 pm
was
high voltage
used. This tech¬
applications: two n-wells with differ¬
p-well inside the deep n-wcll are available.
at
the n-well/substrate
obtained.
junction,
different
Furthermore, integration of CMOS
micromechanical
structures
the main features of this device
is
possible (see
technology
are
listed
device cross-section is shown.
9
Technologies
.4 IC Process
Core process
P-substrate twin-well
Drawn channel
length
2.0 pm
Isolation method
LOCOS
Interconnect
2 metal
Layer
Gate oxide thickness
17 nm
Mask Levels
13
S
(Local
Oxidation of
Silicon)
layer (AISiCuTi)
or
51
G
S
D
G
CMOS, poly Si gate
nm
(high voltage)
S
D
G
D
'BPSG
iLp+fa y_/p+J
kP
Deep
we
N wel
CMOS in
High-Voltage PMOS
deep
N-well
Poly Si
P-Substrate
Fig.
1.2:
Field Oxide
2.0 pm
High-Voltage CMOS technology CBT (S:
MOS transistors).
gate, D: drain of
In the
course
(CYE,
Dev.
of this work, also
8654)
cross-section
platform
During
employed.
displayed in Fig.
was
The main features of this
1.3. In the
technology
future, it is planned
and
a
(CU-) and 0.8 pm BiCMOS technologies (BY-) of AMSiAG
as a
the work
on
within the research
designs
development
research and
on
IC-microsensors.
development
were
assembled
were
into
fabrication of 10 wafers. In most cases,
silicon microsensors at PEL
single design
a
design support,
were
and
processing steps required
the IC
wafers
were
developed
Micromachining
mask
provided.
The
submitted
Engineering
to
Ser¬
fabrication, and the
than 20 wafers per
more
cated. Additional
line of AMSiAG.
on
fabricated within the frame of the
vice of AMSiAG. This service includes
processed
near
projects mentioned, microsensor designs
AMSiAG. The wafers
10
technology
use
for research and
individual
advanced 0.8 pm 5 V CMOS
to
are
0.6 pm CMOS
an
source, G:
run were
for the fabrication of
fabri¬
sensors out
of
and carried out in the wafer fabrication
of wafers
was
performed exclusively
after
1 Introduction: Silicon Microsensors
Core process
Drawn channel
P-Epi
length
twin-well
0.8 pm
Isolation method
LOCOS
Interconnect
2 metal
Layer
Gate oxide thickness
16
Mask Levels
15
Fig.
1.3:
of MOS
0.8 pm 5 V CMOS
layer (AISiCuTi)
nm
technology
CYE
(S:
source, G:
gate,
D: drain
transistors).
completion
con
CMOS, poly Si gate
of IC
processing, mostly at PEL. ECE and further structuring
diaphragms by RIE were used as micromachining techniques.
of sili¬
11
1.5
Major
1.5
The
I
Results
Major Results
major
results
Integration
presented
in this thesis
are
stated below.
of ECE into industrial CMOS
A
technology
foi
technique
the
preparation
of CMOS
wafers for ECE using standard CMOS pro¬
cessing only
developed. It includes the
creation of a conducting network with a con¬
tact field (on top of the Figure) for the con*
5
<
nection
'
'
was
and
the
electrochemical
»
distribution
potentials
of
the
and the
tion and
penaliza¬
back. Using
masking of the wafer
pre-processed wafers of this kind, numerous
microsystems were fabricated, such as ultra¬
sonic sensors, force
microscopy
compounds.
and chemical
sensor
sensors
for atomic force
systems for the detection of volatile organic
II
Development of a new silicon wafer starting
co-integrated with CMOS circuits.
material for silicon
A
new
material
sensors
its
a
for
was
wafer
starting
integrated
developed. It
very low defect
dining
thus,
silicon
sensors
CMOS
silicon
exhib¬
generation
processing and,
strongly improved quality
of cavities obtained by wet aniso¬
tropic etching (right side of the
Figure compared to the left side
con
wafer
material).
Due to the low defect
gettering of impurities is supressed. As a
damage of the crystal lattice at the wafer
12
a
showing a cavity in standard sili¬
density in the new material, internal
consequence, external
back
was
introduced.
gettering using
a
1 Introduction: Silicon Microsensors
Outline of the Thesis
1.6
Following this introduction, the integration of ECE into a commercial CMOS
process family is described in Chapter 2. The micromachining of wafers using
ECE is adresscd in
presented in
co-integrated CMOS
ogy is
with
Chapter 3. A variety of devices fabricated using this technol¬
Chapter 4. Force sensors for atomic force microscopes (AFM)
are
vapors
feature
described.
size
of
circuits and
Furthermore,
n-well
based
Chapter 5, manufacturability
and
a
smart sensors
technique
organic
for the reduction of the minimum
micromcchanical
yield aspects
for the detection of
of the
is
presented.
In
developed technology
are
structures
adressed.
In the second part of the thesis
(Chapter 6). compatibility problems between
CMOS and ECE are discussed. Special attention is paid to internal gettering with
bulk microdefects used in contemporary CMOS processing. Microdefects in the
wafer bulk, such as stacking faults and dislocations used for internal gettering
deteriorate the surface quality of cavities created using ECE. Detailed investiga¬
tions of the influence of the initial concentration of interstitial oxygen of the
wafer starting material on the bulk microdefect generation and the quality of
etched cavities
and back side
result,
a new
externa]
carried out. External
were
damages
are
silicon wafer
gettering using
sive remarks and
an
a
investigated
starting
in
gettering using polysilicon back sides
order to replace internal gettering. As a
material with reduced interstitial oxygen and
back side
damage
outlook to future work
is introduced. In
are
Chapter 7,
conclu¬
aiven.
13
1.6 Outline of the Thesis
14
2
Adaptation
of CMOS for
Anisotropic Etching
Adaptation
2
with Electrochemical
of
Etch-Stop
CMOS
Anisotropic
for
Etching with
Electrochemical
Etch-Stop
In this
chapter,
the modification of
an
industrial CMOS process
family
for the
application of anisotropic etching of silicon with an electrochemical etch-stop
(ECE) is presented. The modified CMOS processes provide wafers prepared for
the connection of the etching potentials through a wafer holder with spring
loaded contacts. For the connection to the wafer holder contacts,
a
large
contact
field is created at the wafer border. A wafer-wide
to the contact field
is formed to
supply
the
conducting network connected
electrochemical potentials to all struc¬
tures to be micro machined.
The network and the contact field
thography steps performed
on
created
are
by
a
number of additional
wafer-steppers together
of the standard metallizations. Therefore, the method
photoli¬
with the
can
be
photolithography
applied to present
and future IC device
diameter. After
technologies irrespective of minimum feature size or wafer
standard IC-processing, a penalization of the wafer back and the
deposition
PECVD silicon nitride
of
a
Up to now, the method has been
(CYE) CMOS device technologies at
out.
Unterpremstatten,
In the
following,
Austria
the
masking layer on the wafer back is carried
implemented into 2 pm (CBT) and 0.8 pm
Austria Mikro
Systeme
(AMSiAG) (sec Chapter 1.4).
changes
in the process
mation and the treatment of the wafer back
for the formation of
(a)
a
method
using
a
an
cycle
International AG,
necessary for the contact for¬
explained in detail. Two methods
supply for the ECE potentials to the wafer are presented:
additional metal layer employed for the first devices proare
15
2.1 Wafer Contact Network for the
cessed
only
during
of the Electrochemical Potentials
the work towards this thesis and
standard advanced
on
Application
(b) the
formation based
photolithography using wafer-steppers.
Wafer Contact Network for the
2.1
contact
Application
of the
Electrochemical Potentials
Modern CMOS
technologies provide weakly doped n-well s diffused in weakly
or epitaxial layers. Thus, the electrochemical etch-stop technique
p-doped wafers
can be applied at
the p-n
junction
and the substrate
n-well)
have to be
electrically
between the n-well
(to be referred
[36]. However, all structural n-well
connected
together
as
structural
areas on
the wafer
and routed to the outside to
electrochemical
arise
CMOS
an
potential from a potentiostate. Difficulties
processing since wafer-stepper lithography provides
fields with
nels
containing
arc
variety
a
ment. The individual
of structures for process
step fields have, in
a
scribe channels must be
bridged by
bridges
In the
low-resistivit}
general,
a
corners
ing step
frame
(now available
of the step fields
by
a
potentials
close-up
fields
on a
routed via the first
as
a
library
metal structures
layer of
arc
a
AMSiAG). Fig. 2.1 (a)
connected to each other at the
placed
in the scribe channel. Thus,
throughout
the wafer
supplying
the
structural n-wclls and the
p-substrate. Fig. 2.2
potentials among 4 neighbor¬
completely processed CMOS wafer. The substrate potential is
metal layer while the n-well potential is routed via the second
the CMOS processes. The
during processing
connected to the
n-well and
to the
element at
view of the connection of the
may be clustered inside
16
fields, the
in the scribe channels.
schematic of the frame. The frames
(a) shows
are
align¬
electrical connection to each
suitable metal structures. The construction of
must not affect the structures
electrochemical
frame
no
and mask
connection between the step
the frames build up two contact networks
metal
monitoring
scribe chan¬
concept developed during this thesis, each step field is surrounded by
predefined
shows
modern
array of step
separated by approximately 100 pm wide
other. In order to form
these
in
the
mutual connection.
no
the step fields
Usually,
apply
of the
a
single
design
microsystem design
is
placed
inside the
data for mask fabrication. Small
frame. All structures in
a
designs
design requiring ECE
etching potentials by routing them from the frame to the
p-substrate contacts of the structures. Ohmic contacts to the structures
2
Adaptation
of CMOS for
Anisotropic Etching
with Electrochemical
Etch-Stop
Microsystem design
SL
"S
M
ir.
F
;j ,
,
(b)
(a)
lb"——"--—-— "-%
Fig.
2.1
:
tials, (b)
Schematic of
array of
step
(a)
frame
distributing
fields surrounded
the electrochemical
poten¬
connected frames;
by mutually
requiring etch-stop, grey:
etched through the openings of
black: contact network for the structural n-wells
contact network for the substrate to be
the mask at the wafer back.
miiiHi
.:
ï-îîiÀffc^-.i .:;:
ISC
.-.^'ÄSfiW
(b)
(a)
»sYy
11111111
H
1 200
pml
(a) photograph of connection of frames carrying the electro¬
chemical potentials among four neighbored step fields in a processed
wafer (Dev. CBT 6927) (SC: scribe channels), (b) for identification,
close-up of frame crossings taken from Fig. 2.1, black lines supplying the
n-well potential are removed at top right of the picture; dashed: additional
Fig.
2.2:
metal structures in the scribe channel.
17
2.1 Wafer Contact Network for the
Application
generated by heavily doped, shallow
source/drain diffusions).
are
In order to avoid short circuits of the
area on
the wafer is limited
edge free
leaving
of structures. For the
step field array is removed
on
stepped exposures of the photo
of one single step field).
of the Electrochemical Potentials
and
n-
potentials
an area
same reason,
at
with
the
p-diffusions (p
a
the wafer
excess
both metal mask levels
resist with
the
mm at
stepped
the wafer
metallization outside the
by
'free' reticle
a
edge,
width of 3
standard
n
,
additional automated
(mask for the exposure
In bulk
micromachining using ECE, a waferholder with spring loaded contacts is
commonly used to apply the electrochemical potentials to the wafer. Macro¬
scopic metallized areas large enough to ensure reliable contact to the contact pins
of the holder have to be created
identical in conventional
the wafer.
wafer-step per
contacts (to be referred
scopic
potential
field.
on
Unfortunately, all stepped fields arc
processing. Thus, the creation of macro¬
ECE contacts in the
following) to supply the
from the outside to the wafer would consume expensive area on each
Two different concepts to solve this problem arc described in the following.
Contact formation by
For the first wafer
Dcv. CBT
create
8331),
a
network
additional metal layer
processed during
runs
third metal
the ECE contacts
every step field
an
layer
this thesis
structured
[37]. Medium sized
used to connect the
were
distributing
as
by
a
contact
potentials
(Dev. CBT 6927, part of
lift-off
technique
pads (400
pm
by
from the ECE
was
used to
400
pm)
contacts to
on
the
the ECE
potentials. The etching potentials were routed from
the frames to these contact pads. The actual ECE contacts were created at the
edge of the wafer using a third metal layer. Metal lines were routed from the ECE
contacts to the medium sized contact pads of the nearest step field. In Fig. 2.3, a
photograph of a wafer processed using this technique is shown.
Exposure on a wafer aligner was used to structure the PEC VD silicon nitride pas¬
sivation layer at the end of the CMOS process in order to generate the pad open¬
ings.
The
photo
resist at the location of the ECE contacts
Therefore, bonding pads
lift-off, a negative photo resist
at this location
mask
large
schematically
chromium
development
18
shown in
areas
forming
of the resist,
a
was
not
exposed.
remain covered with silicon nitride. For
was
deposited
Fig.
2.3
and
exposed through
a
single wafer
(b). The wafer mask pattern contains
the ECE contacts
6000 A aluminum
two
during further processing. After
layer was deposited on the wafer
2
Adaptation
of CMOS for
Anisotropic Etching
with Electrochemical
Etch-Stop
Fig. 2.3:
Photograph of (a) wafer (Dev. CBT 6927) with contacts for the
application of the electrochemical potentials created by a third metal
layer, (b) mask pattern for the lift-off mask. A close-up view of the area
enclosed by a dashed rectangle in (a) is shown in Fig. 2.4 (b).
surface
formed
by low-temperature sputtering. Lift-off of
in an ultrasonically agitated acetone bath.
the aluminum
layer
The described method has two main draw backs: First, the exposure of the
vation
layer
with
wafer mask
a
Second, problems
causes
frequently
observed. As
wafer
was
piesent. In
along
the step
helped
a
result,
some
ferent
overcome
technique
to
by 400 pm
medium sized contact
pads
were
ohmic contact to n-wells and substrate of the
a
scratch with
a
wafer
prober
needle directed
the electrical connection from the ECE contacts
Photographs showing
displayed in Fig. 2.4.
Wafer-stepper-based
In order to
no
cases,
to restore
to the wafer.
are
passi¬
of several pm.
with the step coverage of the third metal at the transition
between third metal and the 400 pm
problem
varying alignment
errors
per¬
was
the
alignment
error
and the step coverage
contact formation
the difficulties associated with the third metal
create
the ECE
contacts
was
developed.
layer,
The
a
dif¬
technique
19
2.1 Wafer Contact Network for the
Alignment
error
of
of the Electrochemical Potentials
Application
passivation layer
Poor
step coverage
3rd
metal
"lULiuutinu
(a)
SS^^SHO
200 pm
'
urn
W,m^v;
Substrate
potential
N-well
potential
(a) a bonding pad and (b) the connection of
the structured third metal layer to the medium sized contact pads present
on every step field (Dev. CBT 6927).
Fig.
Photographs
2.4:
involves standard
is
of
No additional metal
layer
which has the
same
wafer-stepper lithography steps only.
required.
At the wafer
size
as
border,
a
dedicated 'contact' step field is
the other step fields. This
at the second metal mask
reticle. The
done
by
a
field
generated single
to
of the step field array
the
on
spimg-loaded
a
contacts of the
the wafer is chosen in
Fig. 2.5,
using
special
large bonding pads
contains two
field hits the wafer holder contacts. In
photo resist
second exposure of the
level of the CMOS processes
the connection of the wafer
layout
is
printed
to allow
for
wafer holder. The
way that the contact step
stepper-based
passivation layer at the
schematic of the
a
contact construction is shown.
a
'contact'
of the
Dining patterning
end of the IC process, a procédure similar to the creation of the contact field is
used to remove the passivation from the contact field: at the location of (he con¬
tact
field, the photo
in the
wafci-stepper. Again,
removed
'empty'
to
20
resist is
on
exposured through
the
excess
both metal mask levels
reticle.
Fig.
2.6 shows
a
a
special
'contact
metallization outside the
using
automated
photograph
of
a
stepped
wafer
stepped
area
exposures with
pre-processed
allow for ECE at CMOS n-wclls. The individual step field
reticle
opening'
size
is
an
in that way
is 15
mm
by
15
2
Adaptation
of CMOS loi
Anisotiopic Etching
with Electtochemical
Etch-Stop
Contact field
Microsystem design
Single
step
field
Fig.
2.5:
Schematic of the
stepper-based network construction; on top
field for the application of the electrochemical
picture: contact
potentials via spring loaded
of the
Fig.
contacts in
a
wafer holder.
Photograph of a 100 mm wafer (0.8 pm CMOS, Dev. CYE 8654)
with
pre-processing for anisotropic etching with electrochemical
etch-stop (ECE).
2.6:
21
2.2
of the Wafer Back
Preparation
mm.
If
tive die
required,
the step field size
be reduced in order to increase the effec¬
can
the wafer.
area on
The third-metal-based method for the creation of the ECE contacts
additional masks,
outside the
one
stepped
wafer mask for the
'empty'
array
on
reticle for the removal of the
the
patterning
The
wafer,
one
wafer mask for
of the third metal
excess
outside the
'contact"
reticle for the removal of the
the second method is
Additionally,
wafers must be
On the other
one
piocessed
in the
reticle, and
one
requires
excess
'contact
one
also three
metallization
opening'
expensive than the first
wafer-stepper two times more.
more
hand, the stepper-based
and
layer.
the creation of the ECE contacts
array,
three
metallization
pad opening,
stepper-based method for
additonal masks, one 'empty'
stepped
requires
one
reticle.
since the
formation
technique is only based
standard submicron resolution photolithography. The technique is not
on
restricted to the minimum feature size and wafer diameter of a particular process
technology. It can simply be applied to future IC process families. Furthermore,
the overall reliability of the additional processing is much higher.
contact
engineering wafer runs (10-20 wafers each) were processed during this
thesis. The first one (CBT, Device number (Dev.) 6927) and part of the second
Three
(CBT,
one
based
on
8331)
were
processed
with the ECE contact formation method
the third metal. The last wafer
exclusively
2.2
Dev.
with the
run
(CYE, Dev. 8654)
was
processed
stepper-based technique.
Preparation
of the Wafer Back
Anisotropic wet etching with an electrochemical etch-stop starting at the wafer
back requires a back mask. In initial tests, PECVD silicon nitride layers were
deposited directly on the back of CMOS-processed wafers using a STS 310 PC
equipment. Roughness of the wafer back, scratches, and particles deposited dur¬
ing processing deteriorated the mask quality Therefore, an in-fab spin etcher
(SEZ AG, Villach, Austria,
see
[381)
at
AMSiAG
was
used to
planarizc
the wafer
back before
cal
masking. Photographs of the wafer back before and after the chemi¬
penalization arc shown in Fig. 2.7. The method utilizes a stream of an isotro¬
pic
silicon ctchanl
of the
rotating
containing H2S04,
wafer. The wafer floats
HE
on
HNO^, EI3PO4 directed onto the
a nitrogen cushion protecting its
back
front
2
Adaptation
'
k"T<
\
'
,,
<«
«'"«•ft
••
é:j.m"'
>\
^
with Electrochemical
Etch-Stop
...
«*-..
1
I
H^
i>. \
,
*
ï1-
Anisotropic Etching
•'M^.-^'J*
't.
.
4»
»u
of CMOS for
««
4
,
.>:•>' :
'
»Si
«-•.'..
i
'ro
"Vit
y*i
'"i~
ST^^';^ ;50
•-
«s*
Fig.
2.7:
side
throughout
»
pm
50 pm
>
.
Photographs of the wafer back before (a) and after (b) the
chemical planarization. In (b) shallow sickle-shaped patterns caused by
bulk stacking faults can be observed.
the entire
routinely employed
packages
can
as a
etching
process.
last step in CMOS
Thinning
of wafers after
processing
be reduced due to the smaller thickness of the dies.
of 0.06 pmmls with
a
spatial wavelength
of
is
because the size of the die
the substrates from 525 pm to 380 pm in around 100
roughness
processing
results in
s
of
Spin-etching
a
back surface
approximately
300 pm.
The
spin-etcher has a recycling system tor the silicon etchant. The etchant is
replaced routinely after approximately 300 wafers. Tt was observed that wafers
thinned
just
exhibited
before the
an
increased
replacement
roughness
of the etchant had
a
dull appearance and
of up to 0.14 pmims. In order to determine
a
maximum number of wafers
of wafers for
wafers
sensor
already etched in the same etchant before thinning
applications, the following experiment was performed, lest
thinned from 525 pm standard thickness to
were
thickness after 0, 83, 208, 250. and 310
the
same
etchant. The surface
mechanical
roughness
profile
(production) wafers
of the test wafers
stylus profiler (P-10. KLA-Tcncor Corp.,
UBM
long
taken
380 pm
have been thinned in
was
determined
San Jose,
using
USA).
using
a
For the
optical profiler
GmbH, Ettlingen, Germany), The influence of the number of
measurement a
(Microfocus.
5
approximately
mm
scan
was
an
wafers
already thinned in the same etchant on the roughness of the test wafers is
shown in Fig. 2.8. A typical profile of the wafer back is shown in the same figure.
The profile was taken after 83 wafers being thinned using the same etchant. A
detailed description of this experiment is given in f39]. As a result of this investi¬
gation, wafers for sensor applications are not allowed to be processed if more
23
2.2
Preparation
of the Wafer Back
10 pm
(a)
0
100 mm
0
150
CO
E
CO
CO
CD
C
JZ
(b)
100
CT)
=3
O
CD
Ü
CO
H—
*—
en
50
0
100
200
300
Number of wafers etched
Fig.
2.8:
100
mm
(a)
over-all
wafer and
number of wafers
than 200 wafers
profile
of
a
(b) roughness
etched in the
already
were
chemically planarized
of the wafer back
already
etched
same
using
the
back side of
a
function of the
as a
etchant.
same
etchant.
(see Chapter 2.3,
STR).
Poor adhesion of silicon nitride
STS 310 PC
on
the
planaiized
back
using
a
frequently observed during etching in 27% KOH
Especially at the position where the wafer holder O-ring seals
equipment
solution at 90°C.
layers deposited
was
(see Chapter 3.1) press on the wafer back, a delaminalion of the nitride layer was
observed. Due to that, perforation of the wafer at the delaminated areas and
breakthrough
In contrast,
of the etchant into the wafer holder occured.
we
observed that the standard silicon nitride
0.8 pm CMOS process CYE
(see Chapter 1.4) deposited
on
passivation
the
for the
planaiized
back
2
Adaptation
of the wafers
of CMOS for
(Concept
and adhesion
was
below 1
properties
"
cm
Scratches
implemented
ticle
density
the back and
(Surfscan,
found
were
at the
layer
as
the
in
rinsing
a
a
test
wafer after
rinscr-dryer.
of silicon nitride
deposition
Data
handling
were
not
from the wafer-handler of the
the front side of the wafer.
front side of
pinhole density
part of the back end of the CMOS pro¬
particles originating
on
San Jose,
shows excellent mask¬
the front side due to front side wafer
on
observed. On the other hand,
PECVD system
etching. Therefore,
Etch-Stop
Systems Inc.,
in 27% KOH solution at 90°C. The
after 3 firs
at the wafer back was
cesses.
One PECVD system, Novel lus
much better results. The silicon nitride
USA) yields
ing
with Electrochemical
Anisotropic Etching
Fig.
deposition
were
2.9 shows the par¬
of silicon nitride
taken with
a
particle
on
counter
KLA-Tencor
wafer-handler
can
be
Corp., San Jose, USA). The 'particle image' of the
clearly seen. Particles on the frontside of the wafer may
O
/
'
(a)
(b)
o
o
w
Fig. 2.9:
(a) particle density at the front side of a test wafer after the
deposition of silicon nitride on the back (black: particles with sizes from
2.4 pm to 100 pm) and (b) shape of wafer-handler used in the PECVD sys¬
tem.
cause
problems during
photo
resist
ing
was
with
not
or
other
layers
possible.
clean
further
is
A way
wiper
processing
of the wafers
required. Complete
to remove particles
if, e.g., deposition of
removal of the
particles by
of this kind is to
wipe
rins¬
them off
with both, wafer and
wiper immersed in a sink with
deionized water. Similar particle cleaning procedures using brushes arc com¬
monly employed for after-CMP (Chemical Mechanical Polishing) -cleaning. An
a
room
25
2.3
Implementation
of the
Adaptive Steps
additional detrimental effect
processed
were
was
wafers: electrostatic
detected
on
into the
Production Flow
observed with the back side
discharge (ESD)
Chapter
phenomenon
were
Testwafers
with standard silicon
bonding tests
planaiized and coated
were
was
was
the wafer back is not
2.3
subject
to
a
Pyrex
planaiized wafers.
nitride passivation (see
wafers. An electrostatic
glass
(SB 6, Karl Suss AG, Munich, Germany). Bonding
used
at 300°C and
performed
is
carried out with the
bonded with their back to
bonding equipment
fully
5.1.
Some initial wafer
above)
of
defects with sizes of several pm
the front side of coated wafers. This
detailed discussion in
coating
a
voltage
of 500 V.
prime-grade, large
of the
Implementation
Although
unbonded
the surface
areas were
Adaptive Steps
quality
of
not observed.
into the
Production Flow
IC manufacturers
monitoring
commonly
travellers
use run
or run
sheets for controlling and
the
production. For every processing step called a location (deposi¬
tion, photolithography, etching, etc.), and every process technology, a set of
instructions is stored in
locations for
out
specified
a
a
computer system. A printout of the complete
wafer
run
is called
is attached to the wafer box and
process. Process
gram
numbers,
monitoring
are
run
as
or run
the wafers
layer thicknesses,
traveller. In order to
steps for ECE into the real world of IC
lent instruments had to be
raveller
accompanies
data, such
recorded in the
a run
manufacturing,
sheet. This
through
of
print¬
the whole
machine and pro¬
bring
run
set
the
preparation
travellers
or
equiva¬
developed.
Run Travellers
complete run traveller was developed for the 2.0 pm CMOS technology (CBT)
together with an additional metallization for the creation of the ECE contacts.
The new, adapted process called CBU includes all additional steps required for
A
ECE, such
as
contact
nalization and
formation
masking
A number of difficulties
using
the third-metal-based method and the
pe¬
of the wafer back.
arose
with this concept. First, for any other basic process
technology (0.8 pm (CY-), 0.6 pm (CU-). etc.) a new special run traveller would
have to be developed. Second, compared to other wafer runs at AMSiAG. the
number of wafers
26
processed
for ECE
sensor
applications
is
currently
rather
2
Adaptation
small.
of CMOS for
Processing
of wafers with
unnecessary holds and
Therefore, it
called
was
Special
Anisotropic Etching
waiting
decided to
Test
times.
use
special
Etch-Stop
not very well known run traveller caused
a
standard
Request (STR).
monitor parameters of
with Electrochemical
run
STR's
travellers in combination with
are
Irequenlly
a so
used at AMSiAG to
during ongoing production. An STR
contains special instructions at specified locations for specified wafer runs
(devices). It is stored in the computer system and automatically activated at the
specified locations. A dedicated STR for the adaptive steps required for ECE was
developed during this thesis. A similar STR was applicaled for the fabrication of
process steps
the 2.0 pm CMOS devices CBT 8331 and the 0.8 pm CMOS device CYE 8654.
A schematic of the STR used for ECE
preparation
with the
stepper-based
genera¬
tion of ECE contacts is shown in Table 2.1.
Table 2.1
:
Run Traveller and
Loc.
Process
1200
Initial oxidation
(Start)
and Si-nitride
Special
Test
Request
STR Instruction (condensed)
Step
dep.
-
1670
N-well
implant
mask
Inspection
stepped
of
area
from wafer
developed resist,
outer
boundary
must have at least 3 mm
of
distance
edge
-
8780
Metal I mask
Second
(stepped)
remove
excessive metallization outside
area
exposures of
photo
resist to
stepped
(see Chapter 2.1), inspection
-
8880
Metal 2 mask
Second exposure of
tact' reticle, further
resist to
remove
stepped
area
photo
resist
(stepped)
through
'con¬
exposures of
photo
excessive metallization outside
(see
Chapter 2.1), inspection
-
27
2.3
Implementation
Table 2.1
:
of the
Run Traveller and
Loc.
Process
8900
Deposition
8950
Adaptive Steps
Step
of Pas-
into
the Production Flow
Special Test Request
STR Instruction
Deposition
(condensed)
of low stress
sivatiou
CMOS,
Passivation mask
Second exposure of
see
Chapter
passivation
of 0.8 pm
5.2
photo
resist
through
opening' reticle, (see Chapter 2.1)
'contact
-
9100
Thinning
of sub¬
strates
Thinning
of substrates to 380 pm, not
200 wafers
already
etched in the
same
more
than
etchant
(see Chapter 2.2)
9200
Back mask
Deposition of
Chapter 2.2)
silicon nitride
on
wafer back
(see
-
...
9375
Electrical map
-
(End)
This STR
can
be used for different process
technologies
On the other hand, it is obvious that this solution is not
ume
28
production.
without
major changes.
satisfactory
for
high
vol¬
3
3
Micromachining using
ECE
Micromachining
CE
In this
given.
sured
chapter,
a
detailed
description
The electrochemical
using
wafers. The
test
of the setup used for
micromachining
current-voltage
characteristic of the setup is
micromachining
of
fully processed
is
mea¬
CMOS wafers is
described.
3.1
for
Setup
Micromachining Using
The conventional 4-electrode
basic setup used
methods
throughout
ECE
(4EC) setup introduced by Kloeck et.al. f40] is the
this thesis. A
general
introduction in electrochemical
be found in
(41], The n-well(s) and the p-doped bulk of the pro¬
cessed CMOS wafers form the working electrodes, an Ag/AgCl electrode is used
can
as
reference electrode and
as
counter
The
platinum
electrode. The setup is
Ag/AgCl
anisotropic
wire
partly
schematically
enclosed in
shown in
reference electrode is used to create
etchant. A 6M KOFI solution at 90°C
electrode consists of
KCl
a
electrolyte.
an
Ag
wire convered with
a
Fig.
a
glass
tube is used
3.1.
well-defined contact
was
AgCl
used in most
The
cases.
salt in contact with
the
to
a
3M
The KCl
electrolyte itself is in contact with the KOFI solution
via a semipermeable diaphragm. The potential of this electrode vs. the etchant is
given by the sum of the cell voltage of the Ag/AgCl/3M KCl cell and the diffu¬
sion voltage of the liquid junction 3M KC1/6M KOI I. The temperature dependent
cell
voltage is approximately 130 mV at 90°C. The diffusion voltage cannot
measured directly but calculations yield a \aluc of approximately 25 mV.
detailed
description
order to prevent the
ence
electrode
no
of the
depletion
current
impedance negative input
ence
electrode. The
(Platinum wire) and
Ag/AgCl/3M KC1/6M
of the KCl
should flow
of
KOH cell is
an
etching
in
electrolyte in the interior of
through it. For that purpose,
operational amplifier
operational amplifier is operated
the
given
solution in
a
be
A
[42]. In
the refer¬
the
high
is connected to the refer¬
via the counter electrode
closed-loop
mode. Therefore, the
Setup
3.1
for
Micromachining Using
^reference
ECE
O
Potentiostate
Counter
electrode
N-we
P-substrate
Fig.
3.1
Schematic of the 4EC setup used in this thesis.
:
voltages at the negative and
equal and the potential of the
reference
etchant is
are
the
positnc input
of the
reference electrode may
rents,
a
kept
with respect to the Ground.
supply
potentiostate
potentials
are
the
voltage (Vref). In this way, the potential between silicon electrodes and
regulated by shifting the potential of the etchant. The structural n-wells
connected to Ground and the p-type substrate is
(Vbias)
operational amplifier
be adjusted by varying
Operational amplifier,
voltage, and a display were integrated in
throughout the work towards this thesis. Standard
a
for the bias
used
used
at a fixed bias
for
the
driver for
a
voltage
larger
cur¬
home-built
values of (he
micromachining of wafers were Vlcl -1.5V and
Vbias -5 V. The bias current flow ing through the reverse-biased junction and the
termination of the etching of the p-substrate for Vb]as <
2.4 V were used to con¬
=
=
-
trol the function of the apparatus. In
tials in the 4EC is shown.
30
Fig. 3.2,
a
schematic of the various poten¬
3
Micromachining using
ECE
n-Si
Ground
Vb,as -2.4 V
(etch-stop substrate)
=
Passivation
p-Si at passivation
potential
Etching
V:bias
-5V
p-Si
Fig.
3.2:
Schematic of various electrodes and their
potentials in the
4EC configuration, dashed: p-Silicon at passivation potential (potential
for etch-stop). Etching of the n-silicon may be initiated if its potentia!
(Ground) is shifted to values lower than the dashed line.
Wafer holders sealed with
O-rings (EPDM, Angst
&
Pfisler, Switzerland) and
equipped with spring loaded contacts were used during the work towards this the¬
sis. Generally, the wafer holder consists of two parts, the bottom part containing
the
by
spring
a
loaded contacts and the
number of stainless steel
sealed with the
O-rings.
wafer holder press
on
If
fittings
and
The wafer is
the contact
areas
present
beginning of the work towards this
designed and built. The potential supply
teflon hose and
stainless steel
thesis,
a
fittings.
because overpressure in the etch holder caused
etching
solution may
damage
tion of the
spring
was
stainless steel holder
a
A pressure release is
is
was
required
high temperature of the
diaphragms. Later, plexiglass
by
the
used for the
improved
At
realized
were
body
of the holder. Isola¬
loaded contacts from each other is easier to realize
material. Moreover, process control
part
Chapter 2.1).
pressure release
the micromachined
(polymethylmethacrylate (PMMA))
the bottom
loaded contacts of the
the wafer (see
on
and
on
between both parts and
placed
correctly positioned, the spring
screws.
the
using
lid to be fixed
a
using
this
since the wafer holder is trans¬
parent. In initial experiments, creeping of the wafer holder material
at
the
etching
j
I
3.1
Setup
for
temperature
very
Fig.
bulky.
3.3:
Micromachining Using
was
In
ECE
observed. To avoid this, the
Fig. 3.3,
a
plexiglass
holders
were
designed
wafcrholder of this kind is shown.
Photograph and schematic
cross-section
of
a
plexiglass
waferholder.
Current-Voltage Characteristic
In order to characterize the
were
determined. P- and
tion of 6.5-10
pose. A
p4
or
etching setup, the passivation potentials and -currents
n-doped, 100 mm test wafers with a dopin° concentra-
cm° and 1-10
create ohmic contacts to
(CYE,
created
32
a
CMOS process
(CBT,
see
Chapter 1.4)
this pur¬
standard
were
the bulk of the wafers. A standard silicon nitride
Chapter 1.4) was deposited on
by patterning the silicon nitride la\er using
see
prepared for
together with a
were
n+ standard source/drain tilt fusion
aluminum metallization of
tion
cm~\ respectively,
used to
passiva¬
the wafer back. An etch mask
back side
lithography
was
and
3
reactive ion
Micromachining using
etching (RIE) giving rectangular openings
done in order to reduce the etched silicon surface
for the
of mm-size. This
and, thus, the
current
ECE
was
required
etch-stop.
scanning potentiostat (362, EG&G PARC) and electrodes
from Metrohm AG, Flerisau, Switzerland were used. Measurements were carried
out
with
using
At
A
a
a
a
potential scanning
teflon sink with
potential
of
of I mVs"
.
Etching
temperature controller (T
=
performed
90+1 °C).
was
in the dark
approximately
sivation of silicon
panied by
a
rate
occurs
0.9 V with respect to the reference electrode pas¬
and the etching is terminated. The etch-stop is accom¬
peak-shaped etch-stop current [40J. Fig. 3.4 shows the passivation
potentials and passivation currents. As to be seen, the Open Circuit Potential
a
Etching
Passivation
P-silicon
N-silicon
._.
<D
T3
C
0)
zs
iwiMwWtlWtf^WwiM»!"'
Ü
0
Vppn
2
0
Voltage
Fig. 3.4:
doped n-
vs.
Electrochemical
reference electrode
[V]
Current
Voltage characteristic of lightly
and p-silicon in KOH solution, voltages measured with respect
to the reference electrode (
Vpp: passivation potential, OCP: open circuit
potential). The standard values (see above) of Vref -1.5 and Vbias -5 V
(measured with respect to Ground) correspont to values of +3.5 V for
p-silicon and -1.5 V for n-silicon, respectively, measured with respect to
=
=
the reference electrode.
33
3.2
of
Micromachining
Fully
CMOS Processed Wafers
(OCP) and the Passivation Potential (VPP) of p-doped silicon are shifted to
slightly lower values compared to n-silicon. Similar results for KOH solution
[43] and TMAH solution [44]
3.2
After
Micromachining
receiving
to
was
an
other authors.
Fully CMOS
Processed Wafers
measured. The measurements
semiconductor parameter
the ECE contacts
istic of
by
ECE-prepared wafers from AMSiAG, the current-voltage
the junction between the p-substrate and all interconnected
structural n-wclls
a
of
obtained
the
characteristic of
using
were
on
analyzer (4156 A,
the wafer. In
ECE-prepared
Fig. 3.5,
a
wafer is shown. The
were
performed
Hewlett
in the dark
Packard) connected
typical current-voltage character¬
forward voltage drop of the diode
50
<
CD
0
-
Ü
-50
-3
-2
-1
Applied
Fig. 3.5:
Current-voltage
CYE
(Dev.
8654).
0
Bias
characteristic
[V]
of
an
ECE-prepared
wafer
is shifted to values around 0.4 V because of the the very large area of the
p-n
between
all
structural
n-wclls
and
the
substrate. A gradual breakdown
junction
can
be observed at
now not
34
approximately
understood. It
was
1.5 V
re\ersc
bias
present in wafers of all
.
This
phenomenon
engineering
runs
is up to
processed
3
during
not
the work towards this thesis. Howe\er,
influenced
by
the
large leakage
current.
Micromachining using
micromachining
ECE
of the wafers
was
Some of the wafers exhibit short cir¬
cuits between the ECE contacts and, therefore, could not be micromachined. This
is discussed in detail in
topic
Chapter
After the initial test of the diode
etch mask
5.1.
current-\oltage characteristic,
the back of the wafers (see
on
Chapter 2.2)
was
the silicon nitride
structured.
First,
a
photo resist layer with a thickness of 1,8 pm was deposited. A double-sided mask
aligner (EL 6, Electronic Visions, Vil lach, Austria) was used for the exposure of
the photo resist through a 125 mm chromium mask. Masks were fabricated either
at
AMSiAG
at
or
Align-Rite, Nijmegen,
The Netherlands. After
development
of
the
photo resist, the silicon nitride layer was etched in a reactive ion etcher (STS
302) using an SE6 plasma. The wafers were subsequently stripped from the resist
and rinsed in water.
A
commercially
available PMMA
protection coating (XARPC
sion promolor AR 300-80/10, Allresist
deposited
the
on
the wafer front
wafer, deposition
of the PMMA
layer.
sion promotor and
tional
speed
thickness
using
GmbH, Berlin, Germany)
and bake of the adhesion
then
was
three-step procedure: dehydration
a
bake of
promotor, and deposition and bake
All
baking steps were performed for 2 min at 180°C. Adhe¬
PMMA coating were deposited by spin coating with a rota¬
of 3000 rpm and 1000 rpm,
was
5000/4 with adhe¬
approximately
respectively.
5 pm. The
coating
The
serves
resulting PMMA layer
as a protection against
accidental
breakthrough of the etchant into the wafer holder due to cracks in fab¬
ricated diaphragms. After the procedure, the coating was removed from the ECE
contacts by heating the wafer to 50"C and wiping it off using acetone. A detailed
description of various protective coatings is given in Chapter 5.2.
The wafers coated with the
holder. A
dip
native oxide
rinsing,
in
a
layer
rate
PMMA
from the surface of the etch
was
of the solution in (100)
peak
of
an
was
mounted into the wafer
carried out to
openings
on
remove
overetched for 15 min
crystal
a
direction: 125
umrf1),
the
a
cur¬
peak
constant value. Once the constant current is
that the
starting
etching
process is terminated.
with the time of the emergence of the
Fig. 3.6, a current-time graph
ECE-prepared CMOS wafer is displayed.
current. In
the
the wafer back. After
the counter electrode increased within several minutes to
again reaching
reached, H2 bubbling stops indicating
were
were
into the KOH sink. After around 3 hours of
placed
value and decreased
Wafers
layer
1-2% HF solution for 1 min
the waferholder
etching (etch
rent through
protective
recorded
during micromachining
35
3.2
Micromachining
of
Fully
CMOS Processed Wafers
0
500
1000
Elapsed
1500
Time
2000
[s]
Current through the counter electrode measured during
Fig. 3.6:
micromachining of an ECE-prepared CMOS wafer (Dev. CYE 8654). Data
were taken at the end of the total etching time of around 3 hrs.
After
rinsed.
etched
of
etching, the wafers were taken out of the wafer holder and
Sometimes, tiny, black residues with several pm size remained on the
surfaces. The origin of these particle is not clear. It is suspected that impu¬
completion
rities in the
etching
solution
precipitate
as
particles
of this kind.
wafers for several minutes in boiling water enriched with
(Exlran
Dicing
,
Merck)
helped
of the wafers
and Soffa Industries
was
to remo\e the
performed
PMMA
during dicing.
After
dicing,
In the next
the
by
either
a
standard wafer
saw
a
dip
room
detergent
(982-10, Kulicke
Inc., Willow Gro\e, PA, USA) with reduced
rigid
die surface
clean
the
residues.
using
and water pressure. The
structures
a
Immersing
coating protects fragile
the PMMA
in hot acetone
or
chapter, a number of integrated
described technique aie presented.
coating
by ashing
silicon
in
was
an
water
flow rate
micromechanical
removed from the
oxygen
microsystems
plasma.
fabricated with
4 Fabricated Devices
4
Fabricated Devices
In this
chapter, CMOS-integrated microstructurcs and -systems fabricated using
ECE are presented. About 10 coworkers of the Physical Electronics Laboratory
are responsible for the designs of various microsystems. The adapted CMOS
pro¬
and
cess family
subsequent micromacbing using ECE formed the technological
base for their R&D on silicon microsystems.
Basic
micromechanical
n-wcJl-based silicon
side
lithography
island structures
components
diaphragms (if required,
and reactive ion
etching (R1E))
or sensor
the
technology
further structured
and
layers
microscopy (AFM)
At the end of this
n-well based silicon
(2)
of the CMOS process
application
in
an
were
fabricated
chapter, special
during
soft contacts for the fabrication of
4.1
Silicon
Within
project
2.03 PROXYST of the swiss
proximity
and ultrasound barriers
sensors
are
used
priority program MINAST [34], sili¬
are developed. Ultrasound proximity
for liquid level control, counting of
transparent parts, control of stacking levels,
sensor
an
is
a
Usually,
obstacle is
generation
piezoelectric
as
etc. Heart
of
ultrasound transducer with
a
conventional ultra¬
driving-
and readout
time of
flight measurement of an ultrasound pulse reflected at
performed. Commonly, the same piezoelectric layer is used for the
and the detection of ultrasound.
Within the PROXYST
gated
are
arbitrarily
presented.
Diaphragms
based ultrasound
circuits.
ultrasound based
the work towards this thesis.
n-well microstructures with small minimum feature size
sound
for,
capacitive microsensors used for the detection of organic
integrated force sensors for the application in atomic force
shaped
sensors
using
(1)
front
sensor, smart
volatiles in air, and
con
are
structures.
membrane resonators for the
Among others,
to be
the dielectric
suspended by
e.g., thermal isolation of circuits
proximity
producible by
project,
silicon membrane resonators have been investi¬
ultrasound transmitters and receivers for
proximity sensing. However,
il
4.1 Silicon
Diaphragms
since silicon is
and detect
a
not
piezoelectric,
diaphiagm
detection using diffused
sensoi
a
deflection
icsistois
system A schematic and
system
is
shown
m
Fig.
an
a
othci mechanism had to be found to actuate
Electiotheimal excitation and piczoiesi stive
have been chosen loi the
photogiaph
ot the
integiated pioximity
diaphiagm
îcsonatoi ot
such
4 1.
Wheatstone
bridge
P-substrate
(a)
X
Back mask
Cavity
Heating
resistor
(b)
diaphragm resonator with dif¬
fused resistors and wiring and (b) photograph of a fabricated silicon dia¬
phragm; the right hand side of picture (b) is illuminated from the back.
(Dev. CYE 8654, the thickness of the diaphragm is 6.3 urn).
Fig.
38
4.1
:
(a)
schematic of half of
a
silicon
4 Fabricated Devices
In order to characterize the fabricated
face
measured
using
diaphragms,
the
profile
of their etched
sur¬
optical profiler (microfocus, UBM GmbH, Ettlingen,
Germany). The diaphragms slightly buckle due to compressive stress in the stack
of CMOS dielectric layers on top of the silicon surface (sec Chapter 5.2). Surface
was
roughness
is
an
values of around 0.25 pmims
were
typically
observed. This
roughness
higher
roughness
by anisotro¬
pic etching using a timed etch stop (0.07 0.14 pmims). The reason for this
increased roughness is, up to now, unknown. Impurities in the etching solution
were discussed as possible origin of the increased roughness [45]. A photograph
of an etched membrane surface and its surface profile are shown in Fig. 4.2. In
than the
of etched membrane surfaces obtained
-
Fig.
4.2:
Nomarski
fabricated
photograph of (a) bottom surface of a diaphragm
and (b) surface profile along line A. A slight buck¬
using ECE
ling of the diaphragm of 0.3 urn
(b). (Dev. CYE 8654, VLOX wafer
the
diaphragm
most cases, the
6.3
was
subtracted from the data shown in
material
(see Chapter 6.3),
thickness of
pm).
diapragm
thickness is
slightly reduced close to the edge of the
diaphragm and starting from a line parallel to the edge. This is probably due to
the direction of the flow of the etchant driven by the generation of hydrogen bub¬
bles.
Resonance
kind range from 50 kHz to
than 100
due to residual stress of dielectric
frequencies of diaphragms of this
kHz depending on size and buckling
layers. Quality
factors of 100 in air
arc
routine!)
observed. Details
more
concerning
39
4.1 Silicon
Diaphragms
physical properties
of the
diaphragms
and their
applications
can
be found in
[46,47],
The fabrication
production
scopes
technology
for silicon
diaphragms
was
also
of cantilevers foi
(AFM).
integiated parallel scanning
developed systems comprise two or
The
cantilevers and microelectronics to read
out
for the
employed
Atomic Force Micro¬
more
micro fabricated
their deflection due to features of the
probe surface. The deflection of the cantilevers is detected using piezoresistors
and amplified on chip. Thermal actuators are integrated in the cantilevers to allow
for their independent deflection. In contrast to the classical AFM setup 148], no
external
optical
vers were
phy
cantilever deflection measurement
obtained
by patterning
and reactive ion
AFM force
sensor
in
shown
Fig.
On
Fig.
4.3:
of
side
of
(Dev.
CBT 8331, NOX wafer
the
the
read-out
same
phragm
rounded
by
ring-shaped
40
a
silicon
(a)
structure
amplifier
material.
m
diaphragms using frontsicle lithogra¬
SF6 plasma. Photographs of an integrated
a
4.3. A central silicon
chip amplifiers
Photographs
needed. The AFM cantile¬
the silicon
etching (RIE)
are
is
an
Silicon
AFM force
chip (boss)
is
sur-
diaphragm
sensor
chip
before
(b) back
diaphragm
and
patterning the silicon
material, see Chapter 6.3). A boss supports
whereas the
diaphragm
area.
opening in the back mask
cantilevers
For
is
a
consist of silicon
diaphragm
requued, thus,
area
the
of this
dia¬
kind,
masking layer
a
has
4 Fabricated Devices
convex
A
corners.
back mask
provided.
was
compensation
was
for the
compensation
not
u tide
After removal of the
material outside the cantilevers and posts
using
of the wafer and mounted in
The AFM
tested in contact and
mode,
are
excited at their
actuators in the cantilevers. The
amplitude
when the cantilever
the
better than 2
images
nm
approaches
were
concerning
surface
were
topography
a
in the
complete
silicon
diaphragm
lithography and R1E,
conventional AFM setup.
mode. In the
frequency using
dynamic
the thermal
of the cantilever vibration decreases
probe surface. Images with a resolution of
using this method. Moreover, parallel scanning
recorded
in contact mode
a
dynamic
resonance
device,
excess
frontside
the device is
the cantilevers
convex corners
Because of the geometry of the
possible.
pressed out
probes were
of
retching
taken
using
the
measurements
integrated
AFM device. Details
with these devices
can
be found in
[49].
4.2
N-well Based Island Structures
ECE at CMOS n-wells allows not
but also for the fabrication of
n-wclls
n-well
tric
can
can
layer
have (with
be released
of the
some
using
particular
and chemical
strate soft contacts
are
for the fabrication of silicon
complex n-well based structures because
limitations) arbitrary shape. A complex-shaped
together
CMOS process
thermally
as
sensors are
employed
diaphragms
more
ECE
based island structures used
sensors
only
presented.
with
etch-stop
(field oxide). In
an
at
the lowest dielec¬
this
isolated substrates for
In the second
part,
section, n-well
magnetic
a new
field
type of sub¬
to shrink the feature size of n-well based structures
discussed.
4.2.1
Thermal Isolation of Circuits
Diaphragms consisting of the CMOS dielectric layer stack can be fabricated
using the field oxide of a CMOS process as etch-stop layer for anisotropic etch¬
ing. Thermal sensors, such as gas flow sensors have been produced this way [50J.
Furthermore, diaphragms composed of dielectric layers and structured silicon
n-wells
and
can
be fabricated
the electrochemical
dielectric
layer
(ISOWKrhrr1)
using
a
etch-stop.
stack (around 1
allows
a
combination of the
The reduced
etch-stop by the field oxide
thermal conductivity of the
WKrVr1) compared
thermal isolation of
strate. The n-well structure can be heated
a
to
single crystal
silicon
n-well structure from the sub¬
independently
from the substrate
using
41
4.2 N-well Based Island Structures
an
integrated
heater
and, thus, forms
mass
of the structure,
only
As
first
CMOS
a
was
example,
a
fabricated (Dev. CBT
large
offset of the
sensor
small
a
'micro-hot-plate'.
heating
powers
field
magnetic
6927), Magnetic
output signal clue
arc
sensor
Field
Due to the low thermal
required
placed
sensors
to process
.
on
a
micro-hot-plate
usually
suffer from
tolerances, such
as
a
align¬
doping variation, etc. Moreoxer, a strong temperature dependence of
the offset requires a time-consuming calibration of the sensors at different tem¬
peratures. The micro-hot-plate concept allows to stabilize the sensor temperature
ment errors,
at a constant value above
ambient temperature, thus,
only calibration at the fixed
thermally isolated lateral magne-
operating temperature is required. A
totransistor is shown in Fig. 4.4. Thermal isolation
sensor
Fig.
and temperature stabilization
4.4:
Photographs of (a) front side and (b) back side of a thermally
isolated magnetic field sensor (Dev. CBT 6927, NOX wafer material, see
Chapter 6.3, thickness of the n-well 9 urn).
to
80°C allowed
to reduce the variation
of the
in the range between -10 C and +80°C
island is surrounded
Chapter
42
by
a
sensor
[51]. As shown
irregularly shaped
4.2.2. Furthermore, the
signal
contour of
offset
in
by
a
Fig. 4.4,
factor of 5
the n-well
rim. This topic is discussed in
the dielectric
diaphragm
is distorted.
4 Fabricated Devices
The
improvement of the geometrical qualit} of the
wafer starting material is described in Chapter 6.
As
second
a
organic
tated
ically
Fig.
volatiles in air have been fabricated [52,53].
structure with
sensitive
Photographs
volatile
organics
for
integrated
polymer. Absorption
4.5:
of
(a)
and
(Dev. CYE 8654, VLOX wafer
released n-well 6.3 pm).
using
a new
silicon
chemical microsensors for the detection of
example, capacitive
capacitor
cavities
of
electronics
analyte
prior
4.5 shows
a
coating
changes
to
molecules
the front side of
(b)
Fig.
an
interdigi-
with
a
chem¬
the dielectric
smart chemical sensor
its
anisotropically
material, see Chapter 6.3,
etched
cavity
thickness of the
constant of the
polymer and, thus, the capacitance of the sensing capacitor. Au
on-chip sigma-dclta modulator is employed to detect the difference of the capac¬
itance between the
The
polymer-coated
sensing capacitor
is located
sensor
on a
and
an
uncoated reference structure.
released silicon n-well
allow for measurements at different temperatures. A
micro-hot-plate to
meander-shaped polysilicon
heating
resistor is used to heat the released n-well to the desired
temperature.
Since the temperature dependence of the analyte absorption by the polymer
layer
analyte/polymer combination, temperature dependent
additional option to discriminate among different ana-
is characteristic for each
measurements
offer
an
lytes.
nO
4.2 N-well Based island Structures
Soft Contacts for
4.2.2
As shown in
a more or
even
extensive
by
orientation of the
crystal
Related observations
N-well Structure
less thick
after release. This rim
structures
removed
Fig. 4.4,
Improved
can
rim remains around the n-well
be several 10 pm in size and cannot be
overctching.
The rim width is
independent
of the
of the n-well structure.
edge
made
were
p-silicon
Edges
other authors;
by
soft transitions between
regions of a deep- and a shallow n-well released by ECE were found [36]. Obvi¬
ously, p-type silicon remained at the transition after the etch-stop. Furthermore,
p-type substrate material between adjacent deep n-wells placed in
n-well
We
not be
can
assume
n-wells
are
completely
that the
silicon rims and the
p-doped
disconnected from the substrate
of the
junction
overcome
this
the
p+
is not
layers.
In this case,
as soon as
high enough
new
areas
designed
prevented
as
to
contacts
p-doped regions
were
developed.
using
pockets
due
to
p+
contacts via the
developed:
p-well overlapping a deep
a
small
A
the
simple
is not suitable since the contact
the etch-front reaches the contact. The
prevent etching of the
types of
even a
p-silicon and n-well leads to a connection of
potential and, thus, etching of them is stopped.
doping
source/drain diffusions of the processes used in this work (see
121]. Two
strate
the dielectric
problem, special etching
ohmic contact to 'isolated'
would be etched
or
p-doped regions enclosed by
etching potential immediately when
between
substrate residuals to n-well
To
shallow
etched [54].
the etch front reaches the n-well
leakage
a
contacts were
level of
Chapter 1.4)
'boron etch
stop'
soft contacts to 'isolated' sub¬
n-well and recessed contacts
in the n-well. In the first case, the
the
etching
behavior of
etching of the contact is
single crystal silicon in anisotropic
etchants. In the second case, the small size of the contacts prevents them from
being
etched. This is based
gaps between n-well
fingers
both types of contacts
To
investigate
arc
on
the
experience
cannot be
that
etched. In
p-doped silicon in very small
Fig. 4.6, schematic drawings of
shown.
impact of the p-wcll based soft contacts on the etching results,
n-well test structures enclosing a rectangular p-tub area with a size of 160
pm by
110 pm were designed. The p-well of the process was designed to extend over the
the
entire test structure and connected
the
etching potential by metal lines. On one
wafer, the metal line connecting the p-wcJl was cut on every second chip by a sin¬
gle-mask photolithography and etching step: the wafer was covered with photo
resist and exposed through small openings in a mask at the locations of the con-
44
to
4 Fabricated Devices
Etch-stop potential
(a)
N+
Etching potential
Field oxide
P+
P-well
Deep n-wel
P-tub
Deep
n-wel
V
P-substrate
Etching direction
N-well contact line
(Etch-stop potential)
(b)
—
N-well
P-tub contact
(Etching potential)
(a) cross section of a p-well based soft contact
to connect isolated p-tub silicon to the etch potential (dashed lines:
(111)-oriented side-walls, etching is (in theory) stopped at these
side-walls, the n-well edges, and the field oxide and (b) contacts to con¬
nect the p-tub silicon to the etching potential based on recessed pockets
in the n-well (top view).
Fig.
4.6:
Schematic of
passivation above the connecting metal lines was
removed at the photo resist openings using RIE in a SF6 plasma. The metal lines
were etched using a wet aluminum etchant (a mixture of phosphoric acid, nitric
acid, acetic acid). Thus, during anisotropic etching, the p-tub (see Fig. 4.6 (a))
was not connected to the etching potential, i.e., floating, on every second chip.
Etching of the wafer was performed under standard conditions as described in
Chapter 3.2. All structures were overetched for 15 min. Fig, 4.7 shows the test
necting
metal lines. The
45
4.2 N-well Based Island Structures
structure etched with connected and and
Fig.
floating p-well.
With
floating p-well,
a
Photographs of the etched surface of n-well (standard n-well
of CBT, see Chapter 1.4) test structures surrounding a p-tub region with
(a) p-tub region floating and (b) p-tub connected by a p-well
(Dev. CBT 6927), inset: schematic cross-section of the test structure.
4.7:
large p-silicon
the
p-silicon
rim remains. For test structures with connected
rim is
drastically
reduced. In
the test structures etched with connected
shown. A slit of 30 pm
Fig.
4.8:
shown in
p-well.
46
length
Cross-sections
Fig. 4.8,
or
the
the size of
cross-sections of the
edges
of
disconnected
and 20 pm width
of
p-well,
edges
Fig. 4.7; (a) p-tub region floating
etching potential are
crossing the edge of the structure
of
fabricated
and
(b) p-tub
test
structures
connected
by
a
4 Fabricated Devices
was
made
using
a
focused ion beam (FIB). The FIB cut
was
photographed
in
a
SEM under 45°
angle to the surface plane. The FIB cut and the SEM photograph
were performed by Dr. D. Katzer, Fraunhofer Institut für Werkstoffmechanik,
ITalle, Germany. A reduction of the rim size and a major improvement of the
shape
of the
However,
other
a
edge
rim of
be observed in test structures with connected
can
more
than 5 pm remains
hand, the remaining rim
can
dimensions of the n-well in the
is available in
p-tub
design.
easily
for these test structures. On the
taken into account
by reducing
Further information about this
the
experiment
|37].
A test structure similar to the
etching
be
e\en
potential.
one
contacts based on recessed
pockets
in
the
n-well
shown in
pockets
Fig.
4.6
(b)
was
used to
investigate
in the n-well. The metal lines to the
chips on one wafer of
Dev. CYE 8654 using the atxuc mentioned method. In Fig. 4.9, photographs of
structures etched with connected and disconnected etching potential are shown.
Again, for structures with disconnected potential for the enclosed p-tub area sili-
Fig.
were
cut
on
two
Photographs of (a) a n-well grid structure with recessed pock¬
ets in the n-well floating and (b) same structure with recessed pockets
connected to etching potential (Dev. CYE 8654, view to etched surface).
con
4.9:
rims with
strongly
\ar\mg size remain. For structures with connected poten¬
tial the rim size is reduced to around 7 pm with
only
minor variations.
47
4.2 N-well Based Island Structures
In summary, both
types of
contacts
improve
the
quality
of the
edges
tures, thus, the minimum feature size of n-well based structures
around 10 pm.
48
can
of the struc¬
be reduced to
5
Manufacturability
and Yield
Manufacturability
5
Yield
and
yield of more than 85% is today's industry standard in CMOS processing. The
yield of the additional processing steps required for the fabrication of integrated
A
sensors
regular
using
ECE (see
Chapter 2)
should be at least
CMOS process in order to maintain
the total process die
yield FT
is
YT
a
high
as
high
total process
as
the
yield.
yield
In
of the
our
case,
given by
=
(5.1)
rpxEAxEM,
yield of the core CMOS process and YA and EM denote the
yield of the process steps required to prepare for micromachining, and the yield
of the micromaching itself, respectively. Two so-called 'yield killers' were identi¬
where
fied
7P
denotes the
during
•
Short circuits between the contact networks
cal
•
the work towards this thesis:
Breakthrough
only single
this kind. In the
them
of the
anisotropic
etchant into the wafer holder via cracks
diaphragms
dies but whole wafers
following,
the
were
origins
lost due to short circuits and cracks of
of both
yield
killers and ways to eliminate
discussed.
Function of Contact Network
5.1
On
arc
the electrochemi¬
potentials
in micromachincd
Not
providing
a
considerable number of wafers
several Q existed between the metal
Obviously,
chemical
a
prepared
areas
for ECE.
a
of the contact field
short circuit between the two metal networks
potentials
was
present somewhere
low resistance
on
path of
(see Chapter 2.1).
providing
the electro¬
the wafer. On average, 30% of the
49
5.1 Function of Contact Network
wafers of Dev. CBT 6927, CBT 8331, and CYE 8654 showed
this kind,
the
reducing
In order to find the
yield YA
origin
to
short circuit of
a
0.7.
of the short circuits,
a
'hot spot test'
was
performed.
liquid crystal (K15, Merck, clearing temperature
35.2°C), mounted on a hot plate, and heated slightly below the clearing point
(CP). A voltage with a frequency of 1 Hz was applied between the metal areas of
the contact field, yielding a current of 50- 100 mA due to the low resistance
The wafer
path.
was
covered with
a
At the location of the short circuit, the temperature of the wafer increases
due to resistive losses and exceeds
scope with
whereas
polarized light,
with
a
current,
a
areas
applied AC
the
periodically
areas
with
a
Inspected
the CP.
under
a
micro¬
temperature below CP appear colored
temperature above CP appear uniformly grey. Due
grey
area
of
periodically \arying
to the
size shows the location of
the short circuit.
Using
this method, two different kinds of defects
•
•
A SEM
electrostatic
discharge (ESD)
defects
were
found and identified
[55] and
particle-induced short circuits caused by residual
adjacent metal lines carrying the ECE potentials.
photograph
of
an
as
ESD defect is shown in
metal
areas
between
Fig. 5.1.
2 pm
Fig.
with
50
photograph of an
passivation (Dev. CBT 6927).
5.1:
SEM
ESD defect
on
metallization covered
5
Manufacturability
Defects of this kind led to short circuits between metal lines
ing potentials
loss of wafers
design,
other
locations where
at
were
found
the metal lines
large
over
on
they
cross
providing
the
etching potentials
distances. The ESD defects
were
only.
were
created
cesses.
plasmae generated
and the wafer front side
To
investigate
the
to
be
responsible
of the ESD defects,
density
side
using
different
two
PECVD system, Novellus
Systems
long etching time,
the metal
was
passivation
immersed in
were
area
using
optical microscope.
lower
on
machine 2
decided to
use
(1.1
an
machine 2
depos¬
on
the
One
easily
density was
compared
exclusively
to
3.3
passivation.
visible and
can
found to be
cur" on
alumi¬
passiva¬
removed at the defects is much
The defect
cm~~
of the
damage
than the defects itself. Thus, the defects become
an
pro¬
Inc., San Jose, USA, machine 1 and 2 at
tion at the locations of the ESD defects due to the
we
layer
etchant for 30 min. The etchant attacks the metallization below the
to the
of the
deposition equipments (Concept
AMSiAG). After the nitride deposition, the wafers
num
upon the
for the defects.
ited onto the back of test wafers covered with metal 2 and
wafer front
one
deposition system
silicon nitride
a
the
particular
adapted CMOS
between the chuck of the
regarded
are
causing
In the
routed
the etch¬
during deposition
silicon nitride mask onto the wafer back at the end of the
Parasitic
providing
each other. ESD defects
wafers of Dev. CBT 6927
and Yield
machine
Due
larger
be counted
significantly
1). Therefore,
for the back mask
deposition.
all following
Further¬
devices
design rule was stated and applied to
(CBT 8331, CYE 8654). Metal lines providing the etching potentials are allowed
to cross at an angle of 90° only (see Chapter 5.3, rule 3.3). i.e., metal lines carry¬
ing the etching potentials are not allowed to be routed on top of each other on
large distances. After the implementation of this design rule, no further short cir¬
more,
new
a
cuits due to ESD defects
were
observed.
Fig. 5.2, particle-induced short circuits between metal lines carrying the etch¬
ing potentials are shown. Up to three defects of this kind were found on wafers of
In
Dev. CBT 8331. Since the presence of
cessing
cannot be
restrictive
design
avoided (about 0.5
rules must
-
ensure a
a
1
certain defect
cm
high
,
density during
most of them caused
\ield. To avoid
by particles),
particle-induced short
circuits,
the minimum distance between metal lines
carrying the
tials
increased to 20 pm
was
to this rule
Fig.
5.2
exist, if it
was
starting
device pro¬
with the device CYE
necessary for the fabrication
etching poten¬
8654 (some exceptions
of special devices, sec
(b)).
51
5 1 Function of Contact Nctwoik
Photographs of short circuits between metal lines providing
the etching potentials. The short circuit in (a) (Dev. CBT 8331) is obviously
caused by a particle and the short circuit in (b) (Dev. CYE 8654) is pre¬
sumably caused by a photo resist particle present during metal 2 etch.
Fig.
5.2:
The netwoik of metal lines
spacing
lequned by
(dependent
and
the
supplying the electiochemical potentials with the
design iules consumes a significant shaic oi the die aiea
liom the ckruce, up to
10%) This
aiea is
mutually mtei connected Thus, a laige 'die'
formed Laige dies aie veiy susceptible to detects
is
the die useless
In othei
woids, the ieduced
wafct
piesent
on
distnbuted
since one
yield
each step field
ovei
the walci
is
defect may icndei
due to
paiticlc-induced
shoit cncuits between the netwoiks cainmg the electiochemical
potentials
is
a
pnncipal issue We hope that additional design iules foi the electiochemical sup¬
ply will solve the pioblem Foi all futuie designs, the following design iules must
be obeyed to eliminate shoit cncuits between the etching potentials as fai as pos¬
sible
paiallel running metal lines piovidmg the etching potentials have to
designed on diffeient metal levels and must ha\c a minimum lateial spacing
be
ol
20 |im
Using
a
lathci
tune-consummg pioceduie,
'îepaned' do this end, the watei
exposed thiough a 100 pm hole m
shoit cucuit
lemovcd
a
numbei
a
aluminum foil
SF6 plasma
subsequcntl}
using
lemoval of fhe shod cucuit by
a
a
ot
co\eied with positive
fhe metal
wet
was
photo
could
be
icsist and
icmoved at the îesist
causing the shoit cucuit
aiea
aluminum
focused lasei beam
wafeis
mask' at the location of the
dhe passrvation abo\c the shoit cucuit
openings using RIE with
was
was
a
etchant
w as
In
earned out
some
cases,
5
Stress of Dielectric
5.2
During postprocessing
wafers
were
Manufacturability
Layers
of the first device of this work (CBT
lost due to cracks in
and Yield
diaphragms consisting
6927),
a
number of
of the dielectric
layers of
the CMOS process. Due to the cracks, the etchant enters the wafer holder and
immediately destroyed
the
exposed
The stress in the dielectric
Therefore, the
stress of
layers
metallization
on
suspected
to
was
all dielectric
determined
layers
origin
of the cracks.
of the processes CYE and CBT
deposition using a
Corp., San lose. USA).
mechanical
The
layers
stylus
(see
that, single
the difference in the wafer curvature
measured before and after the
(P-10, KLA-Tencor
be the
the wafer curvature method. For
Chapter 1.4) was
using
dielectric layers were deposited and
filer
the front side of the wafers.
was
surface pro¬
deposited
the layer to
were
on
be
prepared test wafers covered with the dielectric layer on which
investigated is deposited in the standard process, e.g., for the stress measurement
of the passivation, test wafers covered with the intermetal dielectric (PEOX) were
used. Additionally, high temperature processing carried out during the standard
process after the
gate/metal
deposion
1 dielectric
of dielectric
(BPSG)
were
tion of the individual dielectric
layer.
All dielectric
layers
stress and the
thicknesses of the
were
layers,
e.g., densification and reflow of the
included in the
processing
after the
deposi¬
found to have
compressive residual stress. The residual
dielectric layers are summarized in Fig. 5.3. The
0
-
-100
1
LU
Q_
i
CD
cd
-"
Q_
i
-
-500
-200
:
1
03
"300
-400
X
o
CO
-200
-100
X
(3
X
Q
2
o
u~
o
CD
Q_
CQ
CL
-
X
LL.
Q_
-500
oxide,
tF0X
=
CYE
Stress in dielectric
5.3:
cesses.
-~
Z
Q_
o
CBT
Fig.
LU
-300
-400
-
(D
FOX denotes field
and
6700
PND
Â, tBPSG
layers
oxide,
in the CBT and CYE CMOS pro¬
BPSG contact oxide, PEOX intermetal
the
=
passivation. Thicknesses of
7700 A, tPE0X
11000 Â, and tPND
=
the
=
layers
11000 Â.
are
53
Design
5.3
Rules
passivation
400 MPa.
100 MPa
of the CBT process showed
a
very
high compressive
Deposition of the low-stress passivation
compressive) on CBT devices instead of
stress of around
of the CYE process
the standard
passivation
found to be efficient to prevent cracks in micromachined dielectric
In
(around
was
diaphragms.
the standard CBT
passivation was used to create buckling of sili¬
con diaphragms in wafers of CYE devices intentionally. Buckled diaphragms of
this kind were used for an ultrasonic proximity sensor system 146] (see
Chapter 4.1). Using buckling, the vibration amplitude of the diaphragms can be
some cases,
increased.
5.3
As
Design
consequence of the discussion about
a
developed
to
ensure
Design
rules
prising
different
bility
The
Rules
are
the
rules
for, e.g., spacings, angles, widths of layers, levels (com¬
layers),
between ECE and
design
yield killers, a set of design rules was
manufacturability of silicon microsystems using ECE.
rules stated below
were
on
the wafer
can
First of
all, the fabrication of silicon
lead to the loss of the
•
Back side mask
•
N-well
layer
layers,
Diaphragm
causing,
wafer, the rules
sensors
arc
using
are
experience
of the pro¬
CBT
6927/8331,
(Dev.'s
e.g,
a
breakthrough
of the
very 'conservative'.
ECE
requires
the definition of
levels and structures:
to
be used for micromechanical structures, referred to
as
layer
levels:
(I) diaphragms consisting of dielectric layers, (IT) nwell silicon diaphragms, (III) silicon n-well structures suspended by
dielectric
layers.
diaphragm
metal oxide
level
is
The
diaphragm
level
comprise
different
layers,
of type (I) consists of field oxide, contact oxide
layer,
and
ld given by
mask underctching
54
from the
compati¬
required.
ensure
layer
structural n-well
•
developed
between 1996 and 1999
etchant
number of additional
to
CMOS, special additional design rules
cessing of 3 engineering runs
CYE 8654). Since one defect
a
(e.g., contacts). In order
or structures
the
passivation layer.
opening
layer,
The dimension of the
of the mask
on
the wafer back
e.g.,
a
inter
diaphragm
/m,
the back
//, and the thickness d of the wafer in the form
5
/
?1_
m
tan(54.7°)
+
Manufacturability
(5.2)
2m
•
Metal lines used for the distribution of electrochemical
•
Ohmic contact structures to
the metal lines to the structural n-wells and the
The
developed design
rules for the
newly
defined
summarized in Table 5.1. All standard process
mentioned above must be obeved
structures
Table 5.1
Design
:
Layer/Level/
potentials
the electrochemical
supply
as
and Yield
potentials
from
p-substrate
layers, levels, and structures are
design rules for the layers and
well.
rules for ECE
Basic Rules
Cause
1.1 Min. width: 10 pm
Precision of back
Structure
Openings
in
side
back side mask
layer
1.2 Min.
spacing
ings:
200 pm
1.3 No
of open¬
lithography
Mechanical
Convex
convex corners
stability
corners
of wafer
will be
stronglv underctched due
the
Diaphragm
level
(1):
Diaphragms
consisting of
dielectric lay¬
ers
only
2.1 No
opening
oxide
2.2 No
of the etchant
Field oxide is etch stop
field
layer
layer
opening
layer
m
anisotropy
to
in contact
and intermetal
Mechanical
stability
of dia¬
phragm
oxide
2.3 No metal 1
on
the level
Safe distance of lines carry¬
ing etching potentials
area
from
etchant
2.4 Max. size: 500 pm
500 pm
by
Larger diaphragms my break
due to
compressive
dielectric
stress
of
layers
55
5.3
Design
Table 5.1
Rules
Design
:
Layer/Level/
rules for ECE
Basic Rules
Cause
Structure
Diaphragm
level (II):
2.5 Min.
tural n-well
closed silicon
diaphragm
diaphragms
100 pm
Diaphragm
level (III): sili¬
con
2.6 Min.
pended by
phragms
according
through
of
2.7 Max.
dia¬
contact to the etchant due to
defects
or
between
diaphragm
and
urn
and substrate after
see
between
diaphragm
Chapter
Stability
and
2.8 Min.
spacing
between
n-
2.9 Max. space n-well and
n-well: 80 pm
preferably
tribution of the
metal lines for
electrochemi¬
strate
potentials
of dielectric dia¬
of n-well struc¬
Separation
tures after
etching,
4.2
of dielectric dia¬
Stability
phragms
metal 2,
p-sub¬
preferably
metal 1
3.2 Min. width: 25 pm
(main lines)
3.3
Lines have to carry
Crossings only
degrees
under 90
Minimum
carrying
overlap
different
to
Chapter
lines
spacing
between
carrying different
potentials 20 pm
of lines
etching
prevent ESD
induced short
3.4 Min.
etch-stop
current
potentials
56
see
3.1 Metal lines for n-wells
used for the dis¬
cal
etching,
4.2
phragm
Chapter
layers
of
of n-well structure
Separation
well and n-well: 50 pm
Metal
misalignment
n-well: 80 pm
2.1
2.4
of
silicon
level:
spacing
edge
Protection of circuits from
back mask
n-well: 50
structures sus¬
over
spacing
edge
n-well
of struc¬
overlap
circuits,
5.1
Prevention of
particle-
induced short circuits,
Chapter
sec
5.1
see
5
Table 5.1
Design
:
Layer/Level/
Manufacturability
and Yield
rules for ECE
Basic Rules
Cause
4.1 Min.
Protection of contact from
Structure
Ohmic contact
structures to
spacing between
diaphragm edge and
structural
contact structure
n-
wcll and sub¬
strate:
strate
4.2 Min.
on
spacing
structures: 30
By
now, most of the
the
design.
defects in-
spacing
or
of contact
Protection of contact from
the etchant
edge
n-well
pm
between
Prevention of
voftagc drop
electrochemical
125
along
urn
rules stated here
are
potentials
structures
checked
by
visual
inspection
DRC checks the
potentials.
The electronic
ECE DRC is
design
for short circuits between the electrochemical
implementation of the other rules to form a complete
Fig. 5.4, design examples and the appropriate design
planned. In
rules are shown. Fig. 5.5 shows a contact structure to be used as ohmic
for the connection of the potentials to n-well and substrate, respectively.
an
of
design rules are already implemented into an electronic Design
(DRC) working on CADENCE design software. As an example, the
developed
As
of
Some
Rule Check
5.4
of
misalignment
contact structures:
design
case
of back mask
suspended
4.3 Max.
sub¬
50 pm
structure to n-well
for
the etchant in the
contact
Polymer Coatings
additional
breakthrough
protection
for the wafer front side and the wafer holder
of the etchant,
against
polymer coating deposited prior to micromachin¬
ing was developed. Pol}mer coatings except Teflon® based ones have certain
advantages over other protective coatings such as silicon nitride layers [56]. They
can, e.g., easily and selectively be removed after micromachining by dissolution
in
organic
solvents
or
ashing
a
in
an
oxygen
plasma.
57
5.4
Polymer Coatings
IS ill :i; Hi
::i
;;:
i:i
::l
iii
:::
US
:i:
:::
;:;
:::
::
::!
:::
'::':
':":
::':
:::
:::
:::
si
:::
::
:::
..
8t
!H
CD
''"
'
ËÏ
CO
i
Closed silicon
ä
»
diaphragm
»
H—
O
Jû
'
BS
N-well
I
Diaphragm edge
!••:•
Backside mask
«I
k
:
j
11
4.1
Fig.
5.5
X
Metal 1
\
in
2.5
(1.1-1.3)
see
V
EU
H !!:
:::
:::(:::I:::
:::
:::
:::
:::
ill
:::
Ii:
:::
lis
:::
:::
:::
2.3
Metal 2
i
i»
1
B
I
»
1
:::
|
!"*
I
_
B»
jif
git
!::
iii
:::
si!
iii
;::
.
N-well
*
II:
iii
i
*
HI
::
»55
i
fc--
HI
S
:::
us
i:i
:::
:::
:::
m
ii:
1
til
h:
.
- ,
_
_
—
.
,
.
^VÄ
J
:::
iii
SSS3
**a
Backside masl <
(1.1-1.3)
Fig.
5.4:
tures with
58
vJ
,
£~~
.
\J
t
:=:
I!!
K!
.
s«
In
Ss
It
2.6,2.7
-*-
Schematic of silicon n-well
applicable design
rules.
5":
••
Diaphragm
edge
m
4.2
- «#~
diaphragm
and n-well island struc¬
5
Active
*"—«—.
Manufacturability
area
(opening
Fig.
ECE
In
Recommended
5.5:
potentials
first
contact
to n-well and
experiments,
in field
oxide)
High dose implant
(source/drain implant)
Contact
tact
and Yield
openings (openings
oxide) 2 pm by 2 pm
in
structure for the connection
con¬
of the
substrate, respectively.
10 pm
thick
polyvinylidcnfluoride/trifluoroethylene
(PVDF/TrEE) copolymer layer deposited by spin-casting a 10% solution of
PVDF/TiFE in cthylmethyl ketone was used. PVDF/TrEE layers as protective
coatings during KOH-etching were investigated for the first time in [57]. A good
chemical stability of the layer against the etchant was observed. On the othcr
hand, rapid delayering of the coating at locations on the wafer where the etchant
penetrates the wafer through cracks in the diaphragms was found. Therefore, fur¬
ther research focused on the reduction of the delayering of various polymer coat¬
ings by the use of surfactants. Test wafers coated with standard silicon nitride
passivation were prepared to investigate the underetching of the coating. (Almost
all
area on a
a
fully CMOS-processed
wafer is covered with the
passivation).
The
coating layer deposited on the wafers was damaged by a number of approxi¬
mately 1 cm long scratches reaching down to the nitride layer. The wafers were
subsequently immersed into a 6M KOH solution at 90°C for different times. After
that, the delayering of the coating at the scratches was measured using a micro¬
scope.
All surfactants
investigated belong to the group of the fluorosilancs (Rn Si X4.n).
These surfactants were subject of extensive research since they are applied to
enhance adhesion between glass fibres and polymers in fibre-glass enforced res¬
ins [581. The basic principle of the adhesion enhancement by fluorosilanes is that
59
Polymer Coatings
5.4
Rn couples
with
a
surface
Fig. 5.6,
a
polymer layer and the hydrolyzed Si X4.n group reacts
containing (hydrolyzed) silicon atoms via siloxane bonds. In
to the
cover
simplified
schematic of these reactions is shown. The combination of
OC2H5
R
OH
Hydrolysis
I
Si-OH
R
Si-OC2H5
I
I
OH
OC2H5
HO-S
R
HO-S
HO-S
OH
Si_OH
HO-S
OH
HO-Si
HO-S
OH
Condensation
1
R
Si
O
AH
HO-S
Si-Substrate
+
5.6:
Schematic of chemical reactions
leading
rosilane-based surfactant (a triethoxysilane) to a
organic rest R couples to the polymer layer.
5 pm thick PMMA
layer
S
-
HO-S
HO-Si
Fig.
a
as
polymer coating
and
to
HoO
bonding
silicon
of
a
fluo-
surface. The
(1FI. 1H, 2F1, 2H) perfluorode-
cyltriethoxysilane (FSE) as surfactant showed the lowest delayering rate of
2 um min"1 [39]. Thus, the organic coating exhibits a similar delayering (or
underetch-) rate as a good-quality silicon nitride layer (approx. 5 pm min"1).
Using a coating of this kind, fully processed CMOS wafers may be anisotropi¬
cally etched without a wafer holder. The surfactant was deposited by spin casting
a
0.5% solution of FSE in
slightly
acidified
ried out under
(pll
=
a
95%
5% Dl-watcr mixture which
5) with acetic acid. Mixing of the components
nitrogen atmosphere
surfactant molecules. The mixture
60
isopropanob
in order to avoid
was
allowed to
was
was car¬
self-polymerization of the
stand for 2 days for sufficient
5
hydrolyzation.
The mixture should
merization of the surfactant.
was
be used after 5
Baking
of the
primed
carried out to create the siloxane bonds. The
surface
the
not
was
primed
increased
by
vv
days
hydrophobic.
and Yield
because of
self-poly¬
wafers at 120°C for 15 min
atcr contact
this treatment from around 30° to
wafer surface is very
by spin casting
Manufacturability
The PMMA
angle
more
on
the wafer
than 100°.
coating
was
Thus,
deposited
commercially available solution (XARC PC 5000/4, Allresist
GmbH, Berlin, Germany) on the primed wafer surface. Spin casting was carried
a
1000 rpm.
out at
Subsequently,
the
layer
baked for 10 min at 165°C. The
was
mechanical adhesion of the PMMA
delayering
with
rate
increasing
of the PMMA
contact
angle
coating was poor. As a general tendency, the
coating in 6M KOH solution at 90°C decreases
of water
mechanical adhesion of the PMMA
on
the
coating
primed
surfaces.
decreases at the
Surprisingly,
same
the
time.
Because of the
complicated priming procedure using FSE, the commercially
available surfactant Diphcnylsilancdiol (AR 300-80/10, Allresist GmbH, Berlin,
Germany) was used for 'all-day' micromachining (see end of Chapter 3.2).
Wafers primed with AR 300-80/10 and coated with PMMA showed a delayering
rate
of 60
using
pmmhC1
FSE.
which is 30 times
Nevertheless, the delayering
higher
rate
than the
is small
delayering rate obtained
enough to protect the wafer
front side and the wafer holder for several minutes after
an
accidental KOH
breakthrough.
The reduction of the stress in the stack of dielectric
layers using
sivation in combination with the
resulted in
micromachining yield FM
protective coating
to almost 100%.
lost anymore due to cracks in
diaphragms
By using
and
both
a
low-stress pas¬
an
increase of the
methods,
no
wafer
subsequent breakthrough
was
of the
etchant.
61
5.4
62
Polymer Coatings
6
Compatibility
Issues Between Sensor- and IC Device
\^01V1Jl A. A AJtSAJLiA A \
O
Technology
AÄölJAt/k,ll
Between Sensor-
and
IC
Device Technology
A number of
incompatibilities between CMOS device technology and ECE
appeared during the work towards this thesis. Integration of sensors fabricated
using ECE into CMOS devices requires to overcome these incompatibilities. The
most
important
are
listed below.
CMOS
1
Wafer stepper
ECE
lithography
Distribution of ECE poten¬
tials
of
on
the
wafer; creation
macroscopic contact
field to apply the ECE
potentials to the wafer
2
Residual stress in
and grown
3
Internal
crystal
4
deposited
layers
gettering by
a
Buckling
and cracks in
mi crom ac h i ned d i aphragms
bulk
defects
Prevention of
latch-up by
epitayial layers on heavily
B-doped substrates
Poor
quality
of etched cavi-
tics
'Boron
etch-stop [21]'
Compatibility problems (1) and (2) were adrcssed already in Chapter 2.1 and
Chapter 5.2, respectively. In this chapter, topics (3) and (4) arc discussed. Espe¬
cially, problems related to defects in silicon wafers and their influence on the sen¬
sor
fabrication
by
wet
anisotropic etching
arc
adressed in this part.
63
6.1
Quality
of Wet Etched Cavities in Processed CMOS Wafers
of Wet Etched Cavities in Processed CMOS
Quality
6.1
Wafers
Wet etched cavities
in wafers of the first device
towards this thesis (CBT 6927)
this kind is shown in
Fig.
6.1
large
Silicon
:
craters were
Fig.
w ere
found.
distorted
cavity side-walls
the outer
boundary
such
of
a
as
were
their
cavity
is
and
ECE
(Dev.
a
CBT
A
the work
cavity of
the cavities
6927).
strongly varying underetching
observed. The intersection line between the
diaphragms
forms
the contours of fabricated silicon
result, the physical properties of the diaphragms,
frequenc} vary from one device to another. A closer view
shown in Fig. 6.2. The ciater structures show a hexagonal
symmetry. The density of
64
large
diaphragms. Thus,
distorted. As
side-wall
a
using
and the bottom surlace of silicon
of silicon
resonance
was
quality.
(lll)-oriented side-walls of
fabricated
Furthermore,
of the silicon nitride back mask
diaphragms
found to be of very poor
6.1. In the
diaphragm
processed during
craters
is
reduced close to the
diaphragm
surface.
6
Compatibility
Issues Between Sensor- and IC Device
Technology
Wafer back
Diaphragm
Fig.
6.2:
fabricated
surface
Micrograph of a (111)-oriented side-wall of
using ECE (Dev. 6927). The structures in the
etched
an
side wall
cavity
are cra¬
ters, i.e, depressions.
At the transition between bottom surface of the
30 pm wide rim with
found. The
origin
diaphragm
thickness of around 20 pm and
a
of this rim is not clear. It
was
observed
a
and
side-walls,
smooth surface
only
20-
a
was
in wafer material
high delect density, i.e., high etch rate in the (111) orientation. During
overetching, i.e., stopped etching in (100) orientation and further etching in (111)
orientation, the rim is gradually released.
with
At
a
first, it
assumed that the
high etching temperature (90°C) caused the irreg¬
ularities in the side-walls. However, etching of a wafer at 60°C did not result in a
better quality of the cavities. At second, the high temperature steps during IC
pro¬
the
of
such
well
drive-in
as
wafers,
cessing
anneals, were regarded as the origin
was
of the poor
quality
of the cavities. Secco
sections revealed that
cessed
samples
entially
etched
a
large
[59] etch experiments
number of bulk
crystal
defects
on
arc
wafer
cross-
present in pro¬
whereas
unprocessed samples were defect-free. Furthermore,
etched cavities in unprocessed wafers were of good quality. After preferential
etching of cavity side-walls in processed wafers, etch figures typical for bulk
stacking faults were found in the centers of the craters. A micrograph of a prefer¬
cavity
side-wall is shown in
tal delects in Czochralski (CZ) silicon is
Fig.
a
6.3. The
generation
side-effect of the
oxygen. The concentration of interstitial oxygen in
CZ-grown
of bulk crys¬
precipitation
silicon is
of
higher
65
6.1
Quality
Fig.
of Wet Etched Cavities in Processed CMOS Wafers
Micrograph of a preferentially etched cavity
stacking faults (lines) and dislocations (dots).
6.3:
bulk
side-wall
showing
than its solid
solubility. Therefore, the oxygen precipitates (in the form of
particles) during annealing. Defects caused by oxygen precipitation are
oxide
com¬
used for the gettering of transition metal
monly
impurities, such as copper, iron,
and nickel. During high temperature processing, oxygen diffuses out of the
wafer, thus, leaving a defect free zone for the devices at the surface. In the bulk of
the
wafer,
stacking
a
of oxygen
high density
faults and
dislocations,
are
precipitates
and
technologies
CBT and CYE (see
Chapter 1.4)
starting
(Wacker
Sdtronic AG,
8.0
2.45
10
I 1
•
1017cur3.
All
determined
by
the
Burghausen, Germany) according
to
the
were
ASTM F121-83 standard. (In order to obtain concentrations in
•
as
material for the pro¬
is about
concentrations of interstitial oxygen used in this thesis
manufacturer
such
present.
The interstitial oxygen concentration of the standard
cess
secondary defects,
cm-3,
factor of
a
^
enr3
was
used
by Wacker).
investigate the influence of the interstitial oxygen concentration on the quality
of anisotropically etched cavities, wafers with initial interstitial oxygen concen¬
1017cnr3 and 8.3-9.3 1017crrT3 were treated with
trations (O,) of 6.7-6.9
To
•
various
high-temperature
cavities in wafers with
quality
very
as
good
as
the
long annealing
an
CMOS
processing steps [60].
oxygen content of 6.7
quality of
--
cavities etched in
6.9
•
It
was
found that etched
I017cnr3
unprocessed
have
a
wafers
surface
even
for
times at 1150 C. Cavities in wafers with interstitial
oxygen
concentration of 8.3 -9.3
66
•
•
1017cirf°
were
of similar
quality compared
to cavi-
Compatibility
6
ties obtained in
Recently,
Issues Between Sensor- and IC Device
fully processed
another
investigation
wafers with standard oxygen concentration.
of cavities in CZ wafers with
oxygen concentration from 6.75
10
•
cnf,
to 7.75
•
10
thermal oxidation and LPCVD (Low Pressure Chemical
reported [61].
A
comparison
simulation of
a
bipolar
process
interstitial
processed
with
Vapor Deposition)
(O,
=
4
•
10
a
was
cm
)
specified oxygen concentration given a thermal
was presented [62]. In both investigations, wafers
with the lowest concentration of interstitial oxygen
In the
differing
cm"'
of cavities in Float Zone (FZ)
and CZ material with not well
Technology
yield
cavities of best
quality.
detailed
investigation of the influence of the interstitial oxygen
concentration and thermal processing on the quality of anisotropically etched
cavities is presented. Furthermore, external gettering using poJysilicon back sides
(PBS) and back side damages (BSD) is investigated as a replacement for internal
gettering using bulk crystal defects. In order to give an introduction into the field
of oxygen precipitation, the theory of nucleation and growth of oxide precipitates
in silicon is briefly described. The argument follows 163,64].
following,
a
6.2
Nucleation and Growth of
During
CZ
rial
growth
of silicon, oxygen
(silica) is incorporated
solubility
Oxygen Precipitates
in the
originating from dissolved crucible mate¬
crystal lattice at interstitial positions. Since the
of oxygen in silicon decreases
strongly
with the temperature, as-grown
CZ silicon is
supersaturated with oxygen. An introduction into the field of super¬
saturated solutions is given in. e.g., [65]. The temperature dependent equilibrium
solubility c,eq of oxygen in silicon is given by 166]
cf9
The oxygen
solubility
as a
=
7.28x10
cxp
J^±±l
(6.1)
.
function of the temperature is shown in
ing
thermal treatments carried out in
ing
the
Fig.
6.4. Dur¬
IC-processing, such as well drive-in anneals
and oxidations, the oxygen tends to precipitate as
SiOx particles. Oxygen precip¬
itate nuclei are formed at temperatures exceeding 400T. It is widely accepted
that nuclei are already present in as-grown wafers [671. They arc generated dur¬
cooling-down period
leave their interstitial
of the
positions
to
crystal. During nucleation.
form
a
SiOv
molecule with
oxygen atoms
an
atom
(O,)
from the
67
6.2 Nucleation and Growth of
Oxygen Precipitates
1E+19
Melting
Tem¬
perature
Supersaturation,
o
at1100°C
>>
5
1410°C
i
IG
1E+18
CO
1E+17
O
to
c
CD
CD
>.
1E+16
X
O
1E+15
600
800
1000
1200
1400
Temperature [°C]
Fig. 6.4:
straight
Temperature dependent solubility of oxygen in silicon. The
line indicates the oxygen concentration of the standard starting
material for the CMOS
regular silicon
technologies CBT,
lattice. Recent
investigations
CYE
(see Chapter 1.4).
have shown that
The volume of the oxide molecule is about twice
large
x
is close to 1
[68].
the volume
occupied
by a silicon atom in the regular lattice. Therefore, a strain field developes around
the precipitate nucleus. It can be partially relieved by punching another silicon
atom from its regular lattice site into an interstitial position. In Fig. 6.5, a sche¬
matic of the nucleation of oxygen precipitates is shown. Absorption of vacancies
o o o o o o o ooo
o o
op
o o o OOO
o o cro o o o OOO
o o o o o o o ooo
o o o o o o o
o
o o o o o o o
oo
o o o o o o o ooo
Fig.
tate
68
as
oooooooooo
OOOOOOOOOO
OOOOOOOOOO
oooooéèoooo
oooooooooo
oooooooooo
oooooooooo
as
o o o o o o o o o o
o o o o o o o o o o
oooo oooo op
éè o cro
oooo oooooo
oooo o o o o o o
oooo oooooo
o o o o o
(1) Oxygen at
interstitial posi¬
(2) Monomolecular
(3) Punching
oxide
silicon self-interstitial
tions
nucleus
precipitate
out of
to relief strain
Simplified Schematic of the formation of an oxygen precipi¬
nucleus; grey: silicon atoms, black: oxygen atoms.
6.5:
6
V from the
Compatibility
crystal
For the sake of
Issues Between Sensor- and IC Device
Technology
lattice
surrounding the precipitate can also relieve the strain.
simplicity, the contribution of vacancies is neglected in the fol¬
lowing.
The combined law of
oxide
mass
and volume conservation for the nucleation of
can
be written
2Si
+
precipitate
20t
=
an
as
Si02
+
ßl
(L-ß)Sistiain
+
(6.2)
.
Here, the simplifying assumption is used that the volume of an SiO molecule is
Q0x 2QSl 2 1/(5 10—) 4 iO^nrO The quantity ß denotes the number
=
-
•
=
•
of silion self-interstitial s 1 emitted
during growth
quantity (1-ß) Sisliain dcsciibes
compressive stress in the silicon lattice.
ecule. The
a
The Gibbs free energy of
a
precipitate
the residual volume
nucleus ha\
3
AG
=
of the nucleus
ing
by
Si02 mol¬
deficiency causing
the radins
r
density.
4itrV^Gp-ß^GT
The next two terms of the
tional to the volume of the
growing
is the chemical energy released
supersaturated
to
punch
out
by
+
G,lldm
expression
nucleus (volume
the
precipitation
arc
silicon
given by
of
an
(6.3)
,
the surface
ö as
contributions propor¬
energies).
solution, 'fhe
one
is
3
where the first term is the surface energy of the nucleus with
energy
one
The
quantity Gp
oxygen atom from the
quantity G} describes the chemical
atom from a regular lattice site into an
energy
required
interstitial
posi¬
tion. The energy due to the residual strain in the lattice is taken into account
Ggfraiir
The chemical
energies GP
and
Gj
are
<
Gp
=
given
C
recl
the
expressions
^
k/ln
,
by
by
(6.4)
,
and
69
6.2 Nucleation and Growth of
Oxygen Precipitates
Gï
kr In
=
(6.5)
,,eq
respectively. Here, c-x is the interstitial oxygen concentration with its equilibrium
value (solubility limit) ccc\ (see Eqn. (6.1)). The concentration of silicon selfintcrstitials is denoted by q with its equilibrium value coqT. In both equations, the
expressions under the logarithm give the supersaluration of the species Oj and I.
Because of
a
positive (surface)
and
maximum. This maximum
radius rcui of the nucleus. A
Fig.
of cx
6.6. A surface energy
-
8
•
10
cm~°,
and
corresponds
plot
density
a
negative (volume) contributions, AG(r)
to
a
temperature dependent critical
of AG for different temperatures is shown in
of
G
=
0.67 Jirf-
[691,
an
oxygen concentration
small contribution due to interstitial s and strain
assumed for the calculation. G reaches
a
energy is lower for
rcu[ .indicating that nuclei with
both,
shrink and nuclei with
r
r <
>
exhibits
rcnt and
r >
maximum for
rcnl grow at the
r=
rcli(,
were
i.e., the free
corresponding temperature.
r <
If
a
rrcut
CZ
5E-17
1150°C
to
13
_CD
Ü
13
C
"o
0
E?
CD
C
CD
r=rcnt(1150°C)
CD
CD
lOSO'C
800°C
-5E-17
0
3
Radius of
Fig.
6.6:
Calculated free energy of
of its size and
70
precipitate
temperature.
a
6
nucleus
precipitate
[nm]
nucleus
as a
function
6
Compatibility
silicon wafer is
Issues Between Sensor- and IC Device
brought instantaneously
to a
temperature of, e.g., 1150°C,
fraction of the nuclei present in the wafer will shrink. This is
Thermal Anneal (RTA) treatments described later in this
hand, annealing
at lower
nuclei to grow. After
exploited
chapter.
large
Rapid
a
in
On the other
temperatures around 800°C allows smaller precipitate
annealing,
their size is
large enough
processing
higher temperatures.
growth during subsequent
device
The critical radius rcrjt
be determined
can
Technology
at
to allow
by setting d(AG)/dr
for further
to zero. It
takes the
form
gQ
cnt
Ox
(6.6)
/-.eq \ß\
/
kiln
VL
A
plot
and
of rcrjt
Q.0x
=
.eq.
(77) is shown in Fig. 6.7.
2QSj
were
V
6i
J
negligible supersaturation
A
of I,
ß
~
1,
assumed for the calculation. Note, that the radius of the
nuclei is of the order of
a
nanometer,
thus, they contain only
a
small number of
oxide molecules.
w
zs
_CD
ü
13
CO
X3
CO
0
600
700
800
900
1000 1100 1200
Temperature [°C]
Fig.
6.7:
Calculated critical radius of
an
oxide
precipitate
nucleus
as a
function of the temperature.
71
6.2 Nucleation and Growth of
Oxygen Precipitates
The nucleation rate./ of nuclei
having
of
a
nucleus of critical size rcril.
rcnl
can
According
to
be calculated
using
the free energy
the classical nucleation
theory,
J is
given by
y
D-x
=
0.13 exp
silicon, d
=
0.235
where
is
which
C\
=
8
•
10
cirr°,
crexp|
Cj- exp
)4*r-rilZ-
^-~
(6.7)
,
] [66] is the diffusivity of oxygen in
the atomic distance in silicon, and Z the Zeldovich factor
(-2.53 eV/k?) |cnrrs
nm
priori
a
=
unknown.
and small
A
plot
of
supersaturation
the
nucleation
rate
for
of interstitials is shown in
Z=l,
Fig.
6.8.
1E11
CO
CO
1E10
^
CD
CO
1E9
c
.2
CO
_ÇD
O
13
1E8
400
500
600
700
800
900
1000
Temperature [C]
Fig.
6.8:
Calculated oxide
precipitate
nucleation rate
as
a
function of
the temperature.
The maximum nucleation rate is reached for
Thus, processing
at
lower temperatures
secondary
72
defects
temperature slightly above 700°C.
moderate temperatures, such
around 800°C for Local Oxidation of Silicon
at even
a
during
are
further
as a
silicon nitride
(LOCOS)
or
deposition at
polysilicon deposition
critical for the nucleation and the
processing
at
higher temperatures.
generation
of
6
As shown
cipitates.
variety
and needles
cipitate
P
of
governs the
containing /
growth
2Si
available in the silicon
cipitate
+
201
crystal.
be calculated
using
mental data (see
[71]). In
or a
large
as
A
large
by
the
slightly
140
a
precipitate. Considering
a
pre¬
P/
by
1
+
+
ßI
(l--ß)Sistiain.
+
(6.8)
the diffusion of the interstitial oxygen atoms
For the
giowth time
the size of
t,
a
spherical
pre¬
a^D^-c^t
=
(6.9)
a
expression are in reasonable agreement with experi¬
Fig. 6.9, the calculated growth of oxide precipitates
NMOS- and
below 26
nm were
pre¬
this
well drive-in anneal
process is
large
as
nucleus into
start with base oxidation and nitride
tion
grow to form
spheres, octahedrons, platelets,
literature [70]. An equation similar to
the
a
such
can
as
Calculated values
the front-end of
=
is limited
r
during
of
(7)
fclit
Technology
SiO molecules, it has the form
precipitate growth
can
r >
precipitate shapes,
described in
were
Py +
The
Issues Between Sensor- and IC Device
above, precipitate nuclei with
A
Eqn. (6.2)
Compatibility
a
deposition
(CMOS).
nm
obtained
CMOS process is shown. Both processes
The final
followed
by
precipitate
either
a
field oxida¬
size after the NMOS
whereas for the CMOS process
(refer
to
experimental
results in
precipitates
Chapter 6.3.2).
as
strain is present in the
surrounding crystal lattice due to the growing
oxide precipitate. The strain can be partially relieved by the emission of silicon
self-interstitials I (see Eqn. (6.8)). The compressive stress in the crystal lattice
generated by the residual strain can nucleate extrinsic stacking faults which grow
arc
absorption
inserted
sequence in
of the emitted inteistitials. Extrinsic
circularly
or
stacking
hexagonally shaped {111} planes.
The
faults in silicon
regular stacking
(11 l)-oricntation of ...A-A-B-B-C-C-A-A... is replaced by, e.g., ...A-
A-B-B-B-B-C-C-A-A.... The strain may also be relieved
matic dislocation
additional
a
layers
loops.
of silicon
sequence of dislocation
atoms
of
is
given
in (110) direction.
is emitted in the
loops
Punching System (PS).
forming a
ondary defects
quality
An
by punching out pris¬
extrinsic, perfect dislocation loop surrounds two
A detailed
During prismatic punching,
{110} orientations of the crystal
description
in [701. The influence of these
anisotropically
etched cavities is the
subject
of the
generation
secondary defects
of
sec¬
on
the
of the next section.
73
6.3 Influence of Bulk
Crystal
Defects
the
on
Quality
of Etched Cavities
150
1150 C
E
100
1000°C
0
N
"to
Final
CD
sizes
+-
CO
/
50
"o.
"o
precipitate
CD
et
0
0
10
5
Annealing
Fig.
6.9:
of
a
NMOS process and
A
phenomenon
Calculated
growth
a
of
Time
an
[hrs]
oxide
CMOS process
related to the
20
15
precipitation
precipitate during the
(Oj 8.0 1Q17cnr3).
=
front-end
•
of oxygen
be observed
can
thermal oxidation of silicon surfaces. Interstitials emitted
by
during
the oxidation
give
rise to the
growth of oxidation induced surface stacking faults (OiSF) nucleated
by damages of the crystal lattice or impurities (refer to Chapter 6.4.2). Further¬
more, the residual
con
compressive
stress is
(by part)
relieved
by bowing
of the sili¬
sample.
Influence of Bulk
6.3
Crystal Defects
on
the
Quality
of
Etched Cavities
In this
section,
a
comprehensive study
on
the surface
quality
of etched cavities in
wafers with four different interstitial oxygen concentrations
mally
cess
simulated CMOS process is
presented.
to
a
ther¬
The thermal simulation of the pro¬
includes all temperature steps
Common
performed at temperatures above 430°C.
as potassium hydroxide (KOH) and tetrame-
anisotropic etchants. such
thyl ammonium hydroxide (TMAH) solutions,
were
in the wafers. The influence of various kinds of bulk
74
exposed
used to create
deep
crystal defects,
such
cavities
as
pre-
6
Compatibility
cipitatcs, dislocations,
and
of the etched cavities is
the
cavity
Issues Between Sensor- and IC Device
stacking faults,
investigated
side-walls is discussed
525
ber
oxygen
ranging
from 6.0
10
•
-
quality
the
in detail. The
using
100
doped, (lOO)-oriented,
pm and a resistivity of 14
of test wafers containing
Boron
on
an
of the
morphology
electronic
etching
24 Qcm
were
used for the
to 9.3 -10
17
s
_
cm
~
Very
Low
were
Oxygen
=
7.0-7.7-
1017cnr3
Low
0,
=
7.8-8.3-
1017cnf3
Normal
0,
=
8.3 -9.3-
1017citT3
High Oxygen (IG)
Chapter 1.4), i.e.,
no
concentration of the
close to 8.0
•
interstitial oxygen
A
num¬
were
was
remaining
study
were
LOX
a
NOX
HOX
CMOS process
(CBT,
see
carried out. The interstitial oxygen
material for this process
Some of the wafers with
processed
The four indi¬
VLOX
Oxygen (IG)
thermal simulation of
(NOX).
(HOX)
CMOS process. The
a
photolithography
standard starting
cm""0
10
to
thickness of
experiments.
prepared.
Oxygen
Oi
exposed
a
four different initial concentrations of interstitial
17
0^6.0-6.9- 10l7cnr3
were
of distortions in
simulator.
vidual concentration ranges of interstitial oxygen used for this
The wafers
fill] side-walls
CZ silicon wafers with
mm
Technology
high
technology
is
concentration of
without the well drive-in anneals of the
process steps
starting
with initial oxidation and
silicon nitride
deposition followed by the field oxidation, correspond to the ther¬
mal simulation of a simple n-channcl MOS (NMOS) process. Fig. 6.10 shows the
temperature profile of the CMOS/NMOS process simulations.
The
thermally pre-processed substrates were chemically polished at the back side
using a spin-etcher (Wetmaster, SEZ AG, Villach, Austria). The procedure is
described in detail in Chapter 2.2. The final thickness of the wafers after the pol¬
ishing was 380 ± 20 pm. The polishing ensures a void free etch mask by remov¬
ing scratches from the wafer back. For comparison, a number of unprocessed
wafers with high oxygen concentration (HOX) were added.
A standard PECVD silicon nitride
Inc., San lose, USA) with
of 1.1 pm
was
the wafer back
of the
a
passivation (Concept One, Novellns Systems
compressive stress of 200 ± 50 MPa and a thickness
subsequently deposited
was
deposited
obtained b\
silicon nitride
from 500 pm to 2500 pm
were
polished surface. An etch mask on
photolithography and reactive ion etching (RIE)
layer. Rectangular openings with sizes ranging
on
the
created. The front side of the wafers
was
pro-
75
6.3 Influence of Bulk
Crystal
1200
r
Defects
'
1000
900
CD
13
y
800
CO
I'" ''T
"Ö
ICXI
"05
I
,,
of Etched Cavities
,,,|,,„l.
T_7__
-
>
>
X
o
F
-
U o
=
CD
\
700
600
w
CD
CD
^
i,
CD
''
!
_
CD
Q.
Quality
co
Ü
-H—'
the
71 j
1100
c
on
_
"O
CD
-
Ll.
-
-
NMOS
CMOS
500
400 L
0
-
1
1
1
10
20
30
1.
!
40
50
Process time
Fig. 6.10: Temperature profile
Chapter 1.4) and the NMOS cycle.
tected
against
thickness
the
(6M)
ond etch
wafers
prepared
by
a
60
,
...
70
fhrs]
simulated
CMOS
(CBT,
see
low stress silicon nitride film of 1 pm
simultaneously immersed into a fresh,
etched to a depth of about 360 pm. A sec¬
were
KOH solution at 90°C and
experiment
anisotropic
performed using
was
a
257c TMAH solution at 80°C
as
etchant. The final
375 pm. Prior to the etch
surface of the
stirrer
etchant
the
1
(310 PC, STS, South Wales, UK).
A number of the
27%
anisotropic
for
,
samples
working
125
pmlr1
The
etching
at
depth of the cavities obtained with this etchant was
experiment in TMAH solution, the native oxide on the
was
300 rpm
removed
was
for KOH and 25.1
by
used to
pmtr1
a
agitate
in
a
2% HE solution. A
magnetic
the TMAH solution. Etch rates of
for TMAH,
defects in the {111} and the
investigated using
dip
respectively,
were
determined.
{100} surfaces of the etched cavities
optical microscope. Profile measurements of the cav¬
ity surfaces were carried out using an optical surface profiler (Microfocus, UBM
GmbH, Ettlingen, Germany). Another part of the processed wafers was used for
were
an
detailed bulk defect characterization b\
etchant
(1.5M Cr03 solution 1:1 with 409c HF [72]). In oder
between bulk
crystal
number of cavities
76
preferential etching using
also
preferential!}
etched.
Yang-
to find correlations
defects and defects in the surfaces of the etched
were
the
cavities,
a
6
6.3.1
Compatibility
Back Mask
Underetching
The surface
roughness
dimensional
optical profile
variation of the
Tssues Between Sensor- and IC Device
Roughness
and
of the etched cavities
measurements.
underetching
between
a
profile
of the
side-wall of the
{111} Side-Walls
characterized
Additionally,
underetching
by
one-
and two-
the amount and the local
of the silicon nitride mask
determined. The local variation of the
mask reveals the
was
of
Technology
on
the wafer back
was
of the silicon nitride back
{111] side-walls since the intersection line
cavity
and the wafer back represents
a
one-dimen¬
profile of the side-wall. Table 6.1 summarizes the mask underetching and
roughness of the side-walls of cavities etched with both anisotropic etchants.
sional
the
The values for the root-mean-square
Process
0, ll017cnU
(RMS) roughness of the surfaces
Underetching
q
mask
of back
[pm]
Roughness
walls
KOH
TMAH
of side-
[pmimsj
KOH
TMAH
(1)
6.0-6.9 (VLOX)
8.1 ±0.6
25 ±2
0.35
0.48
(1)
7.0-7.7(LOX)
14.5 ±3.5
49 ±3.1
0.59
0.7
0)
7.8-8.3
(NOX)
25.6
±
100
2.0
2.3
(0
8.3-9.3
(HOX)
30
5.3
114 ±8
1.6
2.2
(2)
8.3
9.3
(HOX)
23 ±2.2
53
0.25
0.55
(3)
8.3
9.3
(HOX)
7.8 ±0.1
0.14
0.27
-
-
±
6
±
±
15
5
18.7 ±0.2
j
Table 6.1:
on
and
of the oxygen
Underetching of the silicon nitride mask
roughness of the cavity side-walls as a function
centration and thermal
process,
(2):
process
(3): as-grown
(1)and(2).
(1)
processing; (1):
wafers with the
same
the wafer back
thermal simulation of
without well drive-in anneals
back mask
as
were
a
con¬
CMOS
(simulated NMOS),
wafers
processed with
obtained
by calculating the average over a larger number of individual onedimensional profile measurements. Because of the large craters in the side-walls,
the cut-off
wavelength
ficiently longer
1000
for the RMS
roughness
value calculation
than the scanned distance of the
profile
was
chosen suf¬
measurements
(850 pm-
pm).
77
6.3 Influence of Bulk
Crystal
Cavities in wafers with
atoms
and
cm
per
large
and
(NOX
on
the
Quality
and HOX
samples)
is
an
of Etched Cavities
initial oxygen concentration
an
exhibit
samples)
strongly varying underetching
cavities in wafers with
VLOX
Defects
higher than 7.7 -10
heavily distorted geometry
back mask. The quality of
a
of the
oxygen concentration below 7.7
strongly improved
and
•
10
cm
(LOX and
~
reduced
underetching of
the back mask is observed. On the other hand, HOX samples processed without
well drive-in anneals, i.e., simulating a NMOS process, yield etched cavities with
resonable quality. In this case, the amount of mask underetching is comparable to
the underetching in wafers given a full CMOS process thermal simulation but its
local variation is small. Generally, the lower the initial oxygen concentration in
the wafers, the better the surface quality of the etched cavities.
a
drastically
A remarkable difference between cavities etched with KOH and TMAH
observed. The
latter
case.
crystal
amount
and variation of
This is due to the
directions for this
etched cavities in
higher
underetching
etch rate
etching solution
thermally processed
centrations of interstitial oxygen
are
The detailed defect characterization
is
strongly increased in the
in ( 111) direction compared to other
[73]. In Fig. 6.11, photographs of
silicon wafers with different initial
\\ as
CMOS
During
done
by
G.
of about 10°
concentrations and
were
prepared
thermally
Processing
Kissinger
IHP, Frankfurt/Oder, Germany. Bevelled sections with
angle
con¬
shown.
Generation of Bulk Microdefects
6.3.2
was
length
a
and coworkers at
of 1.5
cm
and
an
from the wafers with different initial oxygen
simulated processes. The
samples
taken radi¬
were
ally, 2.5 cm away from the center of the wafer. A wafer without thermal pre-pro¬
cessing except a PECVD silicon nitride deposition on front- and back side was
added for
comparison. The bevelled sections were preferentially etched using the
Yang-ctchant for 2.5 min. During the preferential etching, 4 pm of silicon was
removed. The decorated
trast
microscope.
faults
(SF),
samples
inspected
Four kinds of defects
extended dislocations
small dislocations
were
78
Fig.
as a
phase
con¬
stacking
comparison.
In
Fig. 6.12,
the
density
function of the initial concentration
6.13 shows
etched bevelled sections. No defects
thermal treatment added for
interference
identified and counted:
(P/PD), and punching systems (PS).
of interstitial oxygen in the wafers.
tates and small
an
(D). oxide precipitates, partly associated with
of the different types of defects is shown
tially
were
with
were
photographs
of the
preferen¬
found in the HOX wafer without
In VLOX
precipitate-dislocation complexes
samples, only
oxide
could be observed.
precipi¬
Punching
6
Compatibility
Issues Between Sensor- and IC Device
NOX
Technology
VLOX
KOH 27%, 90°C
TMAH 25%, 80°C
Wet etched cavities in wafers with normal (NOX) and very low
Fig. 6.11 :
(VLOX) oxygen concentration, the wafers were exposed to a thermal sim¬
ulation of a CMOS process (see Fig. 6.10) before etching.
systems
generated
were
in LOX wafers in addition to the defects observed at the
lower oxygen concentration. In the bulk of the NOX and HOX wafers with oxygen concentrations
ing
faults
higher
generated
were
than 7.7
was
10
cm
oxide
at the
close to front- and back side
•
\ extended dislocations and stack¬
precipitates.
observed in these
A defect free
samples.
The counted
of the
are
precipitates in these samples is low because the etch-pits
masked by larger secondary defects generated at them.
A remarkable difference between the
HOX
samples
was
in wafers with
generation of stacking
observed: the average diameter
higher
c/dveui2e
concentration of interstitial oxygen
(DFZ)
zone
density
of these defects
faults in NOX and
of the
was
stacking
faults
smaller than in
wafers with the lower oxygen concentration (26 and 75 pm, respectively, see
Fig. 6.13). However, the concentration of the stacking faults is reduced from
3.2
the
•
104cnf 2
area
(tt/4
both cases,
in HOX
•
samples
dAveta„e~)
thus,
a
to
and the
comparable
4.0
•
lO'cnO2
density
of the
in NOX wafers. The
stacking
faults is
product of
nearly equal
in
concentration of silicon interstitials is involved.
79
Crystal
6.3 Influence of Bulk
Defects
on
the
of Etched Cavities
Quality
.6
10
CXI
10
£
10
en
c
CD
:
5
4
10
Û
10
o
CD
CD
10
10
0
Interstitial
9
8
7
Oxygen [10
17
-O
cm
]
precipitate/precipi¬
complexes (P/PD), punching systems (PS), stacking
dislocation lines (D), as a function of the initial
extended
and
faults (SF),
concentration of interstitial oxygen in a thermally simulated CMOS pro¬
cess (see Fig. 6.10).
Fig.
6.12:
Generation of bulk microdefects, such
as
tate-dislocation
(a)
HOX
lit
|(b) VLOX
|
(r\ I HY
iiÄlÄIWi^S^B
ifllflPffl
TeTHOx"'!^
six ;'!&*?;
ï-f^^^^^:^;,^:^^^
Éï|kJ|i
"
*
*
;
w.
'
*:
S,':":'fcf'
Aïâ«'. 5:f^afJE
11*".Vf«î.v'a*'«**
Fig.
6.13:
Photographs
of
etched
preferentially
cess
80
(see Fig. 6.10).
CMOS process,
(f)
to
50 pm
I
-J
bevelled sections:
(b) to (e) wafers exposed
thermally simulated NMOS
reference wafer without thermal treatment;
thermally simulated
7,«v.'U:':>^:,^j,:*:i:i:.,Ä^
(a)
to
a
pro¬
6
Compatibility
The lower concentration of
ably,
a
Issues Between Sensoi- and TC Device
stacking
faults observed in NOX
result of the lower concentration of oxide
stacking
samples is,
precipitates
presum¬
able to nucleate
faults.
HOX wafers
process,
Technology
see
thermally treated
Fig. 6.10)
late-dislocation
showed
complexes (9.3
without well drive-in anneals
a
high density
(simulated NMOS
of precipitates and small
precipi-
large secondary defects, such as
stacking faults and extended dislocations were not observed. Obviously, the
oxide precipitates do not reach the size required to nucleate stacking faults
(26 nm, 174]) during NMOS process simulation (see also Fig. 6.9).
6.3.3
Fig.
O,
10 cm"-) but
Correlation Between Bulk
Optical micrographs
ent
•
of
Crystal
{111} side-w alls of etched cavities
and different thermal treatment
6.14:
side-wall in
Defects and Defects in Side-Walls
Photographs
of
are
shown in
{111} side-walls
m
wafers with differ¬
Fig. 6.14. The VLOX sample
of KOH-etched cavities:
(a)
a
wafer without thermal
processing except front- and back
side masking, (b) to (e) side-walls in samples given a thermal simulation
of a CMOS process and (f) thermally simulated NMOS process (see
Fig. 6.10); although the structures in the cavity side-walls tend to look like
upheavals, they are, in fact, depressions.
a
81
6.3 Influence of Bulk
shows
and shallow
large
increasing
lion
Crystal
to
7.7
on
depressions in
cm
(LOX),
I 7
10
•
Defects
_A
-
the
of Etched Cavities
Quality
the side-walls. With oxygen concentrathe defect
density
on
the side-walls rises
and the
depressions get a terraced structure. In samples with oxygen concentra¬
1017cnO' (NOX and HOX). up to 10 pm deep, terraced
tions larger than 7.7
craters appear in the side-walls. The densit} of craters is higher in HOX samples
•
than in NOX wafers whereas the size of the craters is reduced. This result
lates with the observations from the defect characterization
the
ing. Here,
by preferential
faults increases from the second
stacking
highest
initial interstitial oxygen concentration whereas the size of the
highest
faults is reduced.
Obviously,
the
uniform
etch¬
to
the
stacking
Furthermore, the back mask underetching is increased in HOX
but the local variation of the
samples
more
of
density
corre¬
underetching
(sec Table 6.1).
is smaller
higher density of large bulk defects in the HOX wafers leads to a
underetching in contrast to NOX samples. In samples etched with
TMAH, deeper and less terraced
found. The HOX
samples pro¬
cessed without well drive-in anneals (simulated NMOS cycle) exhibit a high den¬
sity of shallow etch pits but no deep craters. The back mask underetching in these
samples is large but uniform so that the etched cavities maintain a well-defined
truncated
craters were
pyramidal shape.
In order to find the
side-walls,
microscopic origin
of the
depressions
craters in the
or
(111)
number of
samples with cavities were preferentially etched using
the Yang-etchant. Various bulk crystal defects were found in the center of the cra¬
a
ter-like structures.
bulk
7.7
by
The
micrographs of
shallow depressions
initial interstitial oxygen
small dislocations
generated
at
(NOX, HOX) showed
bulk
precipitates
stacking
of
were
that the
neighbored
only
defect
in
more
up
to
found to be caused
punching systems.
than 7.7
•
1017cm
3
The
oxy¬
ciystal
defects and
etching
structures
not
were
with
of
a
occurs.
observed. Extended dislocation lines
high density
stacking
were
not
found.
depression
'masking' by craters or depres¬
Depressions associated with
a
of
stacking
faults mask the
Depressions surrounding precipitates
defect associated
82
samples
etching patterns
cation lines.
were
with
faults of different size and orientation in
found, it is assumed that
extended dislocation lines
observed
samples
{111} side-walls, also crystal defects without associated
in the side-wall
sions
in
and small
their centers. Besides the clear correlation between
defects in the
craters and their associated
(VLOX, LOX)
in the side-walls of cavities in wafers with
craters
gen
6.15 shows
defects.
crystal
1017cnr-
•
Fig.
faults. It is assumed,
etching pattern
with
no
were
secondary
of the dislo¬
bulk
crystal
6
Compatibility
Issues Between Sensor- and IC Device
Technology
Depressions in side-walls of KOH-etched cavities, (a) focused
ion beam (FIB) micrograph of a small crater with associated bulk stacking
fault, (b) SEM micrograph of associated triangular dislocations in the cen¬
ter of the crater shown in Fig. 6.16 (a) (both samples were preferentially
etched).
Fig. 6.15:
6.3.4
Morphology
Generally,
two
of Craters in {111} Side-Walls of Etched Cavities
types of
craters
caused
observed. Most of the craters have
small number of craters,
II). Fig. 6.16 shows
in
a
VLOX
a
by
the different bulk
crystal
defects
were
V-shaped (type I) height profile whereas a
very large diameter, has a well profile (type
usually with
profile plots of both
crater
types in the side-walls of cavities
sample.
;20 pm :
(a)
.01:«|§||rj:;^g :;
-1.76p.
(b)
Surface profiles of (a), V-shaped (type I)
Fig. 6.16:
(type II) crater defect in a (111)-oriented side-wall of
(VLOX sample given a CMOS thermal simulation).
and
a
(b) well-shaped
cavity
KOH-etched
83
6.3 Influence of Bulk
Defects
Crystal
on
The bottom of the type II craters appears
experiments
type
reveal that
no
slightly
concave.
defects
crystal
associated
of Etched Cavities
Quality
the
Preferential
are
II craters. It is assumed that the defective volume of the silicon
removed
by
etchant, i.e.. the crystal defect
the
was
etching
present in the center of
crystal
etched away. Based
on
was
this
well-shaped crater could be a measure for fhe
extension of a bulk crystal defect perpendicular to the (lll)-oriented side-wall.
In the side-walls of VLOX samples, very large, well-shaped depressions together
with V-shaped craters of small diameter were found. This indicates crystal
defects of small size. On the other hand, well-shaped and V-shaped craters in the
side-walls of NOX and HOX material are of similar size because of the large bulk
stacking faults present in these samples.
consideration, the depth of such
a
In contrast to the observations of other authors
side-walls of the etched cavities have
Similar
etching patterns
were
a
hexagonal shape (see Fig. 6.14).
distinct
observed in
[75.76], the depressions in the
{111) side-walls of anisotropically
etched cavities in wafers from other vendors. It is assumed that these
hexagonal
anisotropic etching patterns. The individual etching pattern is
formed by released crystal planes intersecting a (lll)-orientcd side-wall. The
intersection line of, e.g., 6(111} planes or 6 {110] planes with a given (11 ^-ori¬
structures
ented
are
plane is
a
regular hexagon with 120° angles. Fis. 6.17 shows
the
crystal planes intersecting
a
the
given (11 l)-oriented plane
under
with
angle larger
an
(111) side-wall,
given (111) plane.
In order to prove the
etching patterns,
an
a
schematic of
{111} planes intersect
steep angle of 70.5°, three others intersect
a
than 90°. Furthermore, 6
three of them under
Three
a
shallow
assumption that the
etching experiment
{110} planes
angle
craters
intersect
a
released
of 35.3°.
in the side-walls
are
anisotropic
was per¬
artificially
by 10 pm openings was used to expose a
£2cm, (lll)-oriented wafer covered with photo resist.
created defects
on
formed. A dark field mask with 10 pm
50
mm
diameter, 50
-
200
Subsequently,
the silicon
of 6 pm
RIE. After
a
using
was
etched
stripping
through
the
27% KOH solution at 90°C for 4 min.
tern. It has
walls. As shown in
Fig. 6.17,
intersection
angle
tern appear
slightly
84
Fig.
photo
resist
resist, the wafer
openings
was
to a
depth
immersed into
6.18 shows the
resulting etching pat¬
etching patterns caused by the bulk crys¬
hexagonal shape similar to
Three edges of the etching pattern
a
tal defects.
photo
the
appear
as
steep and smooth side-
these side-walls
of 70.5°. At the upper
correspond to {111} planes with an
edge, the side-walls of the etching pat¬
rounded. The three other
edges
of the structure
are
strongly
6
Compatibility
Issues Between Sensor- and IC Device
Technology
70.5
35.3C
Fig.
6.17:
Schematic of
crystal planes intersecting a given (111) plane A.
Three {111} planes intersect plane A at an angle of 70.5°, 3 others at
109.5°. Furthermore, three {110} planes intersect A under 35.3°. Dotted
line: intersection line of the plane of the etching simulation shown in
Fig. 6.19.
Ill
Initial artificial
defect
SjpTT
Fig.
6.18:
defect
on
Etching pattern resulting from the etching of an artificial
(111)-oriented wafer (initial size 10-10-6 um3) (SEM photo¬
graph).
85
6.3 Influence of Bulk
toothed. This is
Crystal
presumably
responding {111} planes
Additionally,
is
Defects
on
the
Quality
due to the fact that the
angle
of incidence of the
cor¬
than 90°.
larger
the
ented material
etching pattern resulting from an artificial defect in (111 ^ori¬
was simulated using an electronic etching simulator (QSIMODE,
GEMAC, Chemnitz, Germany). QSIMODE is able
silicon structures
a
of Etched Cavities
during anisotropic etching.
30% KOH solution
were
cross-sectional view of the
used
as
etching
An
calculate cross-sections of
to
etching temperature
of 80°C and
parameters for the simulation. In Fig. 64 9,
simulation of
an
a
artificial defect is shown. The
U
Fig.
with
6.19:
an
Time evolution of
artificial
cross-section is
cross-section of
(111)-oriented wafer
defect during a simulation of wet anisotropic etching.The
viewed from (110)-orientation (see Fig. 6.17).
intersection line of the
a
a
(HO)-oricnted cross-section plane with
tion is
displayed as a dotted line in Fig.
defect, a (lll)-oriented plane is released
the
(111) orienta¬
6.17. At the left side of the artificial
the
beginning of the etching time.
With increasing time, a (110)-oriented cixstal plane begins to dominate the etch¬
ing pattern. This is due to the fact that the upper edge of the artificial defect is a
convex corner. It is well known that during wet anisotropic
etching at convex cor¬
ners crystal faces with high etch rates
appear [21].
Besides their
ples
with
a
found to be
hexagonal shape,
low
densit}
very large.
individual defects
86
are
of
at
the lateral extension of craters
special
cnstal defects
(PD
Because of the low defect
not
strongly
affected
by
in VLOX, SE in
density,
the
especially
the
in
sam¬
NOX)
was
etching patterns
etching patterns
of
of other
6
defects
a
Compatibility
and, thus, their size
Issues Between Sensor- and IC Device
be monitored. The
can
defect located in the wafer bulk may extend
(see Fig.
(b), (d)) although
6.14
wafer bulk and
exposed
the defects
over
are
'Technology
anisotropic etching pattern
the whole side-wall of
a
of
cavity
concentrated in the center of the
the etchant
only part of the entire etching time.
Following the result of the etching simulation that (HO)-oriented planes domi¬
nate the edges of the depressions for longer etching times, it is assumed that the
elevated silicon etch rate in (110)-direction (compared to the etch rate of the
were
(lOO)-orientation [21,73])
In order to
investigate
roughness
of
tom
of the
causes
the fast lateral
growth
of the craters.
of Anisotropically Etched {100} Silicon Surfaces
Analysis
6.3.5
to
the influence of oxygen induced bulk
{100} surfaces, cavities
cavity
were
crystal
etched in wafers in
a
defects
on
the
way that the bot¬
located in the defect-rich interior of the wafer. Wafers with
was
the four initial interstitial oxgen concentrations treated with both thermal pro¬
cessings
and
subsequent
back
masking
KOH solution at 90°C to obtain 195
wafers
was
380
±
20 pm
so
±
that the
200 pm below the wafer front surface.
of the etched cavities appears
Groups
depth
of shallow circular
of about 0.3 pm
high density
of these
slightly
were
polishing
depressions
process
spectral density
similar to earlier observations 177].
a
diameter of 50
at the
observed in
polished
samples
back side (sec
of this kind have been used
serve as
of the
convex
was
is assumed that the patterns of bulk
the
deep cavities. The thickness of the
investigated {100} surfaces were about
The profile of the (JOO)-oriented bottom
found at the bottom of the cavities
depressions
etched in 27%
were
5 pm
depressions having
patterns of bulk stacking faults
defined circular
mentioned above
crystal
defects
at
initial defects for these
as
-
100 pm and
(sec Fig. 6.11).
with
Fig.
a
A
sickle-shaped
2.7
(b)). Well-
micromirrors [78]. It
the wafer back
generated by
depressions. Analysis
of the
{100} surface roughness after filtering of convexity and
circular
depressions shows a broad
spatial wavelength for all samples.
spectrum with
a
maximum at around 80 pm
The
integrated value of the roughness was
around 0.07 pmrms for all samples. Compared to the roughness of the wafer back
of 0.06 pmims with a spatial wavelength of approximately 300 pm, the etching
process creates additional roughness at a reduced periodicity down to 6 pm spa¬
tial wavelength. A clear dependence of the surface roughness on the interstitial
oxygen concentration and thermal
processing of the individual samples was not
found. Moreover, preferential etching (Yang-etch, 2 min) reveals no obvious cor¬
relation between bulk crystal defects and the profile of the (lOO)-oriented bottom
of the cavities.
87
6.3 Influence of Bulk
In
a
further
well
Crystal
experiment,
Defects
wafers
unprocessed
on
the
Quality
(VLOX. NOX) given
reference wafer
of Etched Cavities
a
CMOS process simulation
anisotropically etched starting
from the prime quality polished front side. For that, layers grown or deposited
during the CMOS simulation were removed using RIE. RIE etching was not fully
completed in order to avoid roughening of the surface. The residual layer (buffer
oxide) was removed by a 2-5% HF solution. The front and back of the wafers
were protected against the etchant by a low stress silicon nitride film with 1 pm
thickness. Rectangular openings of sizes ranging from 500 pm to 2500 pm were
created in the silicon nitride layer on the front side using RIE. Because of possi¬
ble roughening of the surface by RIE, the silicon nitride layer was not completely
etched through leaving a layer of around 50 nm. This residual layer was removed
using a 10% HF solution. Subsequently, the wafers were anisotropically etched to
a depth of 270 pm. Therefore, the investigated surfaces were in the center of the
defect-rich zone of the wafer. Again, a difference of the roughness of the {100}
planes between wafers with high defect density (NOX) and low defect density
(VLOX) and the reference was not found. The {100} roughness was about
0.17 pmrms for all samples in this experiment. Presumably, because of the small
as
as
an
were
difference of the etch rate of silicon in ( lOOVdirection and the etch rate of defec¬
tive
crystal
zones,
resolution of the
an
effect due to the defect
•
(Quality
of Wet Etched
The craters in the side-walls of wet
cessed silicon wafers
various bulk
stacking
not
was
found within the
experiment.
Conclusive Remarks
6.3.6
density
were
crystal defects,
anisotropically
identified
such
Cavities)
as
etched cavities in pro¬
anisotropic etching patterns of
dislocations, punching systems, and
as
faults. The effects of the individual types of delects
Bulk microdefect
Precipitate (P)
Precipitate
Effect
on
were:
side-walls
-
associated with dislocation
Shallow
depression (1-2 pm)
Shallow
depression (2-3 pm)
(PD)
Punching system (PS)
Stacking
fault
(SE)
Extended dislocation lines (D)
88
Crater (up to 10
Not observable
pm)
6
•
Compatibility
Generally,
the
Issues Between Sensor- and IC Device
dependence
of the
etching
results
tion of interstitial oxygen is similar for both
this
study.
The
underetching of
pared to KOH.
•
of the
depth
craters
on
etched
not
silicon surfaces
of the etched
high roughness
the initial concentra¬
anisotropic
in the
etchants used in
side-walls and the
cavity
the back mask is increased for the TMAH etchant
An influence of bulk microdefects
{100}
on
Technology
was
the
com¬
of wet
quality
anisotropically
might be due to the
by the etching process
found. This
{100} planes caused
itself.
•
Using etching experiments
it
was
nates
shown that the
from
{111} and
on
artificial defects and computer simulations,
hexagonal morphology of the crater defects origi¬
{110} planes intersecting the side-walls. For short
edges of depressions in the side-walls were formed by
(11 l)-oriented planes whereas for longer times {110} planes dominate.
etching times,
•
The
the
experimental
(0^6.0-6.9
•
10
I 1
results
indicate
that
VLOX
material
^
cm~°)
co-integrated
is well suited for the fabrication of silicon
with CMOS circuits
by wet anisotropic etching.
Only small precipitate-dislocation complexes with a very low density of
103ciTr2 were generated during the thermal simulation of the CMOS
8
sensors
•
process CBT. The
depth
of the
depressions
in the side-walls of the cavi¬
ties did not exceed 2 pm
etched cavities is not
since wafers with low interstitial oxygen concentration have
required
•
and, therefore, the geometrical shape of the
distorted. However, an extrinsic gettering scheme is
insufficient
gettering capabilit}
precipitates
and
secondary
Etched cavities in HOX
of
good
surface
quality
due to the low concentration of oxygen
bulk
(O,
=
when
crystal
8.3
-
defects.
9.3
•
1017cm~ 1)
thermally processed
wafer material
without the well drive-
in anneals of the CMOS process simulation. The absence of
stacking
faults in these wafers led to
were
strongly improved
surface
large
bulk
quality
of
the side-walls of the etched cavities. In contrast to LOX and VLOX
wafers, the gettering capability of this wafer material is maintained due
to
high density of small precipitate-dislocation complexes. For KOH as
anisotropic etchant, the underetching of the back mask in HOX samples is
large but uniform and predictable. It can easily be taken into account by
a
reducing
the size of the
openings
of the
photomask
used for back side
89
6.4 External
Gettering
exposure. As
PMOS)
or
can
concentration
As
(VLOX)
the low defect
6.4
be devised
on
density
gettering
to
are
CMOS
with
sensors
using
internal
required
simple
Oxygen
circuits
(either NMOS
standard wafer material with
an
oxygen
gettering.
investigations above,
concentration
microsensors based
external
result, silicon
leading
main result of the
a
gen
a
for Wafers with Reduced Interstitial
wafers with reduced interstitial oxy¬
for the fabrication of
technolog}
and ECE. Such
in the bulk, low internal
a
integrated
silicon
material has, due to
gettering capability.
Additional
for this material is discussed in the next section.
Gettering
External
Interstitial
for Wafers with Reduced
Oxygen
As shown in
Fig. 6.12, silicon wafer material with O, 6.0 6.9 10 cm"J contains only precipitate-dislocation complexes with a low density of 8.0 10JcnkO
It is expected that in wafers with this interstitial oxygen concentration internal
gettering of impurities is strongly reduced.
=
-
•
•
Especially
for 'smart'
co-integrated with VLSI circuits on one single
chip, gettering of metallic impurities in the substrate material is mandatory.
Insufficient gettering of impurities leads to \ ield losses in VLSI processing. Thus,
sensors
silicon wafer material with reduced
is
density
of
crystal
defects in the bulk and
gettering capability
required.
gettering capability required
by external gettering methods using, eg, polysilicon layers on
wafer or damage of the crystal lattice at the wafer back surface.
The
can
be
high
provided
the back of the
The Fe
gettering capability of a pol} si lieon la} er on the back of either Float Zone
(FZ) or CZ-grown wafers with an initial concentration of interstitial oxygen of
6.5
6.0
10 enr1 was investigated earlier (79,80]. It was shown that gettering
by a polysilicon layer is effective as long as the polycrystallinity of the layer is
•
-
maintained.
Efficient reduction of the
ing
faults
by
density
of
impurity-nucleated
oxidation induced stack¬
damage present at the wafer back was reported [8l|. In high
temperature processing, a relaxation of the introduced damage by the generation
of crystal defects, such as stacking faults and dislocation lines occurs. Very effi¬
cient Fc
90
a saw
gettering by
these defects
was
observed [82].
Especially stacking
faults
6
Issues Between Sensor- and IC Device
Compatibility
proven to be effective nucleation centers for the
were
metal ions
In this
precipitation
layer
The
study
the back side
on
is limited to the
polysilicon layer
(PBS)
or a
investigation
and in
CMOS processes is adresscd.
nated wafers
14
-
were not
100
doped,
24 Eicm and
of the
a
the wafers. For the
Gettering experiments
sides, respectively. Espe¬
with
thickness of 525 pm
investigation
of the
a
were
the influence of thermal
was
6.0
resistivity
•
6.9
-
annealing
processing
on
the
the back of the wafers. The temperature
by
layer
intentionally
used for the
•
contami¬
behavior of
of 27
density
profiles
(Oj]) for most of
the polysilicon thin
29 Ocm and
-
cm"1
10
resistivity of
experiments. The ink
a
10 cm~°
(Oj2)
simulations of the front-ends of two CMOS processes
silicon
various stases of
at
(lOO)-oriented CZ silicon wafers with
mm.
stitial oxygen concentration of 7.4-7.7
A number of
polysil¬
carried out.
films, Oj | wafers and wafers with
Fig.
a
damage (BSD) are investigated.
density of gettering-active defects
wafers back
damaged
tial concentration of interstitial oxygen
shown in
heavy
back side
cially, the evolution of the densitv of setterinç-active defects
Boron
of
[83].
section, silicon wafers prepared by the wafer manufacturer with
icon
in the
Technology
of
initial inter-
an
used. Thermal
were
investigate
gettering-active defects at
were
used to
of the thermal simulations
are
6.20.
OiL
and
Ol2
wafers
the back. The
on
were
coated with
deposition
of the
a
0.8 pm thick
undoped poly¬
polysilicon layer was performed
Burghausen, Germany) prior to
the wafer manufacturer (Wacker Siltronic AG,
front side
polishing.
rccrystallization
cross-sectional
The film
deposition
was
carried out at 650°C for 1 hr. The
of the
polysilicon layer during CMOS processing
transmission electron microscopy (XTEM).
was
studied
by
hard
0,j wafers was treated by the wafer manufacturer with a soft or a
mechanical damage. Wacker denotes the hard mechanical damage by Stan¬
dard
Damage
A second lot of
Damage
Hard
of the
(SDH)
and the soft
or
silicon carbide
wafers is not visible whereas
on
wet
pyrogenic steam
gettering capability of back
oxidation (about 850 nm)
preferential etching using
the
(SDH) particles.
Damage
by
at
1100°C for 2 hrs
side
damages.
a
The
the back of SDFÏ wafers striae
A wet oxidation in
the
Standard
lattice at the wafer back is introduced
crystal
aluminum oxide (SDS)
ate
damage by
was
Soft
(SDS).
treatment
damage
can
at
using
SDS
be observed.
employed
The oxide grown
to evalu¬
during
the
subsequently stripped in buffered HF. After
Yang- or the Wright etchant, the density of grown
was
91
6.4 External
Gettering
for Wafers with Reduced Interstitial
Oxygen
1200
1100
1000
o
900
CD
(a)
CMOS1
800
03
CD
Q.
700
E
600
CD
Buffer Oxid/ Nitride
500
400
0
10
30
20
50
40
60
P
(b) CMOS2
CD
r3
+—-
CO
CD
Q.
E
CD
10
5
Process time
15
20
25
[hrs]
Temperature profiles of the thermal CMOS process simula¬
tions used in this study: (a) simulation of the front-end of CBT and (b)
simulation of the front-end of CYE (see Chapter 1.4).
Fig.
6.20:
crystal
This
defects
procedure
was
is
determined
commonly
by counting
used
the defects within
a
by wafer suppliers for damage
specified
evaluation
area.
[84]
time-temperature graph of
the oxidation carried out during the damage-test is shown in Fig. 6.21. Insertion
and withdrawal of the wafers in- and from the furnace were performed under
and is referred to
92
as
damage-test
in the
following.
A
6
Compatibility
Issues Between Sensor- and IC Device
1200
I
I
Technology
!
1100
1000
o
o
900
CD
Z5
H
/
>
Wet Oxidation
/
F
800
CD
Q.
—
700
F
CD
-
t-
600
..
500
-
-
I
400
0
I
!
3
12
Process time
Fig.
6.21
:
Time-temperature graph of
atmosphere.
pure oxygen
(OiSF)
at the
microdefects
the
[hrs]
damage-test
used in this
Dislocation lines and oxidation induced
back surface of the wafer grow
(e.g., microcracks)
introduced
during
the
by
damage.
the
micro defects able to nucleate dislocations lines and
damage
stacking
study.
stacking
faults
test nucleated at
It is assumed that
faults have getter¬
ing activity. Following this argument, the density of gettering-active defects at the
back of damaged wafers is at least equal or higher than the density of defects
grown during the damage test.
density of defects obtained by preferential etching using the Yang
The
compared with a TEM investigation. The density of dislocations at the back
damaged, oxidized (Fig. 6.21) and subsequently annealed sample was deter¬
was
of
a
mined
both
ing
etchant
the
cases was
is
6.4.1
using
an
Yang
in the
appropriate
Polysilicon
etchant and TEM. The
same
order of
method to
density
of dislocations obtained in
magnitude indicating
measure
defect densities in
preferential etch¬
these experiments.
that
Back Sides
Deposition on BMD Generation
investigation, enhanced oxygen precipitation
Influence of PBS
In
an
initial
crystal defects during
shown in
a
and
generation
of bulk
CMOS process (CYE, front-end
Fig. 6.20, (CMOS2))
was
observed in
time-temperature graph
0,i material with PBS compared
93
6.4 External
to
Gettering
for Wafers with Reduced Interstitial
material without PBS. The thermal
Oji
budget
of the
Oxygen
polysilicon deposition
hr) appears to be an effective nucleation step for the precipitation of
oxygen (see Fig. 6.8). Enhanced precipitation of oxygen by a polysilicon deposi¬
tion was also observed by other authors [85]. The growth of grown-in precipitate
(650°C,
nuclei
1
during
enhanced
moderate temperature processing is well known
precipitation [67].
nucleation treatment
below)
ramp
at
was
or
(BMD) generation in
studied: after
Rapid
Thermal
a
In Table
(denoted
as
"etched
back")
a
an
cause
for
alternative
CMOS process
Annealing (RTA,
0,i wafers were subjected to
min""1) prior to the CMOS process. 0,j
RTA and nucleation treatment
tion
the influence of
1050°C for 3 min.
(500-700°C, IK
parison.
comparison,
bulk microdefect
on
(thermal simulation of CBT)
sec
For
as
were
a
slow thermal
wafers without
added for
com¬
6.2, the influence of the nucleation by either polysilicon deposi¬
slow thermal ramp
on
the BMD
Nucleation treatment
generation
P/PD
|cm"2]
is shown.
SF
[cirT2]
Stacking faults,
SF
length
Lpm]
None
8-103
PBS
9.2ri04
1.2-JO4
16
Etched back, slow thermal ramp
1.7-105
2.8-104
18
500
-
-
-
700°C, 1 K min-1
Table 6.2:
Influence of nucleation
slow thermal
simulation of
by either poly silicon deposition or
ramp on BMD generation in O^ material during a thermal
a CMOS process (front-end is shown in Fig. 6.20 (CMOS1).
detrimental for the
quality
of wet
anisotropically etched cavities, were generated
by both treatments. Thus, 0,|/PBS wafers without any further treatment cannot
be used as starting material for the fabrication of integrated sensors by ECE.
The reduction of the size of
precipitate
nuclei grown
during crystal pulling by
was
recent!} [86]. Therefore, RTA treatments were performed on
the PBS wafers in order to shrink the size of the oxide precipitate nuclei grown
during polysilicon deposition (see Fig. 6.6). RTA was performed on Ol{ wafers
with PBS for cither 3 min at 1050X or 3 min at 1150°C. Ramp rates of 50 Ks^1
for ramp up and 33 Ks~l for ramp down, respectively, were chosen. RTA was
pcrRTA
94
studied
6
Compatibility
formed under
roughening
Issues Between Sensor- and IC Device
nitrogen atmosphere containing
of the surface
by
efficient for the
during
ing
faults
generated
5% oxygen in order to avoid
thermal
etching. Both treatments turned out to be
precipitation and generation of secondary defects
suprcssion of
subsequent thermal simulation
a
Technology
of
a
CMOS process.
Especially,
no
stack¬
in
O,, wafers with PBS pre-processed using RTA dur¬
ing subsequent thermal processing. Thus, the detrimental effect of the PBS
deposition on the BMD generation during CMOS processing can be cancelled
and the wafers can be used as starting material for sensor fabrication. Table 6.3
were
shows the effect of RTA
on
the BMD generation in PBS wafers. On
Thermal treatment
PBS
P/PD[cnr-|
SF[cm~-]
SF
1.5-10"
8.0-101
19
PBS
+
RTA 3 min, 1050°C
1.2-10"
PBS
+
RTA 3 min, 1150°C
8.0-10'
Influence of RTA treatment
Table 6.3:
with
see
polysilicon
Fig. 6.21).
samples
3 min
back side
during
a
on
BMD
generation
simulated CMOS
annealed at l 150°C,
slip lines were found. Therefore,
exclusively employed for all further experiments.
was
Recrystallization
In order to
a
number of
length [pm]
in
On wafers
process (CMOS1,
RTA at 1050°C for
of PBS
the
gettering capability of PBS, alterations of the crystal struc¬
ture due to CMOS processing must be monitored. In a number of previous stud¬
ies, an epitaxial realignment (ETR) of poh silicon thin films with the underlying
assess
silicon substrate
at
was
found after
1100°C for 120 min led to
con
layer
layer
at
was
high-temperature annealing: a furnace annealing
complete realignment. Grain growth in the polysili¬
observed at lower temperatures [87].
U50°C caused ETR within 25 min
observed in
doped polysilicon layers
ter transistors
|89]. The native oxide
Deposition
epitaxial
the wafers
was
polysilicon
stripped prior
deposition. Only a very thin interface oxide layer was grown
between stripping and pol}silicon deposition. The break-up of
con
an
[88]. Very fast recrystallization
used for the fabrication of
on
of
to
was
emit¬
polysili¬
within the time
this interfacial
95
6.4 External
Gettering
oxide appears to
realignment.
film
occurs
were
play
for Wafers with Reduced Interstitial
a
major
role in ETR since it is
Once it is dissolved, the
very fast. RTA treatments at 1050
observed to be sufficient for
polysilicon layer
of the
growth
grown, 100
In order to
realignment
nm
-
of
1100°C for
without ETR
was
to thermal
(CMOS1
CMOS2,
and
see
ture was
were
10's of seconds
hand, only grain
observed with
a
thermally
(0,j and Ol2) were treated
precipitate nuclei and after¬
simulations of the front-end of two CMOS processes
Fig. 6.20).
polysilicon films were carried out. In
on the polysilicon layer, a wafer with
with RTA
silicon
wafers with PBS
investigate possible ETR,
subjected
some
for the
[90].
with RTA for 3 min at 1050°C in order to shrink the
wards
acting as a barrier
the polycrystalline
ETR. On the other
complete
thick interfacial oxide
Oxygen
characterized
by
After
that, TEM characterizations of the
order to evaluate the influence of the RTA
PBS
delivered and
as
TEM. In both
samples,
a
a
PBS wafer treated
columnar
grain
struc¬
found. No difference in the microstructurc of the PBS due to the RTA
observed.
was
ETR of
polysilicon layers was found after CMOS1 process simulation.
It was speculated that the long well drivc-in anneals (more than 20 firs at 1150°C)
caused the ETR. Therefore, the behavior of the polysilicon layer was investigated
Complete
in
process simulation with shorter anneals at 1150°C
a
sections of PBS after certain thermal process steps
samples
were
oxidation and
are
(CMOS2).
shown in
TEM
Fig.
cross-
6.22. The
exposed to different sections of CMOS2 (sec Fig. 6.20). Buffer
nitride deposition at the beginning of the process simulation as the
well
as
ture
of the PBS. However, the well drive-in anneal at 1150°C for 6 hrs led to
almost
ing
well drive-in anneal at 1000°C did not
complete epitaxial realignment
substrate. In
200-800
nm
some
and
an
samples prepared
silicon
investigations
layer
were
Halle, German}).
for
alter the microstruc-
polysilicon layer with the underly¬
TEM, single grains with a size of
orientation
differing from the orientation of the realigned
density in these samples was estimated to be around
polysilicon remained. Their
107cm~O In Fig. 6.23, a single grain
polysilicon layer is shown.
Detailed
of the
significantly
as
of the defects
large
as
remaining
the thickness of the
in the
epilaxially realigned poly¬
carried out (Dr. D. Katzer, Institut für
The sequence of diffraction
recrystallized
fringes
in
Werkstoffmechanik,
bright- and dark field
TEM was investigated for a large number of defects in the rccrystallizcd layer. A
photograph of a typical crystal defect present in the annealed polysilicon layer is
shown in Fig. 6.24. For ever} defect investigated, a s}mmetrical sequence (from
96
6
Fig.
6.22:
were
Compatibility
XTEM
processed
Issues Between Sensor- and IC Device
micrographs
of
polysilicon
back sides. The
with RTA for 3 min at 1050X and
tions of CMOS2 thermal simulation
underwent
additionally
samples
with, subsequently,
(see Fig. 6.20).
sec¬
The
characterized after base oxidation and silicon nitride
(b)
Technology
well drive-in anneal 1 and
sample (a) was
deposition, sample
sample (c) obtained
both well drive-in anneals of CMOS2.
dark
was
fringe
to dark
fringe
or
obtained. This type of
wins
in
vice versa) of
fringe
sequence
fringes in both, bright- and dark field,
is unique for microtwins [91]. Microt¬
annealed
polysilicon layeis were found by
[80.87,921. Fringe sequences symmetrical in biight-field
in dark field TEM observation
Microtwins, however,
as
typical
foi
stacking
other
authors
TEM and
faults
as
well
asymmetrical
were
not
found.
bound
b} dislocations in contrast to stacking faults
and, thus, have no gettering capability [80]. In other words, the gettering activity
of the polysilicon layers used in this study is stiongly reduced during the frontare
not
97
6.4 External
Getteiing
Fig.
TEM
6.23:
loi Waleis with Reduced Inteistitial
micrograph
of
a
single grain
in
a
Oxygen
realigned
PBS
layer.
0 1 pm
j
Bright field (a) and dark field (b) XTEM photograph of a microtwin in a realigned PBS layer. Note the symmetrical sequence of fringes,
from dark to dark in (a) and from bright to bright in (b).
Fig.
6.24:
end ot
a
CMOS piocess with well dnve-m anneals at l 15(EC On the other hand,
the giam boundaiies between
leahgned polysilicon
capacity ol the wafei.
98
should
lemamum
provide
a
smsle giams and then sunounding
certain
contnbution to the total
gettering
6
6.4.2
Compatibility
Back Side
Issues Between Sensor- and IC Device
Technology
Damages
first
experiment performed for comparison, as-damaged wafers were investi¬
gated using the damage test (sec text above and Fig. 6.21). Wafers (O^) treated
with a soft (SDS) and a hard (SDH) mechanical damage were used. The density
of crystal defects generated during the damage test is shown in Table 6.4.
In
a
of
Type
2.7-105
SDH
I-107
Defect
density
test
Stacking
faults with
observed
on
density
the back sides of
faults, dislocations
orders of
a
SDS wafers have the
stacking
'l.l-lO5
faults
length [urn]
23
8.3-104
10-22
SF:
damaged
Stacking Faults).
of around lO^cm""" and
a
found. The
same
(OiSF) The OiSF
on
identified
were
stacking
SDH wafers is two
wafers. Because all
were
22 pm
In addition to
of dislocations
length, they
wafers after the
length of
both, SDS and SDH wafers.
density
magnitude higher compared to SDS
were
SF
at the back surface of
(D: Dislocations,
damage
S F [cm "1
[cm""]
SDS
Table 6.4:
on
D
Damage
as
stacking
faults
oxidation induced
obviously, nucleated at the damage at the
wafer back. They grow by the absorption of silicon self-ititerstitials generated by
the oxidation (see end of Chapter 6.2). Stacking faults at SDH wafers have a cer¬
tain length variation because the very high density of dislocations influences their
growth. Photographs of preferentially etched back sides of the damage-tested
wafers arc shown in Fig. 6.25. Obviously, the wafers have gettering activity as
specified by the wafer manufacturer.
Stability
were,
of
damages during CMOS processing
In order to evaluate the temperature stability of the damages during
cessing, SDS and SDH wafers were exposed to thermal simulations
end of two CMOS processes (CMOS1 and CMOS2 (see
mal
processing,
all
layers
CMOS pro¬
of the front-
Fig. 6.20)). After ther¬
deposited during processing were stripped
and the wafers were investigated using the damage test. It should be pointed out
that, if the damage test performed on wafers pre-processed with certain process
steps gives high defect densities, the gettering activity of the damage is main¬
grown
or
tained after these process steps. The
damage
test
performed
on
the
pre-processed
99
6.4 External
Gettering
fault
Stacking
Fig.
for Wafers with Reduced fnterstitial
Dislocation
Photographs
6.25:
Oxygen
of defects grown at the back of
(b) a SDH wafer after the damage test;
tially etched using theYang-etchant.
and
wafers resulted in
substantially
the
samples
(a)
a
SDS wafer
were
preferen¬
reduced defect densities
compared to wafers
without thermal pre-processing. Thus, their gettering capability is strongly
degraded. In Table 6.5, the results of the experiment are shown. Tn particular, no
of
Type
CMOS1
SDS
2.1-104
SDH
l.l-JO5
CMOS2
damage
D
SDS
Table 6.5:
Density
aged wafers
ulations CMOS1 and
stacking
faults
were
7.M03
3.5-104
pre-processed
damage test; the wafers underwent the thermal
CMOS2 (see Fig. 6.21) prior to the damage test.
generated
on
SDS wafers
pre-processed
found
SDS wafers
hand,
CMOS2.
Obviously, out-annealing
occurcd.
-
5.3-104
the other
no
[cirT2]
2.5-103
of defects at the back surface of
after the
SF
-
SDH
100
[cm"2J
Process
dislocations
were
of the
on
damage
nuclei
or
dam¬
sim¬
with CMOS1. On
pre-processed
with
oxidation of them
6
Compatibility
Influence of Oxidations
on
Issues Between Sensor- and IC Device
the
Damage
thermal oxidation of silicon,
During
'Technology
a
silicon
layer
with
thickness of around
a
45% of the total thickness of the oxide grown is consumed. Therefore, it
pected
tions carried out
common
nuclei at the
damage
that
throughout
oxidations,
investigated.
screening
a
afer back
buffer- and
oxidations for well
a
capping
implants
buffer oxide and
a
arc
consumed
during
thermal oxida¬
the CMOS process. To this end, the influence of two
Oxidation of Silicon
Local
film sandwich of
w
was sus¬
buffer oxidation and the nitride
a
arc
oxidation
on
the
damage
nuclei
were
(LOCOS) for device isolation and
performed
at the
LPCVD silicon
openings of a
nitride (ON-stack).
deposition are performed on
nitride layer for LOCOS arc
thin
The
the front- and back
created at the front
Openings in the
side of the wafer only. Thus, the back side remains covered with the ON-stack
throughout screening oxidations and LOCOS and is not further oxidized during
these process steps. Depending on the CMOS process, the ON-stack may be
renewed several times. Approximately 500 A oxide is grown during each buffer
oxidation (1000°C, 30 min). Prior to the drive-in of a boron implant for the pwell of CMOS 1 and CMOS2 (see Fig. 6.21), the silicon nitride layer of the ONstack is removed on front and back in order to grow a capping oxide (1050°C,
20 min) to prevent boron outdiffusion during the p-well drive-in. The final thick¬
ness of the capping oxide is around 1250 A.
of the wafers.
SDS wafers
thermally pre-processed
ited similar defect densities after the
wafers. In order
to
obtained
a
ping oxide
delect
layer
p-well
were
was
drive-in
to not
pre-processed
capping oxidation,
a
number of
covered with the ON-stack. On part of the
wafers, the
stripped
from front and back. Both types of wafers
including capping
oxidation. The
growth of the cap¬
layer considerably reduced the
found at the back of the wafers after the
defect densities
of the ON-stack exhib¬
damage-test compared
the wafers without the nitride
on
density
generation
evaluate the influence of the
SDS and SDH wafers
silicon nitride
with the
damage
test. The
obtained
displayed as a function of the oxide thickness in Fig. 6.26.
Only on SDH wafers, the density of stacking faults remained in the same order of
magnitude compared to as-damaged and subsequent!} damage-tested wafers.
The results indicate that a critical thermal oxide thickness of around 500 Â on the
are
wafer back should not be exceeded in order to preserve the
the
gettering activity
of
damage.
101
6.4 External
for Wafers with Reduced Interstitial
Oxygen
tAc—
bUb U
10e
«-
SDSSF
105
*-
SDH D
104
*-
SDHSF
Gettering
10e
10
(M
7
_
C/)
c
CD
T5
-t—<
O
(11
103
CD
Q
irv=
500
0
1250
Oxide thickness
Fig.
the
the
[Â]
Density of defects at the back surface of damaged wafers after
damage test; the wafers were exposed to different oxidations prior to
damage test.
6.26:
Activation of
the
During
damages
damage test performed
locations and
damage
test
stacking
as
are
'as
grown.
damaged' wafers
a
high density
Therefore, it is obvious
damage-activating pre-anneak
a
the
faults
on
to
of dis¬
employ
the
After
stripping of the oxide
as a starting material for
grown
during
CMOS
processing with built-in external gettering. On the other hand, the genera¬
stacking faults at the front side of the wafers due to the pre-oxidation must
tion of
damage
test, the wafers may be used
be monitored.
In addition to the
pre-anneal.
The
damage-test, a
defect generation
wet
on
oxidation for 1 hr at 1100°C
was
used
as
the wafer back and front due to the different
pre-oxidations is displayed in Table 6.6. Due to the shorter oxidation time for the
second pre-anneal, the length of the stacking faults is reduced. A few OiSF with a
„O
density of 3 10 cm" were found at the front side of the wafers after the differ¬
~
-
ent
pre-oxidations.
Stability
The
stability
1100°C)
102
of activated
was
damages
of the defects
investigated
generated by
in further
one
of the
experiments.
pre-oxidation (wet,
To this
1 hr at
end, the pre-oxidized
Compatibility
6
Activation of
Damage
Wet
Issues Between Sensor- and IC Device
damage
(see Fig. 6.21)
test
1 hr
ox.
IcnG2]
D
CMOS I
etchant
the
stripped
were
2.7-KE
J.l-105
5
23
2.3-104
1.9-105
3
15
pre-oxidations
was
made in
our
to
were
the thermal simulations
crystal
annealed out.
at
(SDS).
defect charactcri7ation
that most of the
density
using
the
defects grown
Especially,
Yang
during
stacking
no
experiments,
publication [93]: damage-created stack¬
prolonged annealing and only dislocations are
an
faults start to break down after
left. In
wafers
exposed
the defect
on
found after the thermal processing in both, SDS and SDH wafers. A
similar observation
ing
damaged
processing,
was
were
length
[pml
performed. It turned out
pre-oxidation disappeared, i.e..
faults
SE
(Front)
from the oxide and
CMOS2. After
or
[cm"2]
(Back)
the back and front surface of soft
wafers
SF
(Back)
Influence of different
Table 6.6:
fcnG2]
SF
Technology
older
dislocations
surv
ived the thermal
processing
to a certain
extent. Their
density is reduced b} about one order of magnitude compared to
samples without annealing. The influence of the stability test on dislocation and
stacking fault density is shown in Table 6.7.
Thermal simulation
SDS
D
[cm
~2]
SF
SDH
->
[cm"-],
D
[cm-"]
length [pm]
None
pre-oxi-
(as
5.3-104
5-10\
16
SF
[cm-2],
length Ipm]
1.6-
HI7
1.3-104,
10-22
dized)
1150°C.
for
(CMOS2
well-drive
6hrs
5.7-106
1.3-103
3.6-10'
without
1)
CMOS1
Table 6.7:
4-104
Influence
defects at the back of
of
different
-
annealing steps on the density
damaged and pre-oxidized damaged wafers.
of
103
6.4 External
Gettering
After the different
for Wafers with Reduced Interstitial
stability
frequently
tests, etch
observed
pits of
the
dislocations
samples.
On
Oxygen
arranged in
a
'twin'
prolonged
Sccco etch experiment was carried out. Photographs of this experiment arc
shown in Fig. 6.27. During Secco etching, the etch pits grow and approach each
other. Obviously, both dislocations belong to a single dislocation line (half loop).
structure were
2.5 min
Fig.
one
5 min
Photographs
6.27:
on
of
a
sample,
a
10 min
prolonged Secco
pits.
etch
experiment
on
an
individual 'twin' structure of dislocation etch
6.4.3
Conclusive Remarks (External
The
(Oj
density
6.0
=
ages
-
(BSD)
of
6.9
•
was
gettering-active defects in low interstitial oxygen CZ-wafers
10 cm""1) with polysilicon back sides (PBS) or back side dam¬
investigated.
for the fabrication of
etching
Gettering)
Material of this kind is
required
Low interstitial oxygen PBS material showed enhanced
stacking
faults
tain
material
and genera¬
An RTA treatment at
precipitation
caused
by
the
deposition.
During
ment
precipitation
during CMOS processing.
1050°C for 3 min is efficient to supress enhanced
PBS
starting
CMOS-integrated silicon microsensors by wet anisotropic
bulk crystal defect generation and gettering capability.
due to its low
tion of bulk
as
well drive-in anneals
of the PBS
was
at
1150°C
observed. On
some
longer
than 6 firs,
epitaxial realign¬
samples, large single grains with a cer¬
an
gettering capacity due to their grain boundaries remained. Thus, the gettering
capability of the PBS is strongly degraded during CMOS processing.
104
6
Compatibility
Issues Between Sensor- and IC Device
Technology
Back side
showed
a
damaged wafers, especially the hard mechanical damaged (SDH),
better functionality. A wet oxidation at H00°C (damage test) was used
to evaluate the
gettering activity
faults and dislocations grow
defects introduced
the
by
during
damage.
the front-end of
Prolonged dry
a
damage. Crystal defects,
the
oxidation, nucleated
At the back of SDH
iforf
of dislocations of 1.1 /E
density
of the
~
CMOS process (CBT,
oxidations reduce the
obtained after
was
such
by
wafers,
a
as
stacking
micro
crystal
considerable
a
thermal simulation of
Chapter 1.4) and the damage test.
functionality of BSD by oxidizing the damsee
o
aged layer
at the
wafer back. The thickness of the oxide should not exceed 500 A
in order to preserve the
Activation of the
ate
a
damaged layer.
damage by
a
wet
oxidation (1 hr at 1100°C)
was
found to gener¬
network of defects with reasonable
cessing.
damage
A dislocation
was
of
density
obtained
after
a
stability against subsequent thermal pro¬
3.6A;l"tbm"~ on SDH wafers with activated
thermal
simulation of the
front-end of CBT
(CMOS1).
conclusion, the external gettering methods investigated suffer from strong
In
decay
of
their
mechanical
functionality
damage (SDH) is
gettering-active crystal
As
ity.
6.0
of
-
a
6.9
•
considered the best candidate to
10l7eui"3
defects for wafers with reduced internal
and SDH will be used
as
standard
starting
The
provide
hard
additional
gettering
result, silicon wafer material with reduced interstitial
integrated
6.5
during high-temperature processing.
capac¬
of
oxygen
for the fabrication
sensors.
Influence of
Doping Concentration
on
Anisotropic
Etching
Weakly doped epitaxial layers on heavih doped substrates (p/p4 or n/n+) are rou¬
tinely used to improve latch-up stability in modern commercial submicron
CMOS processes [94]. It is well known that
reduced etch rate in
depends strongly
on
tion range for the
the amount of
doping
wafer manufacturer (0.005
In
our
experiments,
alkaline etchants
wet
a
doping.
silicon has
[21]. Furthermore, the etch
Because of the
level of the wafer
-
heavily boron-doped
starting
a
rate
fairly large specifica¬
material delivered
by
the
0.02 Qcm). the etch rate varied from wafer to wafer.
reduction of the etch rate of 12
-
30%
was
observed.
105
6.5 Influence of
Doping
Concentration
on
Anisotropic Etching
applications, the standard p/p"f epitaxial starting
material for the 0.8 pm CMOS technology (CY-, see Chapter 1.4) was replaced
by a non-cpi material with a bulk resistivity of 14 24 Ocm and reduced interstitial oxygen of 6.0-6.9
10 cm"'1. Epitaxial wafers with a bulk resistivity of
O.Ol Dem and reduced interstitial oxygen are currently under investigation. A
bulk resistivity of 0.01 Qcm corresponds to a boron concentration of 1-10 cm
thus, the etch rate of wafers of this kind should not be reduced compared to mate¬
rial with a high bulk resistivity. On the other hand, immunity against latch-up
should be maintained using this material.
Therefore, for integrated
sensor
-
•
,
106
7
Summary
7
Summary
and Outlook
Outlook
and
implementation of additional process steps required for silicon microsensor
fabrication using wet anisotropic etching with an electrochemical etch-stop into
The
commercial CMOS
Unterpremstàtten,
device
Austria
technologies
co-integrated
of Austria Mikro
technologies
demonstrated. The features of the
core
CMOS
remain untouched. Thus, the fabrication of silicon
sensors
was
with standard CMOS circuits for. e.g., offset
A/D conversion of the
steps comprise
International AG,
Systeme
raw
sensor
the formation of
a
signal
is
possible.
compensation
The additional
contact network and contact
areas
and
processing
for the sup¬
of the electrochemical
ply
back. The additional
nology and
potentials to the wafer and the masking of the wafer
processing is independent from the particular process tech¬
the wafer diameter. Thus, it
can
be added
easily
to other IC device
technologies.
The
of
developed CMOS sensor technology
integrated microsystems developed at
Examples
include force
low-noise
amplifiers
sensors
is the
the
for AFM's
and smart chemical
technological base for a variety
Physical Electronics Laboratory.
co-integrated
sensors
with
with
fully
differential
on-chip sigma-dclta
modu¬
lators.
Investigations
influence
out. It
on
was
of the
level and defects in the bulk of the wafer and their
silicon etch rates and
found that bulk
cessing strongly
this kind
doping
cr\
quality of etched
structures have been carried
stal defects present in the wafers after CMOS pro¬
deteriorate the
quality
of the fabricated structures. Defects of
employed for internal gettering of impurities
density of crystal defects could be drastically reduced using
are
in IC processes. The
wafer material with
a
3
slightly lower initial concentration of interstitial oxygen (6.0 6.9-1017cm"
compared to the standard value of 8.0 10 cm"1). Using this material, the qual¬
ity of the fabricated structures was strongly improved. Due to the low concentra¬
-
tion of defects in wafers with reduced oxygen
capability is strongly reduced. Therefore,
layer on the wafer back and damaged w afer
result, weakly p-doped
concentration, their gettering
external
gettering using polysilicon
back surfaces
were
investigated.
As
a
substrates with reduced interstitial oxygen concentration
107
of 6.0
-
6.9-10
standard
and
cm
starting
a
hard mechanical
material for the
developed
damage
sensor
at the
process
back side
are
used
as
technology.
Future research
Future research and
•
development
has
to
adrcss the
following topics:
The
advantages of the standard CMOS process core in the developed
technology should be fully exploited, e.g., integration of digital signal
processors
(DSP) and microprocessor
cores
with silicon
sensors
is feasi¬
ble.
•
•
A first level
packaging technique should be added to the technology, e.g.
electrostatic bonding of pre-processed and micromachined substrates to
Pyrex glass wafers. The development of this techniques is an important
requirement for the possible commercialization of the integrated sensor
fabrication technology.
A
new
doped
starting
substrate
material with
exhibiting
a
a
lightly doped epitaxial layer
low bulk defect
Material of this kind is
generation
on a
heavily
has to be devel¬
oped.
required for integrated sensor fabrication
using IC processes with smaller feature sizes (down to 0.25 pm) due to its
improved latch-up immunity.
108
REFERENCES
[1]
Nexus Task Force
Report,
Market
Analysis
for
Microsystems 1996-2002,
1998.
12]
Autoliv Inc.,
[3]
Robert Bosch GmbH.
tronic
14]
Sweden, Airbag restraint systems, in http://www.autoliv.com.
Germany,
Stability Program.
DaimlerChrysler AG,
Coupe,
in
Vehicle
ESP), in
Dynamic
Control
http://www.bosch.com.
Active
Body Control (ABC)
http://www.mercedes-bcnz.eom/c/cars/.
for Mercedes Benz CL
Robert Bosch GmbH,
[5]
Germany. Bosch Parktronic, Parking
http://www.bosch.de/de___e/news/.
[6]
Robert Bosch GmbH,
tem, in
Germany.
http://www.bosch.de.
System (Elec¬
ME 7 Motronic
aid system, in
engine management
sys¬
[7]
Eberspäclicr GmbH, Esslingen, Germany, Catalytic converters,
www.eberspaecher.de.
[8]
Temic GmbH,
Germany,
http://www.temic.de.
19J
Delphi Automotive Systems Inc.. USA, Forewarn1 M Collision-Warning
Systems Technology and Adaptive Cruise Control (ACC), in http://
www.dclphiauto.com.
[101
Federal
Automotive Distance Control
Highway Administration, USA,
Automated
in
http://
System (ADC),
Highway Systems,
in
in
http://ahs.volpc.dot.gov/.
109
References
[11]
N.
Murakami, M. Kira, Application of Gas Sensor for Air Damper Control
in Automobiles, Tech.
Systems
Automotive
[12]
tions
[13]
Systems
for Car
Passengers by
Digest of Advanced Microsystems
98, Berlin, Germany, March 26-27, 1998, p.
Analog Devices, Inc., USA, ADXL50,
VTI
March
Tech.
Signal Conditioning,
[14]
of Advanced
Applications 98, Berlin, Germany,
C. Voit, Protection
Quality,
Digest
Microsystems
for
26-27, 1998, p. 303.
Surveillance of the Air
for Automotive
Applica¬
307.
Monolithic Accelerometer with
Data Sheet. 1996.
Hamlin, Finland, SCA 100. Low-g accelerometer, in http://www.vti.fi/
Products.
[151
Motorola Inc., USA, MPX4J00, MPX4101
Pressure
[16]
Series, Manifold Absolute
Sensors, Data Sheets, 1995.
Robert Bosch
GmbH, Germany, SMD 022, Absolute Pressure Sensor, Data
Sheet, 1997.
117]
W.
Golderer,
II.
Münzel, and U. Bischof,
Technology
M. Lutz, J. Gerstenmeier, J.
Yaw Rate Sensor in Silicon
for Automotive
Microsystems
Marek, B. Maihöfcr, S. Mahler,
for Automotive
Applications,
Tech.
Micromachining
Digest of Advanced
Applications 98, Berlin, Germany,
March
26-27, 1998, p. 69.
[18]
J.M. Bustillo. R.T. Howe, and R.S.
Microclectromechanical
Muller. Surface Micromachining for
Systems. Proceedings
of the
IEEE, 86,
1552,
(1998).
[19]
G.T.A. Kovacs, N.I. Maluf, and K.E. Petersen, Bulk
Micromachining
of
Silicon, Proceedings of the IEEE. 86. 1536, (1998).
[20]
K.E.
Petersen, Silicon
70,420,(1982).
110
as a
Mechanical
Material, Proceedings of the IEEE,
[21]
H.
Seidel, L. Csepregi, A. Hcuberger, H. Baumgärtel, Anisotropie Etching
of
Crystalline
Silicon in Alkaline Solutions, J. Electrochcm. Soc, 137,
3612, (1990).
[22]
H.A.
Bell
123]
Waggener, Electrochemically
Syst. Tech. L, 49, 473, (1970).
Controlled
T.N. Jackson, M.A. Tischler, and
Junction
Etch-Stop
K.D.
Thinning
of Silicon, The
Wise, An Electrochemical P-N
for the Formation of Silicon Microstructures, IEEE
Electron Dev. Lett., 2, 44, ( 1981 ).
[24]
J.M. Giachino, Smart
[251
J.M.
Borky,
sure
Sensors,
Sensors, Sensors and Actuators A, 10, 239, (1986).
K.D. Wise,
Integrated Signal Conditioning
IEEE Transactions
on
Electron
for Silicon Pres¬
Devices, ED 26,
1906,
(1979).
[26]
D. Arand, J. Marek, K.
Pressure Sensor with SMD
Packaging: Example
Packaging,
Publications 960756. Sensors and
in SAE
(SP-1133), 1996,
127J
Weiblen, and U. Lippliardt, Integrated Barometric
K.
Special
of Standardized Sensor
Actuators,
p. 23.
Sooriakumar, R. Verma. T. Maudie, and M. Shah, An Integrated Silicon
Bulk Micromachincd Barometric Pressure Sensor for
and External Mount, SAE
ators.
f28]
Special
Publications
(SP-1220), 1997, p. 67.
H. Crazzolara, G.
Flach, and W.
von
with Overload Protection and Low
tors
[29]
T.
Engine Control Unit
970610, Sensors and Actu¬
Miinch, Piezoresistive Accelerometer
Gross-Censitivity,
Sensors and Actua¬
A, 39, 201, (1993).
Ishihara, K. Suzuki, S. Suwazono. M. Hirata. and H. Tanigawa, CMOS
Integrated Silicon
151,(1987).
Pressure Sensor, IEEE J. of Sol. Si. Circuits,
SC-22,
Ill
References
[30]
H.-J. Kress, F.
witli
Banticn, J. Marek and K. Willmann, Silicon Pressure Sensor
Integrated
CMOS
Signal-conditioning
Temperature Coefficient.
[31]
EI.
Seidel,
with
8th Int. Conf.
ers'95), Stockholm,
[32]
Sensors and Actuators A,
Compensation
of
25-27, 21, 1991.
U. Eritsch. R.
Accelerometer
Digest
Circuit and
LP. Schuster, W.
Gottingcr and J. Schalk, A Piezoresistive Silicon
Monobthically Integrated CMOS-Circuitry, Tech.
on
Sol id-State Sensors and Actuators
(Transduc-
Sweden, June 25-29. 1995. p. 597.
Czarnicki, X. Ding, Monolithic Pressure Sensor System
with
Digital Signal Processing, Tech. Digest Advanced Microsystems for
Automotive Applications 99, Berlin, Geimany, March 18-19, 1999, p. 297.
133]
H.
Baltes,
A. Kolk D.
Proceedings
Lange.
The CMOS MEMS Nose
of the IEEE International
Symposium
on
-
Fact
or
Fiction?,
Industrial Electron¬
ics, New York, NY, USA, 1997, p. 1635.
[34]
Schweizerische
Eidgenossenschaft,
schaft, Schwerpunktprogramme, in
Bundesamt für
Bildung und
http://www.admin.ch/bbw/.
Wissen¬
Austria Mikro
[35]
Systeme International AG. Unterpremstätten, Austria, Pro¬
in http://www.amsint.com/products/
cess Technology Reference Guide,
technology/.
136]
R. Huster, and A. Stoffel,
Electrochemical
[37]
T.
Etching,
Vertically
Structured Silicon Membranes
by
Sensors and Actuators A. 23, 899. (1990).
Müller, T. Feichtinger, G. Breitenbach, M. Brandi, O. Brand, and H.
Baltes.
N-well
Micro
Industrial
Fabrication
Method
for
Arbitrarily Shaped Silicon
Micromcchanical Structures, Proceedings IEEE Workshop on
Electro Mechanical Systems 1998, Heidelberg, Germany, Jan.
25-29, 1998. p. 240.
L38]
[39J
112
SEZ AG,
Villach,
Austria,
www.sez.com,
(1999).
B. Fankhauser.
Diploma
SEZ
Spin
Process
Technology,
Thesis. ETH Znrich/TU Graz, p.
in
30, (1998).
http://
[40|
B.
Kloek, S.D. Collins, N.F. de Rooij and R.L. Smith, Study of Electro¬
chemical
Etch-Stop
branes, IEEE
[41 ]
A.J.
for
Transact,
High-Precision
on
Thickness Control of Silicon Mem¬
Electron Dev.. 36,
663, (1989).
Bard, L.R. Faulkner, Electrochemical Methods, Wiley, New York, NY
(1980).
[421
T.
[43]
R.L.
Fcichtinger, Diploma Thesis,
ETH Zurich/TU
Graz, p. 10, (1997).
Smith, B. Kloeck, N.F. de Rooij. S.D. Collins, The Potential Depen¬
dence of Silicon
Anisotropic Etching
in KOH at
60°C, J. Electroanal.
Chcm., 238, 103,(1987).
[44]
M.C. Acero, J. Esteve, Chr. Burrer, A.
Götz, Electrochemical Etch-Stop
Characteristics of TMAILÏPA Solutions, Sensors and Actuators A,
46-47,
22, 1995.
[45]
T.A. Kwa, R.F. Wolffenbuttcl, Effect of Solution Contamination
Silicon
on
Etched
Surfaces, Journal of Micromechanics and Microengineering, 5, 95,
(1995).
146]
M.
FJornung, Micromachined Ultrasound-Based Proximity Sensors, Ph.D.
Thesis, ETH Zurich. (1998).
[47]
M.
Hornung, O. Brand, O. Paul.
H. Bakes, C. Kuratli, and
Micromachined Acoustic Fabix-Perot
System
for Distance
Proceedings IEEE Workshop on Micro Electro
Heidelberg, Germany, Jan. 25-29, 1998, p. 643.
[48]
G.
Binnig,
Rev. Lett.,
149]
D.
Lange,
C.F.
Quate,
Systems,
Microscope, Phys.
56, 930. (1986).
T.
Akiyama,
C.
AFM with
Hagleitner,
Rooij,
on
A.
Tonin, H.R. Hidber, P. Nieder¬
O. Brand, and H. Baltes, Parallel Scan¬
On-Chip Circuitry
Workshop
USA, January 17-21, 1999.
IEEE
Mechanical
and Ch. Gerber, Atomic Force
mann, U. Staufer, N.F. de
ning
Q. Huang,
Measurement,
in CMOS
Micro Electro Mechanical
Technology, Proceedings
Systems, Orlando, Florida,
p. 447.
113
References
1501
F.
Mayer,
A.
Häberli, H. Jacobs, G. Ofncr, O. Paul, H. Baltes, Single Chip
Anemometer, Proceedings IEEE International Electron Devices Meeting
IEDM'97, Washington DC, USA,
151]
M.
CMOS
Chip
Electro Mechanical
FI.
Chip, Proceedings IEEE Workshop on Micro
Systems, Nagoya, Japan, January 26-30, 1997, p. 512.
on
Balles, D. Lange, and A. Koll, The Electronic Nose in Lilliput, Special
report
[53]
1997, p. 895.
Schneider, T. Müller, A. Häberli, M. Hornung, and H. Baltes, Integrated
Decoupled
[52]
Dec. 7-10,
in
IEEE
Spectrum,
35
,
35, (1998).
C.
Hagleitncr, A. Koll, R. Vogt, O. Brand, and H. Baltes. CMOS Capacitive
Chemical Microsystem with Active Temperature Control for Discrimina¬
tion of Organic Vapors, Tech. Digest of the 10
Int. Conf. on Solid-State
Sensors and Actuators
(Transducers '99) Senclai, Japan,
June
7-10, 1999,
p. 1012.
[54]
S. Marco, J. Samitier, J. R. Morantc. A. Götz and J. Esteve, Three Dimen¬
sional Structures Obtained
Stop,
by
Double Diffusion and Electrochemical Etch
J. of Micromcchanics and
Microengincering,
3, 141, (1993).
[55]
C.
Dcnissi, Novcllus Systems Inc., personal communication.
[56]
U.
Munch, N. Schneeberger. O. Paul, H. Baltes and E. Doering, Thin Film
Front Protection of
chined Devices
Fully Processed CMOS Wafers, Proc. Symp. Microma¬
and Components SP1E 3514. Santa Clara, Sept. 21-22,
1998, p. 124.
[57]
D.
Eichncr, W.
von
Munch, A Two Step Electrochemical Etch-Stop
duce Free
Standing Bulk Micromachincd Structures,
Leuven, Belgium, Sept. 9-11, 1996. p. 203.
[58]
E.P. Plueddemann, Silane
New York
[59)
F. Secco
Coupling Agents,
2nd
to Pro¬
Proc. Eurosensors X,
Edition, Plenum Press
(1991).
d'Aragona.
trochem. Soc.
Dislocation Etch for
119, 948, (1972).
(100) Planes in Silicon,
J. Elcc-
160]
T.
Müller, T. Fcichtinger, B. Bankhäuser, A.C. Benkitsch, O. Brand, and H.
Baltes, Surface Quality of Anisotropically Etched Grooves in CMOS Sili¬
con
Wafers with Internal
Proc. Micromechanics
1998,
[61]
A.
Gettering
-
the Role of the
Ulvik in
Europe.
Oxygen Content,
Hardangcr, Norway,
June
in
2-5,
p. 59.
Hein, G. Findler, S. Finkbeiner, H. Miinzek E. Obermeicr, The Effect of
in Silicon
Impurities
Digest
of
on
Anisotropic Etching
in
KOH-Solutions, Tech.
Microsystem Technologies '98, Potsdam, Germany,
Dec.
1-3,
1998, p. 409.
[62J
A.
Hein, S. Finkbeiner, H. Münzel, J. Marek, E. Obermeicr, The Effects of
Thermal Treatment of CZ- and FZ-Silicon
and the
in
Etching
Digest
ference
Behavior
of Technical
Crystal Defect Formation
During Anisotropic Etching in KOH Solutions,
Papers
on
of TRANSDUCERS
'99, International Con¬
Solid-State Sensors and Actuators. Scndai,
on
Japan,
7-10,
June
1999, p. 1090.
163]
T.Y. Tan and W.D.
Taylor, Mechanisms
Quantitative Aspects, in Semiconductors
Silicon,
1641
G.
F.
of
Oxygen Precipitation:
and Semi metals, VI,
Some
Oxygen
in
Shimura, Ed., Academic Press, New York (1994).
Kissinger,
J. Vanhellemont, U.
Lambert, D. Graf, E. Dornberger, and H.
Richter, Influence of Point Defect Supersaturation
Grown-ln Oxide
Precipitate
on
the Formation of
Nuclei in CZ-Si, J. Electrochem. Soc,
145,
L75(1998).
165]
Meyer. Physikalisch-chemische Kristallographie, VEB
lag für Grundstoffindustrie, Leipzig, Germany, (1977).
[661
J- C.
K.
Mikkclsen, The Diffusiv ity and Solubility of Oxygen in Silicon, Proc.
of Mater. Res. Soc.
|671
G.
Deutscher Ver¬
Kissinger,
Symp., 59,
T. Grabolla, G.
p.
19(1986).
Morgenstern,
hellemont, U. Lambert, and W.
von
IT.
Richter, D. Graf, J. Van¬
Amnion, Grown-in Oxide
Precipitate
Nuclei in Czochralski Silicon Substrates and Their Role in Device Pro¬
cessing,
J. Electrochem. Soc. J46, 1971
(1999).
115
References
168]
O. De
Gryse,
Stoichiometry
and
Oxygen
Content in Platelike and Octahedral
in Silicon with FT1R
Precipitates
ence on
Clauws, J. Vanhellcmont and C. Claeys, Determination of
P.
Spectroscopy,
169]
July ,Aveiro, Portugal,
in
1997).
S. Senkadcr, G. Hobler, C. Schmciser, Determination of the
itate-Silicon-Matrix Interface
Energy by Considering
cipitate Morphology, Appl. Phys.
[70]
19th International Confer¬
Defects in Semiconductors, 1CDS 1997,
Materials Science Forum. 258-263, 405 (
Oxygen
yy. Zulehner,
Oxygen
Oxide-PrecipChange of Pre¬
Lett., 69, 2202 (1996).
Related Defects and
stein New Series 111722b, O.
the
Microdefects, in Landolt-Börn-
Madelung, Ed., Springer, Berlin, Germany
(1989).
171]
Esfandyari, G. Obernieier, E. Dornberger, D. Graf and
Kissinger, Recent Progress in Understanding Oxygen Pre¬
J. Vanhellcmont. J.
U. Lambert, G.
cipitation
ceedings
[72]
K.H.
in Silicon, PV98-13, p. 101, The Electrochemical
Series,
Yang,
Society
Pro¬
Pennington, NT, (1998).
An Etch for Delineation of Defects in
Silicon,
J. Electrochem.
Soc, 131, 1140(1984).
[731
U.
Schnakenberg.
Micromachining,
W.
in
Benecke, P. Lange, TMAHW Etchants for Silicon
Digest
International Conference
of Technical
on
K. Marsdcn, T.
Kanda, M. Okui. M. Hourai, and T. Shigematsu, Determi¬
Oxygen Precipitates
[76]
Pressure
Quality
Crystals,
of
Ring-OSF
Mat. Sei.
from Small
Eng. B, 36,
16
As-grown
(1996).
{11 1} Side-walls in KOH-etched Cavities
Sensors], Sensors and Actuators A, 60, 244 (1997).
H. Schröder, E. Oberineier, A.
Steckenborn, Effects of the Etchmask Prop¬
erties
Anisotropic Etching of {100}
Microeng., 8, 99 (1998).
on
the
Anisotrop}
Aqueous KOH,
116
in CZ-Si
C. Merveille, Surface
[for
'91,
p. 815.
nation of the Criteria for Nucleation of
f75]
of TRANSDUCERS
Solid-State Sensors and Actuators, San Fran¬
cisco, USA, June 24-25, 1991,
[74]
Papers
Ratio in
J. Micromcch.
Silicon in
[77]
G. Findler, J. Muchow, M. Koch and H. Münzel,
Temporal
Evolution of
Silicon Surface
Roughness During Anisotropic Etching Processes, in Proc.
of the 5th IEEE Workshop on Micro Electro Mechanical Systems,
Travemiinde, Germany, Feb. 4-7. 1992, p.62.
178]
D.L.
Kendall, G.R. de Guck and S. Gucl-Sandoval, Chemically Etched
Micromirrors in
Silicon, E.J. Garcia and
T.A. Allen.
Appl. Phys. Lett., 52,
836(1988).
[791
R.B.M.
Girisch, Indiffusion and Polysilicon Backside Gettering of Iron
During Oxidizing
Multiple High-Temperature Steps, in Crystalline
Defects and Contamination: their Impact and Control in Device Manufac¬
turing, B.O. Kolbesen, C. Claeys, P. Slallhofer, F. Tardif, Editors,
and
PV93-15, p. 170. The Electrochemical Society Proceedings Series.
nington,
[80]
D.M.
NJ
(1993).
Lee, K. Mishra, W. Huber. S. Chevacharoenkul, S.P. Choi, and I.H.
Doh, Iron Gettering Efficiency bv
a
con, in Semiconductor Silicon 1994,
cal
181]
Society Proceedings
of
Stacking
and Contribution to
P-type
CZ Sili¬
PV94-10, p. 820, The Electrochemi¬
Pennington,
NJ
Faults
during
Leakage,
CMOS
(1994).
Processing: Origin,
J. Electrochem.
Elimination
Soc, 127, 716 (1980).
Kirscht, M.B. Shabani, T. Yoshimi. S.-B. Kim, B. Snegirev, C. Wang,
L. Williamson. K. Takashima, P. Taylor, and D. Lange, Strain and Getter¬
Silicon Wafers, in Solid State Phenomena, 57-58, 355
F. Shimura and R. Craven. Process-Induced Microdefects in VLSI Silicon
Wafers, in Proceedings of the AIP Conference,
Institute of
184]
in
F. G.
ing in Epitaxial
(1997).
183]
Series,
Polysilicon Layer
S.P. Murarka, T.E. Seidel. .I.V. Dalton. J.M. Dishman, and M.H. Read, A
Study
[82]
Pen¬
D.
no.
122, p. 205, American
Physics (1984).
Graf, Wacker Sdtronic AG, Burghausen. Germany, personal communi¬
cation.
117
References
[85]
J. Partanen, T.
Tuomi, M. Tilli, S. Hahn, C-C.D. Wong, F.A. Ponce, Thin
Film Backside
Gettering
ulated CMOS Process
186]
R.
1871
H.
Sim¬
Ealster, M. Cornara, D. Gambaro. M. Olmo, and M. Pagani, Effect of
High Temperature
in
N-type (100) Czochralski Silicon During
Cycles, J. Mat. Res., 4, 623 (1989).
in
Si, in Solid State
Miyairi,
S.
Oxygen Precipitates
Phenomena, 57-58, 123 (1997).
Pre-Anneal
Tsuchiya,
Wafer with Back-Surface
on
Nucleation Kinetics
Suga, Warp of Czochralski
Polycrystalline Silicon Film, Jpn. J. Appl. Phys.,
H. Yoshioka and H.
32,3687(1993).
Wijaranakula and LH. Matlock, Morphology of Microdefccts Formed
at the Polycrystalline Silicon and Substrate Interface after Epitaxial Depo¬
sition and Subsequent High-Temperature Annealing, J. Electrochem. Soc,
137,2980(1991).
f88]
W.
189]
J. D. Williams and P. Ashburn,
talline Silicon
Layers Given
Epitaxial Regrowth of n+ and p+ Polycrys¬
Single and Double Diffusions, J. Appl. Phys.,
72,3169(1992).
[90]
[91]
T.-Y.
X.
Zhang,
of
Polysilicon
Zhang.
M.
Wong
and Y. Zohar,
Thin Films, J. of Micromech.
Grundstoffindustrie,
[93]
Syst., 7, 356
-
213, Deutscher Verlag für
G. Lux, R. Manukonda,
Banerjee,
Arsenic
and Boron
Systems,
J. Electrochem.
Phys.
Phasengrenzen
Leipzig, Germany (1977),
K. Park, S. Batra, S.
D.J.D. Thomas,
p.
Annealing
(1998).
Thermal
H.G. Schneider. J. Woltersdorf, Strukturen kristalliner
Elektronenmikroskopischcr Bildkontrast,
192]
Rapid
Diffusion
in
Polycrystalline/Single-Crystal
of
Silicon
Soc., 138, 545 (1991).
Surface Damage and
Stat. Sol. 3, 2261
Comparison
^
(1963).
Copper Precipitation
in
Silicon,
194]
J.O.
Borland, T. Deacon, Advanced CMOS Epitaxial Processing for
Latch-Up hardening
and
Improved Epilayer Quality,
Sol. St. Techn.,
27,
123,(1984).
119
References
120
Acknowledgments
First of all, I would like
at
to
thank Prof. Baltes for the excellent
PEL, continuous encouragment. and
I wish to thank Dr. O. Brand for the
script of this thesis and other
suggestions and corrections.
I like to thank Dr. G.
in defect
density
proof-reading
exhausting
from IHR
Kissinger
During
of wisdom.
work of
proof-reading the manu¬
provided extremely valuable
Frankfurt/Oder, Germany for her work
the
from her.
gettering
collaboration,
1 learned many
Furthermore, I like
to
things
thank her for
of this thesis.
I wish to thank Dr. A. Häberli. He
I want to thank Dr. V
Eilmsteiner, S.
Plessnioo
secret words
technical papers. He
determination.
about defects and
some
conditions
working
Kempe,
Hellinger,
guided
me
in the first year of the thesis.
M. Brandi. Dr. O.
Leitner, R. Csernicska, Dr. G.
H. Hofstätter. P. Pann, A.
Benkitsch,
M.
Pippau,
H.
Walter Poelzl, Wo If «an s Poelzl, A. Schmid, E. Brandlhofcr, Rainer
Minixholer, Rupert Hütter, IL Kresina, A. Hansemann, P. Elsncgg, and S. Fink
from Austria Mikro
Systeme
International AG for their excellent support, the col¬
laboration, and many stimulating discussions. It
time and 1 will
forget
Praun, Morellenfeldgassc 32,
never
the
evenings
für
grateful
to Dr. D.
Graz each
in my "favorite* restaurant Braun de
Katzer. J.
processings
Bagdahn.
and many fruitful discussions.
F. Altmann from Fraunhofer Institut
Werkstoffmechanik, Halle, German} for
SEM/TEM
to be in
Holzner, and N. Hintcrschwepfingcr from Wacker
Siltronic for non-standard wafers and
am
pleasure
8010 Graz.
I wish to thank Dr. D. Graf, A,
I
was a
a
large
number of FIB cuts and
photographs.
I wish to thank
Jürgen Niess,
STEAG AST Elektronik GmbH, Dornstadt, Ger¬
many for the RTA treatments and Dr. M. Reiche from Institut für Mikrostruktur-
physik, Halle, Germany
for wafer
I want to thank my students T.
polishing.
Feichtingcr,
B. Fankhauser, and S.
from Technische Universität Graz, Austria, for their
important
Uguiiu,
all
contributions to
this thesis.
121
Ac kno wled g me nts
1 wish to thank P.
shop
at ETH
Many people
Brtihwiler,
Zurich for the
from the
H.
Hediger,
and A.
Egi
just-in-time fabrication
Physical
Electronics
from the mechanical work¬
of wafer holders.
Laboratory
have contributed in dif¬
ferent ways to this thesis. I would like to thank Erna
Hug and Yelena von Allmen
for excellent administrative support and D. Scheiwiller, I. Levak, M. Schlapfer,
Ch. Kolb, M. Markwalder for technical assistance.
Furthermore, 1 like
to
thank the scientific staff of the
Physical
Electronics Labo¬
ratory (in alphabetical order): Dr. M. Emmeneggcr, Ch. Hagleitner, Dr. A. Hierlemann, N.
Kerncss, A. Koll, S. Koller, D. Lange, Ch. Maier, M. Mayer, M. Metz,
U. Munch, A. Schaufelbühl. S. Taschini, Dr. R. Vogt, M. Wälti, V Ziebart, M.
Hornung,
F.
Mayer,
Dr. M.
Schneider, and
This work has been funded
tem
Technology (MINAST)
Zurich, Dec. 1999.
122
by
the Swiss
within the
Dr. R. Steiner.
priority program
project AM SYST.
Micro and Nano
Sys¬
List of Abbreviations
List of Abbreviations
AFM
Atomic Force
AMSiAG
Austria Mikro
Microscope
Systeme International AG. Unterprem-
stätten, Austria
BMD
BulkMicrodcfcct
CBT
2.0 pm
CYE
0.8 pm 5 V CMOS process
high voltage
stal
CMOS process
C-Zj
Czochralski
D
Extended dislocation line
Dl
Deionized water
ECE
Wet
anisotropic etching
stop
at
a
p-n
en
(AMSiAG)
(AMSiAG)
growth
with
an
electrochemical etch-
junction
ESD
Electrostatic Discharge
ETR
Epitaxial Realignment
FIB
Focused Ion Beam
FSE
Perfluorodecyltriethoxysilane
FZ
Float Zone
HOX
High
crystal growth
interstitial oxygen concentration,
0,-8.3-9.3- 1017cm~3
LOCOS
Local Oxidation of Silicon
LOX
Low interstitial oxygen
0,
=
7.0-7.7-
concentration,
10l7cnr3
MEMS
Microelectromechanical
MINAST
Swiss
Priority Program
System
Micro und Nano
System Tech¬
nology
123
NMOS
N-channelMOS
NOX
Normal interstitial
0,
=
7.8 -8.3
•
o\\
gen concentration,
1017cm^
OiSF
Oxidation induced
0,i
Interstitial oxygen concentration,
Stacking
Fault
0,-6.0-6.9- JOVm"3
Oi2
Interstitial oxygen concentration,
0,-7.4-7.7
•
1017cm"3
P
Oxide
PBS
Polysilicon
PD
Oxide
PECVD
Plasma Enhanced Chemical
PMMA
Polymcthylmethaery late (Plexiglass)
PS
Punching System
RIE
Reactive Ion
RTA
Rapid
SDH
Standard
Damage
Hard
SDS
Standard
Damage
Soft (Wacker Siltronic AG)
SF
Stackina Fault
STR
Special
(X)TEM
(Gross-sectional) Transmission Electron Microscopy
TMAH
Tetramethyl
VLOX
Very low interstitial
precipitate
Back Side
precipitate/dislocation complex
Etching
Thermal
Test
Annealing
(Wacker Siltronic AG)
Request
Ammonium
Hydroxide
ox}gen
0,-6.0 -6.9-1017cm^
124
Vapor Deposition
concentration,
Curriculum Vitae
Thomas R. Müller
Born
1981
April 12,
-
1965 in Dresden,
German}
education
Vocational
1986
in
communication
and
information electronics.
Berufskolleg,
1986- 1987
Aalen, Ger¬
Gewerbliche Schule
many.
Study of precision mechanics
1987-1988
schule Aalen.
April
-
Fachhoch¬
Germany.
Abitur.
1989
Oct. 1989
at
Sept. 1995
Study
of
Physics
at
the
University
of Konstanz,
Germany.
Sept.
Diploma
1995
Jan. 1996
-
Dec. 1999
Work
in
on a
Physics.
Ph. D. thesis and related
topics
at the
Physical Electronics Laboratory at ETH Zurich
(Prof. Dr. IL Baltes) and Au stria Mikro Systeme
International AG.
Unterpremstätten,
Austria.
125