Solid State Equipment LLC
Silicon Wafer Thinning to Reveal Cu TSV
(Innovation in Middle End Process Cu Via Reveal)
Laura Mauer, John Taddei, Ramey Youssef, Elena Lawrence
European 3D TSV Summit
Grenoble January 22-23,2013
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Outline
• Wafer thinning to reveal Cu TSV
• Silicon etch with KOH
• Integrated Wafer Thickness Measurement
• Process Results
• Summary
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Background
• High cost of TSV processes
• Opportunity to lower costs and improve manufacturing productivity
– Wet etch to reveal TSV
– Integrated Metrology
– Endpoint Detection
 Develop Low Cost Wet Etch Process with
Integrated Metrology

Wafer Thinning to Reveal TSV
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TSV Reveal, Protect and Planarize
Silicon thickness adhesive carrier
Post Grind
Via depth adhesive carrier
After Si Etch
– TSV Revealed adhesive carrier
Oxide/Nitride deposition to protect Si surface from Cu adhesive carrier
Surface planarized and Cu vias exposed
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TSV Reveal: Process Options post Grind
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Why KOH as etchant?
• Requirements for Etchant:
– Good etch rate for Silicon
– Does not etch SiO2 or Copper
• Possible Candidates:
Silicon Etch Rate
(µm/minute)
TMAH 0.3-0.5
KOH 1.5-2.0
– Higher etch rate for KOH
 Faster single wafer process
 Higher throughput and lower CoO

Wafer Thinning to Reveal Cu TSV
• Device wafer on carrier
• Grinding process used to get within 10-20µm of Cu TSV
• Wet etch process to reveal Cu TSV
– Use of KOH to etch Silicon without attack of Cu via or Oxide liner
Silicon thickness adhesive carrier
Via depth adhesive carrier
Etch target
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Integrated Thickness Measurement
• Need to know
– Silicon thickness post grind
– Uniformity of Silicon
– Via depth
Silicon thickness
• Use of integrated measurement provides
– Silicon thickness and radial thickness variation
– Etch rate feedback from previous wafer
• Determine amount of Silicon to etch
– Average silicon thickness to be removed
– Radial profile of etch
– Assume 2µm reveal height
Example
 Table shows large variation in amount of
Silicon to be etched depending upon post grind thickness and via depth adhesive carrier
Via depth

Single wafer spin etching
Post Grind
Post Silicon Etch
• Post Grind non-uniformities can have radial dependence
– Center to edge variations
• Single wafer etch process can compensate for radial non-uniformities
– More/Less etch in center of wafer
• Resulting Silicon wafer thickness is more uniform
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Wafer Thinning to Cu TSV
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KOH etching of Silicon requires Post Clean
Post Etch Post Clean
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Wet Etch TSV Reveal – post clean
VPD-ICPMS measurements indicate the cleaning process is effective at removing the residual Potassium from the etch process.

TSV revealed post etch and clean
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TSV revealed post etch and clean
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FIB section – after TSV reveal
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Wafer Thinning to Cu TSV
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Wafer Thinning to Cu TSV
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Surface Roughness after Grind
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Surface Roughness post KOH etch
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Wafer Thinning to Cu TSV
EDX analysis shows the oxide liner and Cu via remain intact
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Integrated Wafer Thickness Measurement:
Process Control
• Create map before etch
• Create map after etch
• Compute etch rate
• Compute etch uniformity
• Spike chemistry
• Determine etch time
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Integrated Wafer Thickness Measurement

Integrated Wafer Thickness Measurement
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Wafer Thickness Measurements
SSEC Integrated Sensor Graphics ISIS SemDex Graphics
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Integrated Wafer Thickness Measurement
- mapping options
Ring map Surface map
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Cost comparison
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TSV wafer post wet etch reveal
Illustration of wafer with revealed TSVs after wet etch and clean processes
Optical
SEM

Summary
• Process demonstrated to etch silicon and safely reveal Cu TSV
• Clean silicon surface and isolated Cu TSVs
• Integrated Wafer Thickness Measurement for process control
• Low cost of ownership
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