Live at Power-Up
PLD Effects on System Design
August 2005
Table of Contents
System Design Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Circuits and Applications Requiring Short Initialization Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Live at Power-Up Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Programmable Logic Device Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power-Up Device Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
System Functionality Difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Level 0 LAPU Contributes to Cost Savings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
List of Figures
Live at Power-Up Devices Active During System Voltage Power Ramp-Up and Before Power-Up . . . 4
Programmable Logic Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Power-Up Device Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power-Up Behavior of SRAM FPGA and NVM (Antifuse) FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-Up Behavior of Hybrid SRAM FPGA and NVM (Flash) FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-Up to Operation Time – NVM vs. SRAM FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-Up to Operation Time - NVM vs. Hybrid SRAM FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
System Implementation Using Level 2 SRAM FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
System Implementation Using Level 0 Nonvolatile FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
List of Tables
Programmable Logic Device Power-Up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
The LAPU Cost Difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2
Live at Power-Up
System Design Trends
As systems become more complex, pressure to reduce cost and shorter design cycles are the drivers for
higher efficiency, modularity, and simplicity of systems. When a certain feature is required in the
application, designers usually scan the market for possible solutions that could meet system requirements.
Once they narrow down the selection to those solutions that satisfy the design needs, they choose
between the alternatives on the basis of cost and design simplicity.
Circuits and Applications Requiring Short Initialization Time
Once power is applied to a typical system, system components must be initialized and system supervisory
tasks are performed, such as setting up the microprocessor environment, performing critical system
startup tasks, and controlling operation during power ramp-up until system voltages are stable. In a
complex system, system supervisory tasks may include configuring memory blocks; system initialization
tasks might include decoding of the microcontroller address bus, synthesizing and distributing various
clocks to multiple system components, distributing resets or enable signals, managing bus activity
transmissions to avoid data glitches, and performing time critical tasks to minimize processor initialization
time.
Some applications require fast system initialization time to allow immediate operation. Examples include
medical and industrial applications that perform critical operations, such as life assistance equipment.
Battery-operated portable applications with frequent power-up and power-down cycles require short
initialization time to increase product usability for the user. Other critical operation applications that require
instant operation after power-up are automotive engine startup control and military applications such as
missile startup control.
Live at Power-Up Devices
A system is composed of multiple components with inter-dependencies, and the designer's task is to make
sure these components all work together. It is vital to choose live at power-up devices for the system’s
critical path in order to achieve efficient system operation. As illustrated in Figure 1 on page 4, live at
power-up devices are operational before the system voltage has reached its minimum level, which is
defined as the power-up stage, as opposed to devices that are operational only after power-up. For
example, choosing a live at power-up device that has an integrated phased-locked loop (PLL) for clock
distribution tasks, not only reduces overall system startup time, but also eliminates the need for a
standalone PLL to perform this function.
Selecting live at power-up devices for the critical system startup path minimizes overall application startup
time, cost, size, and reduces design complexity.
Live at Power-Up
3
Power On
Power Up
Voltage
System
Voltage
Time
LAPU
Non-LAPU
Figure 1: Live at Power-Up Devices Active During System Voltage Power Ramp-Up and Before Power-Up
Programmable Logic Device Alternatives
Programmable Logic Devices (PLDs) have experienced dramatic growth contributed by their benefits of
short time-to-market, in-system programming (ISP) capability, ease of use, and rapid prototyping. The
transition to advanced technologies has resulted in a dramatic cost reduction for PLDs, which are
increasingly replacing live at power-up Application Specific Integrated Circuits (ASICs) in system designs.
When a PLD is required in the system, designers should not ignore the live at power-up attribute of the
chosen PLD. This decision could unnecessarily increase the size and cost of the system.
PLDs require configuration memory to initialize the device for operation. There are differing technologies
for configuring PLD solutions available in the market. PLDs based on nonvolatile memory technologies,
such as Flash, EEPROM, and antifuse, store their configuration on chip. This eliminates the need to
download the configuration, making these devices readily available for operation in a similar way to
Application Specific Standard Products (ASSPs) and ASICs.
Other technologies, such as the volatile SRAM-based programmable logic devices, wake up in an
unknown state and require configuration from an external, nonvolatile memory device on each power-up
cycle. In addition, there are Hybrid SRAM devices that have an SRAM FPGA architecture and a
nonvolatile configuration memory on-chip. These Hybrid FPGAs must be loaded internally on each powerup cycle. Only after the device is loaded with the configuration, can it start operating according to the
customer application. After each power-down or power supply "brownout," the Hybrid device loses its
configuration and needs to be loaded again in the next power-up cycle. Figure 2 on page 5 describes the
PLD technology alternatives, which include SRAM, EEPROM, Flash and antifuse, with respect to their
external or internal configuration component.
Live at power-up PLDs simplify the design effort required, and can help initialize and set up the system
environment and prepare for microcontroller and other system operations, hence shortening system
initialization time. Setup activities such as configuring system memories, providing a consistent and
reliable power-up sequence for components on the system board, distributing clocks to devices, and
managing interfaces and bus activity, help make the design more efficient, reduce component count, and
reduce power consumption.
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Live at Power-Up
EEPROM
SPLD/CPLD
EEPROM
Nonvolatile SPLD/CPLD – EEPROM
NVM
FPGA
Flash/Antifuse
Nonvolatile Memory (NVM) FPGAs
PROM
SRAM
FPGA
or
NVM
MCU
SRAM
Volatile SRAM FPGAs with external
configuration memory
(Boot PROM or Flash MCU)
NVM
SRAM
FPGA/CPLD
SRAM
Hybrid FPGAs/CPLDs – Volatile SRAM FPGA
fabric loaded from on-chip NVM
Blue
– EEPROM (Nonvolatile Memory)
Green – Flash/Antifuse (Nonvolatile Memory)
Purple – SRAM (Volatile Memory)
Figure 2: Programmable Logic Technologies
Power-Up Device Classification
Actel is using a device classification system that helps designers identify the power-up behavior of
semiconductor devices in a system. This classification system helps designers choose the appropriate
programmable logic components for their applications, taking into account operation and functionality
during power-up stages of the system.
Figure 3 on page 6 shows a typical system power-up operation from the moment a voltage is applied
(power-on), to the point where the voltage reaches the lower operational limit of the system voltage, and
finally the system is initialized. For the purpose of simplification, the classification uses a single system
voltage to reflect system operation. After power-on, which is the first time power is applied to the system,
the voltage starts to ramp-up. System components that have a low voltage trigger point can start operating
and help in system initialization, power management, critical system tasks, providing clocks, and reset
signals. Devices that are operational between power-on and power-up (the time at which the applied
voltage has reached the lower limit of system voltage and is stable) are considered as supporting Level 0
live at power-up (LAPU). Devices that meet Level 0 LAPU are nonvolatile memory (NVM) PLDs, ASICs,
Live at Power-Up
5
and some ASSPs. Devices that require a configuration download or require a higher minimum system
voltage level to operate are classified as Level 1 LAPU as they are operational only after power-up. These
are usually ASSPs or other devices that help in configuring the memories or interfaces to the main
processors. Once the system environment is initialized and clocks, resets, interfaces, and memories are
ready, the processor (MCU/CPU) can start to function and access the peripherals it requires. These
devices support Level 2 as they are operational after the system is initialized, i.e., the system components
are functional and processors can start operating.
Figure 3: Power-Up Device Classification
6
Live at Power-Up
Table 1 shows laboratory tests and datasheet analysis done for several PLDs to determine actual powerup timing. The data presented supports the LAPU classification differentiation for each technology. Note
Flash and antifuse nonvolatile FPGAs are the only FPGAs that are classified as Level 0 LAPU as well as
the SPLDs, which have EEPROM technology.
Figure 4 on page 8 shows NVM (antifuse) FPGA AX250 (Actel’s Axcelerator®) I/Os operating prior to
system power-on. The SRAM FPGA XC3S200 (Xilinx Spartan-3) takes more than 200 ms for the part to
load its configuration and begin I/O operation.
NVM FPGAs are classified as Level 0 LAPU, which is typically 4,000 times faster than the SRAM FPGA,
which are classified as Level-2 LAPU.
Table 1: Programmable Logic Device Power-Up Timing1
Family
Power-Up Time
(est./test)
Live at Power-Up (LAPU)
Classification
Actel FPGA
Flash ProASIC3
50 µs
0
Actel FPGA
Antifuse
60 µs
0
SPLD (EEPROM)
22V10
70 µs 2
0
CPLD (EEPROM)
MAX7000
70 µs 2
0
Hybrid CPLD
MAX® II
CoolRunner® II
200 µs
1
Lattice FPGA
LatticeXP
>1 ms 3
1
Xilinx® FPGA
Spartan® II/IIE and Spartan3
XC3S200
>200 ms
2
Altera® FPGA
Cyclone™, Cyclone II
>200 ms 4
2
Notes:
1. FPGA/PLD core voltage ramp-up 100 µs
2. Estimated time
3. Based on the company statement
4. Best case conditions taken from the datasheet
Live at Power-Up
7
SRAM FPGA Power-Up Behavior
Operational hundreds of milliseconds after power-up. Meets Level 2 classification.
Nonvolatile Antifuse FPGA Power-Up Behavior
Operational before power-up. Meets Level 0 classification.
Figure 4: Power-Up Behavior of SRAM FPGA and NVM (Antifuse) FPGA
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Live at Power-Up
Figure 5 shows the NVM (Flash) FPGA A3PE600 (Actel's ProASIC3/E) I/Os operating prior to system
power-up. The Hybrid SRAM FPGA EPM1270 (Altera's MAX-II) takes more than 200 µs to load its
configuration and start functioning.
Hybrid (SRAM plus NVM) FPGAs must be configured after every power-up cycle and meet Level 1 live
after power-up. Flash FPGAs meet Level 0 live at power-up regardless of the ramp-up time and are
typically 20 to 40 times faster.
Hybrid (SRAM plus NVM) FPGA Power-Up Behavior
Active hundreds of nanoseconds after power-up. Meets Level 1 classification.
Nonvolatile Flash FPGA Power-Up Behavior
Operational before power-up. Meets Level 0 classification.
Figure 5: Power-Up Behavior of Hybrid SRAM FPGA and NVM (Flash) FPGA
Live at Power-Up
9
Figure 6 shows a comparison of time to operation between NVM FPGAs and SRAM FPGA for different
ramp-up times, which clearly indicates the superiority of NVM FPGAs, for all ramp-up rates.
Time I/Os Become Active
Ramp-Up Time
0.1
1
10
100
0
50
100
150
200
250
300
Time (ms)
ProASIC3/E
Axcelerator
Spartan3
Note: Actel's devices were always operational BEFORE power-up.
Figure 6: Power-Up to Operation Time – NVM vs. SRAM FPGAs
10
Live at Power-Up
Figure 7 shows a comparison of power-up operation time to ramp-up time ratio for different ramp-up times
between NVM FPGAs and SRAM Hybrid FPGAs. The ratio used in this diagram clearly indicates a faster
operation time for all NVM FPGAs ramp-up rates.
Time to Power-Up as a Percentage of Ramp-Up Time
Power-Up Time/Ramp-Up Time (%)
250%
200%
150%
ProASIC3/E
MAX-II
100%
50%
0%
0.1
1
Ramp-Up Time (ms)
10
Figure 7: Power-Up to Operation Time – NVM vs. Hybrid SRAM FPGAs
The nonvolatile FPGAs tested are always operational prior to power-up and the time from power-on to
operation is not dependent on device logic size. On the other hand, SRAM and Hybrid devices have a
longer power-on to operation time because the device configuration size is dependent on the logic density
of the device. Therefore, the differences between NVM and SRAM is even more significant with large
density devices.
Based on the LAPU classification defined and the devices tested, power-up time for Level 0 LAPU NVM
FPGAs is 4,000 times faster than that of SRAM FPGAs, and 20 to 40 times faster than that of Hybrid
FPGAs.
Live at Power-Up
11
System Functionality Difference
System architecture is impacted by the PLD's LAPU level supported, as can be seen in Figure 8 and
Figure 9 on page 13. Figure 8 illustrates a system implementation with SRAM FPGA that is loaded from
external flash, and describes the system's power-up sequence step by step.
The system is operational after hundreds of milliseconds, as it takes time for the SRAM device to load its
configuration and start operating.
Power-Up Sequence
Time
1.
Power-On (applied)
0 ns
2.
Regulate power, clock
3.
Apply reset and provide
clocks to devices
4.
SPLD address memory
for MCU
5.
Power-up (stable)
6.
Components initialized
7.
MCU wakes up and starts
initializing
8.
MCU operational
9.
FPGA configuration
loaded from MCU
10.
FPGA operational
Reset
Controller
(CPLD)
ASSP
Clock
Generation
PLL/Dividers
MCU
100 µs
Config.
Xtal
Osc.
SRAM
FPGA
Address/Data
Address/Data
Address/data
Decode SPLD
Address/Data
Address/Data
Flash
Memory
>200 ms
Figure 8: System Implementation Using Level 2 SRAM FPGA
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Live at Power-Up
Figure 9 illustrates system implementation with NVM FPGAs and the system's power-up sequence.
The system is operational after 50 µs instead of hundreds of milliseconds, as there is no need to configure
the nonvolatile FPGA upon power-up.
Power-Up Sequence
Time
1.
Power-On (applied)
0 ns
2.
Regulate power, clock
3.
Actel FPGA is live, I/Os
active FPGA applies
reset and provides
clocks to devices
4.
FPGA initializes
memory
5.
Power-Up (stable)
6.
Components initialized
7.
MCU wakes up and
starts initializing
8.
MCU is operational
50 µs
Clock
Reset
MCU
ASSP
Actel
FPGA
Clock
Source
Memory
100 µs
Live at power-up
(Level 0)
Live after power-up
(Level 1)
Live after system
initialized (Level 2)
Figure 9: System Implementation Using Level 0 Nonvolatile FPGA
Level 0 LAPU Contributes to Cost Savings
In addition to the system simplification benefits, the LAPU function also contributes to reducing the number
of components used on board, decreasing power consumption, reducing total system cost, and increasing
reliability.
For SRAM-based FPGAs, significant additional circuitry may be needed. In addition to a boot PROM and/
or additional system memory for unsecure configuration code, a live at power-up CPLD may be needed for
system configuration and supervisory tasks. Clock and reset signal generation is also required upon
power-up to help initialize components on board. These issues add complexity and cost to the system
design and slow down the development process.
Nonvolatile FPGAs help to simplify board and system design, and reduce cost, as illustrated in Table 2 on
page 14.
Live at Power-Up
13
Table 2: The LAPU Cost Difference
Comparing Value FPGA Total System Cost (High Volume Design)
SRAM
ProASIC3
$2.25 to $3.00
$2.75
SPI Serial Flash
(e.g. Atmel AT45DB DataFlash)
$0.60
$0.00
Startup Clock Management
Clock Generator (MPC9229FA-ND)
$1.25
$0.00
Live at Power-Up CPLD
(CY37032P44-125AC) System supervisory, Enable signals, etc.
$0.75
$0.00
$4.85 to $5.60
$2.75
FPGA Unit Cost – 125KSG
3x Unit Cost – LAPU SRAM Penalty
The average system cost using Level 2 LAPU SRAM FPGA could be as much as three times the system
cost of using Level 0 LAPU nonvolatile FPGA.
Conclusion
Level 0 live at power-up FPGAs address design requirements by serving applications that require short
initialization time and instant availability of product features to the end user. Level-0 LAPU FPGAs make
the system available to the microprocessor at power-up. Nonvolatile FPGAs can perform microprocessor
address decoding, and the FPGA's PLLs are immediately available. This leads to the elimination of
external CPLDs, additional oscillator and reset handling circuitry, and results in an efficient and simplified
system design.
Level 0 LAPU FPGAs also reduces the total cost of ownership through the reduction of components, which
results in reduced inventory and increased end-product reliability, as parts not included on the printed
circuit board (PCB) cannot fail.
Actel is the only FPGA provider that supports Level-0 LAPU class for its FPGAs using nonvolatile
technologies. Actel Level 0 LAPU FPGAs are orders of magnitude faster to power-on than their nearest
competitors.
Level 0 LAPU is an enabling technology for control during power-up, which helps in simplifying design,
reducing cost, and contributing to efficient use of resources.
14
Live at Power-Up
For more information, visit our website at www.actel.com
www.actel.com
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