ASYMMETRICAL CASCADED MULTILEVEL INVERTER
USING SINGLE DC POWER SOURCE
Prof. Tejas G Mistry1, Prof. Shaikh Mo.Suhel A2, Prof. Himanshu N Chaudhari3
Assistant Professor, Electrical Engineering Department ,S.N.P.I.T & RC, Umrakh1
Assistant Professor, Electrical Engineering Department ,S.N.P.I.T & RC, Umrakh2
Assistant Professor, Electrical Engineering Department ,S.N.P.I.T & RC, Umrakh3
Abstract: Multilevel Inverters can produce a high-power, high-voltage inverter with
multilevel structure the way in which device voltage stresses are controlled. A symmetrical
standard cascaded multilevel inverter requires ‘n’ DC sources for ‘2n+1’ levels which
needs isolated DC sources for power conversions. This paper aim is to increase the number
of level with reduce the no of dc source. The scheme proposed here is to use Asymmetrical
Multilevel Inverter with isolated DC power supply. Analysis is extended to the use of the
single DC power source with the remaining ‘n-1’ DC source being capacitor and
simultaneously maintains the DC voltage level of the capacitor and to choose a
fundamental frequency switching pattern to produce a nearly sinusoidal output.
Simulation using Matlab simulink is done to verify the performance of Asymmetrical
Multilevel Inverter using isolated Dc source. Simulation and hardware results are shown
and discussed in this paper.
Keywords: Asymmetrical Multilevel Inverter, MATLAB, Optimization Angle Control,
Symmetrical Multilevel Inverter, THD.
INTRODUCTION
A multilevel inverter is a more powerful inverter that it does the same thing as an
inverter except provides energy in higher-power situations. Multilevel inverters are a
source of high power, often used in industrial applications and can use either sine or
modified sine waves. Instead of using one converter to convert an AC current into a DC
current, a multilevel inverter uses a series of semiconductor power converters (usually
two to three) thus generating higher voltage. While with an inverter can transfer energy
with the flip of one switch, with a multilevel inverter flip several switches, each switch
requiring a circuit. These multiple switches and circuits usually make multilevel
inverters more expensive than inverters.
Multilevel inverters include an array of power semi-conductors and dc voltage
sources, the output of which generate voltages with stepped waveforms [1]. In
comparison with a two-level voltage-source inverter (VSI), the multilevel VSI enables to
synthesize output voltages with reduced harmonic distortion and lower electromagnetic
interference[2]. By increasing the number of levels in the multilevel inverters, the
I.
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output voltages have more steps in generating a staircase waveform, which has a
reduced harmonic distortion. However, a larger number of levels increase the number
of devices that must be controlled and the control complexity [3].
The multilevel inverter produces common mode voltage, reducing the stress on the
motor and preventing the motor from damage. Multilevel inverters can draw input
current with low distortion .The multilevel inverter can operate at both fundamental
switching frequencies and higher switching frequency. It should be noted that the lower
switching frequency means lower switching loss and higher efficiency is achieved.
Selective harmonic elimination technique along with the multi-level topology results the
total harmonic distortion becomes low in the output waveform without using any filter
circuit.
Nowadays there exist three well-known types commercial topologies of multilevel
voltage source inverters [4].They are the neutral point clamped (NPC) multilevel
inverter, the flying capacitor (FC) multilevel inverter and the cascaded H-bridge (CHB)
multilevel inverter. Series-connected H-bridge cells with an isolated dc voltage sources
connected to each cell are used in the CHB multilevel inverter. The cascaded multilevel
control method is very easy when compare to other multilevel inverter because it
doesn’t require any clamping diodes and bulky capacitors. The CHB multilevel
inverters can be divided into two group according to the dc voltage sources,
symmetrical and asymmetrical topology. In the symmetrical topology, the values of all
of the dc voltage sources are equal. This characteristic gives the topology good
modularity. However, the number of the switching devices rapidly increases by
increasing the number of output voltage level. In order to increase the number of output
voltage level with reduced no of switches asymmetrical type multi level is used.
According to Binary and Ternary ratio of dc voltage sources are selected [8].
ASYMMETRICAL CASCADED MULTI LEVEL INVERTER
A cascade multilevel inverter is a power electronic device built to synthesize a desired
AC voltage from several levels of DC voltages. In symmetrical multi level inverter with
using „n‟ no. of sources we can obtain (2N+1) level. As we are increasing the no. of steps
THD decreases and it increases the requirement of dc source.
With using Asymmetrical Cascaded Multi Level Inverter we can eliminates the
excessively large number of bulky transformers required by conventional multi level
inverters. It can also possible to eliminate the clamping diodes and the bulky capacitors
required by the diode clamp and flying capacitor multilevel inverters. No. of 1 phase Hbridge inverters are used and connected in series. This method introduces the idea of using
separate produce an AC voltage waveform which is nearly sinusoidal. Separate DC source is
provided or connected with each H bridge inverter. By cascading the output voltage of each
H-bridge inverter, a staircase type output voltage waveform is produced. The no of output
voltage levels obtained are depends upon the no. of H bridges used in ACMLI. The output
voltage obtained is equivalent to summation of the output voltage of bridges as shown in
equation (1).
If ACMLI has N no. Of H-Bridges, than output voltage is:
Vo (t) = Vo1 (t) + Vo2 (t) + ..... + Vo N (t)
(1)
Where, Vo1 (t) ,Vo2 (t) , ..... Vo N (t) is the output of individual H-bridge.
II.
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In ACMLI DC voltage with geometric propagation (GP) ratio binary and ternary are
used. In binary GP ratio with H- Bridge inverters, the DC voltages having ratio 1: 2: 4: 8. . :
2N.Using binary GP ratio the maximum output voltage would be (2N -1) V dc and the
voltage levels will be (2N+1-1). While in the ternary progression the amplitude of DC
voltages having ratio 1: 3: 9: 27. . : 3N and the maximum output voltage reaches to
((3 - 1)/2) V dc and the voltage levels will be (3N).
III. . PROPOSED SCHEME
Fig. 1 shows the basic connection diagram of 1 phase of 15 level inverter. To operate a
cascade multilevel inverter using a single DC source, it is possible to use capacitor as the DC
source for all auxiliary bridges in place of isolated voltage source. In this research work a
scheme is proposed that allows the use of a single DC power source (e.g., battery or fuel cell
stack) with the remaining „n−1‟ DC sources being capacitors. It is shown that one can
simultaneously maintain the DC voltage level of the capacitors and choose a fundamental
frequency switching pattern to produce a nearly sinusoidal output.
To operate a cascade multilevel inverter using a single DC source, it is proposed to use
capacitors as the DC sources in conjunction with single DC source. The DC source for the
first H-bridge (H1) is a DC power source with an output voltage of Vdc. The DC source for
the second H-bridge (H2) has a capacitor voltage to be held at Vdc/2 and the DC source for the
third H-bridge (H3) is a second capacitor voltage held at Vdc/4. The output voltage of the first
H-bridge is denoted by V1, the output of the second H-bridge is denoted by V2 and for the
third H-bridge is denoted by V3 so that the output of this DC source cascade multilevel
inverter is V(t)=V1(t)+V2(t)+V3(t).
S0
S1
Vdc
S3
S2
S4
S5
Vdc/2
L
O
S7
S6
S8
S9
S11
S10
A
D
Vdc/4
Fig 1.Hardware of 15-level inverter
Fig 2. Output voltage waveform for a
15-level inverter
By opening and closing the switches of H1 appropriately, the output voltage V1can be
made equal to -Vdc, 0, or Vdc while the output voltage of H2 can be made equal to -Vdc/2,0,
or Vdc/2 and the output voltage of H3 can be made equal to -Vdc/4,0, or Vdc/4 by opening
and closing its switches appropriately and hence the output voltage of the inverter can have
the values −7Vdc/4, −3Vdc/2, −5Vdc/4, −Vdc,−3Vdc/4,−Vdc/2,−Vdc/4 0, 7Vdc/4 , 3Vdc/2,
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5Vdc/4, Vdc,3Vdc/4,Vdc/2,Vdc/4 which is seven level and is illustrated in Fig.2(a).The
possible ways in which the voltage waveform of Fig. 2 can be achieved are given in Table 1.
Θ
V1
V2
V3
V1+ V2 + V3
0 ≤ θ ≤ θ1
0
0
0
0
θ1 ≤ θ ≤ θ2
0
0
Vdc/4
Vdc/4
θ1 ≤ θ ≤ θ2
0
Vdc/2
−Vdc/4
Vdc/4
θ1 ≤ θ ≤ θ2
Vdc
−Vdc/2
−Vdc/4
Vdc/4
θ2 ≤ θ ≤ θ3
0
Vdc/2
0
Vdc/2
θ2 ≤ θ ≤ θ3
Vdc
−Vdc/2
0
Vdc/2
θ3 ≤ θ ≤ θ4
0
Vdc/2
Vdc/4
3Vdc/4
θ3 ≤ θ ≤ θ4
Vdc
0
−Vdc/4
3Vdc/4
θ3 ≤ θ ≤ θ4
Vdc
−Vdc/2
Vdc/4
3Vdc/4
θ4 ≤ θ ≤ θ5
Vdc
0
0
Vdc
θ5 ≤ θ ≤ θ6
Vdc
0
Vdc/4
5Vdc/4
θ5 ≤ θ ≤ θ6
Vdc
Vdc/2
−Vdc/4
5Vdc/4
θ6 ≤ θ ≤ θ7
Vdc
Vdc/2
0
6Vdc/4
θ7 ≤ θ ≤ π/2
Vdc
Vdc/2
Vdc/4
7Vdc/4
Table .1
By choosing the nominal value of the capacitor voltage to be one half that of the DC
power source, the nominal values of the levels are equally spaced. The criteria required for
this capacitor regulating scheme is that (1) the desired capacitor voltage is less than the DC
power source voltage,(2) the capacitance value is chosen large enough so that the variation of
its voltage around its nominal value is small, and (3) the capacitor charging cycle is greater
than the capacitor discharge cycle.
SIMULATION AND THEIR RESULTS
Simulation for 15-level multilevel inverter shown in figure 3. The DC source for the
first H-bridge (H1) is a DC power source with an input voltage of 18v. For the second Hbridge(H2) a DC power source with an input voltage of 9v, for the third H-bridge (H3) has a
DC power source with an input voltage of 4.5v.
For 15-level inverter here 12 MOSFET switches are used and load is connected
between H1 and H3 bridge as shown in figure. Voltmeter V1 and V2 are measured voltage
across the capacitor C1 and capacitor C2 respectively, which give voltage 9v and 4.5v
respectively. A voltmeter V3 measured voltage across the load. Note that the fifth level is
constant at 25v because this level is due to only the power supply source with capacitor
voltage not being used. However, the first, second, third, fourth, six, seven level require using
the capacitor voltage and note that they are not constant. Fig 4 shows the output voltage
waveform of 15 level inverter using single dc source.
IV.
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Fig 3. Circuit diagram for 15-level inverter
15-level inverter (Using single DC source)
V.
Fig 4. Waveform for
V. HARDWARE AND RESULTS
Fig 5. Block diagram of cascade H-bridge Multilevel Inverter
Basic block diagram for cascaded H-bridge Multilevel Inverter shown in fig 5. It
consists of control circuit which is used to generate gate pulses for switches. In that control
circuit 89V51RD2 microcontroller is used which is low cost and efficient controller. In power
circuit MOSFETs (IRF840) are used as switching device. Power circuit and control circuit
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must be isolated from each other. To provide isolation 6n137 opto-coulper are used. The 05V square wave is fed to the inputs of the driver circuit. The proper selection of a MOSFET
driver depends on whether the device uses a positive or negative supply. International
rectifier recommends their independent high and low side drivers IR2110 with floating
channel and designed for bootstrap operation. Each gate driver circuit operates two MOSFET
of opposite leg of power inverter. The main application of the gate driver is that it converts
the square wave signal produced from microcontroller to a level where the MOSFET s can
operate with it. Here we are using IR2110 MOSFET driver which have Voffset=500V max and
Vout =10-20 V and output current 2A.The single phase inverter has an input of maximum
325V DC and consists of 4 MOSFETs. Each MOSFET will be exposed to a maximum
voltage of 325 V and current of 1A.However,for safety purpose, the MOSFETs were chosen
to a handle minimum breakdown voltage of 500 V DC and maximum current of 8A so we
IRF840 MOSFET are used here.
Fig 6. Hadware Implementation
Fig 7. Output waveform of 15-level
using a single DC source
Hardware setup for 15 Level Multilevel inverter with a single Dc source is shown in figure
6. A 3 phase cascaded multilevel inverter using MOSFET IRF840 as the switching devices to
carry out the experiment. A power supply was used as the DC power source with Vdc = 18v
and 4700 microfarad (25v) capacitor was used as the second and third Dc source. The main
components for this inverter are: Single phase uncontrolled rectifier, filter capacitor, Single
phase inverter, control card for inverter(Gate driver and opto-coupler) and power supply of
5v and 15v. For this inverter one single Dc source of 18v is connected with one bridge and
for other two bridge the voltage source are capacitors, one of the capacitor among them is
charged up to 9v whereas another charged up to 4.5V. For three bridges gating signals to the
MOSFET‟s are given by the use of microcontroller(89V51RD2). A resistive load is
connected between first and last terminals of series connected bridges. The output measure
across the resistive load which is shown in the CRO in Fig. 7. Voltage spikes are seen in
waveform. These spikes occur at the instant when both of the sources (power supply and
capacitor) are being switched in or out simultaneously. This is due to the difference in dead
time of the H-bridge switches as well as the timing of turning the switching on and off not
being exactly the same between the three H-bridge.
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THD Analysis Result:
Number of level
15 level (With single DC source)
15 level (With multi DC source)
%THD
15.26
14.48
VI. CONCLUSION
The whole research work presented in this paper is concentrated on multi level inverter
with only single DC supply. And it has been conclude that by increasing no. of levels for the
output voltage, the THD can be reduced. No. of levels can be increased by increasing the no.
of bridges of MLI. In this paper H-bridge Multilevel Inverter have been simulated and
implemented on hardware.
The H-bridge Multilevel Inverter with single DC source has some advantages over the
conventional H-bridge Multilevel Inverter is that with single DC source is used hence it
reduces the overall size as the required no. of DC sources. Also as the sources are reduced
and so does the cost also reduces and the complication is also reduced to some extent.
REFERENCE
[01] J. Rodriguez, J. S. Lai, and F. Z.Peng, “Multilevel inverters: A survey of topologies,
controls, and applications,” IEEE Trans. Ind. Electron.,vol. 49, no. 4, pp. 724–738, Aug.
2002.
[02] J. H. Kim, S. K. Sul, and P. N. Enjeti, “A carrier-based PWM method with optimal
switching sequence for a multilevel four-leg voltage-source inverter,” IEEE Trans. Ind.
Appl., vol. 44, no. 4, pp. 1239–1248, Jul./Aug.2008.
[03] A. Boora, A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, “Voltagesharing converter to
supply single-phase asymmetrical four-level diode clamped inverter with high power
factor loads,” IEEE Trans. Power Electron., vol. 25, no. 10, pp. 2507–2520, Oct. 2010.
[04] J. Rodriguez, S. Bernet, P. Steimer, and I. Lizama, “A survey on neutral point clamped
inverters,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2219–2230, Jul. 2010.
[05] M. Manjrekar and T. A. Lipo, “A hybrid multilevel inverter topology for drive
application,” in Proc. Appl. Power Electron. Conf., 1998, vol. 2, pp. 523–529.
[06] Zhong Du,Leon M. Tolbert,Johan N.Chiasson, and Bura Ozpineci ,“A Cascade
Multilevel Inveter Using a Single DC Source”0-7803-9547-6/06/$20.00©2006 IEEE
[07] Nabae, I. Takahashi, and H. Akagi, „A new neutral point clamped PWM inverter‟, IEEE
Trans., 1981, 1A-17, (5), pp.518-523V
[08] J.Rodríguez, J.S.Lai, and F. Z.Peng,”Multilevel Inverters: A Survey ofT opologies,
Controls, and Applications”, IEEETransactions on Industrial Electronics, Vol. 49,No. 4,
August 2002,pp.724-739
[09] D.Mohan and Sreejith B.Kurub “Performance Analysis of Multi Level Shunt Active
Filter based on SDM” in CiiT International Journal of Digital Signal Processing pp 42 –
46
[10] Damoun Ahmadi, KeZou, Cong Li, Yi Huang and Jin Wang, “A Universal Selective
Harmonic Elimination Method for High-Power Inverters”,IEEE Transactions on power
electronics, vol. 26, no. 10,pp2743-2752,2011.
VII.
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