CHAPTER 7
COMPLEMENTARY MOS (CMOS) LOGIC DESIGN
Chapter Outline
CMOS Inverter Technology
Static Characteristics of the CMOS Inverter
Dynamic Behavior of the CMOS Inverter
Power Dissipation and Power Delay Product
in CMOS
7.5 CMOS NOR and NAND Gates
7.6 Design of Complex Gates in CMOS
7.7 Minimum Size Gate Design and Performance
7.8 Dynamic Domino CMOS Logic
7.9 Cascade Buffers
7.10 The CMOS Transmission Gate
7.11 CMOS Latchup
Summary
Key Terms
References
Problems
7.1
7.2
7.3
7.4
Motorola’s PowerPCTM 620 32/64-bit RISC
microprocessor.
Courtesy of International Business Machines
Corporation. Unauthorized use not permitted.
Chapter Goals
From Chapter 7, we shall gain a basic understanding of the
design of CMOS logic and memory circuits.
• Introduce CMOS Logic Gates
• Explore the voltage transfer characteristics
of CMOS inverters
• Learn to design CMOS inverter, NOR, and NAND gates
• Learn to design complex CMOS logic gates
• Explore sources of static and dynamic power
dissipation in CMOS logic
• Develop expressions for the rise time, fall time,
propagation delay, and power-delay product
of CMOS logic
• Develop expressions for CMOS noise margins
• Introduce the concept of dynamic logic and domino
CMOS logic techniques
• Learn to design “cascade buffers’’ for driving high-load
capacitances
• Explore layout of CMOS inverters and logic gates
• Understand the problem of “latchup’’ in CMOS
technology
462
Complementary MOS, or CMOS, technology is by far
the dominant integrated circuit technology. CMOS logic
was first described by Wanlass and Sah in 1963 [1], but
for many years, CMOS technology was available primarily
in unit-logic form, with several gates packaged together
in a single dual in-line package (DIP). CMOS circuitry
requires both NMOS and PMOS transistors to be built
into the same substrate, and this increase in process complexity leads to higher-cost circuits. In addition, standard
CMOS gates require more transistors than the corresponding NMOS or PMOS logic gates, and thereby require more
silicon area to implement. Larger silicon area contributes
further to increased cost.
The increased cost that results from CMOS fabrication and circuit complexities represented the primary reason why CMOS technology was not widely used in complex
integrated circuits. CMOS was utilized primarily in applications that required extremely low power and where the
increased cost could be justified.
7.1
CMOS Inverter Technology
463
However, as mentioned in Chapter 6, power levels associated with NMOS microprocessors
reached crisis levels by the mid 1980s, with power dissipations as high as 50 W per chip or
more. To solve the static power dissipation problem, the microprocessor industry rapidly moved
to CMOS technology. Today, CMOS is the industrywide standard technology, and this important
circuit innovation was recognized by the award of the 1991 IEEE Solid-State Circuits Society
Field Award to Frank Wanlass for his invention of CMOS logic.
I
n Chapter 7, we investigate the design of CMOS logic circuits, starting with characterization of
the CMOS inverter, and followed by a discussion of the design of NOR, NAND, and complex gates
based on a CMOS reference inverter. CMOS gate design is demonstrated to be determined primarily by logic delay considerations. CMOS noise margins and power-delay product are discussed,
and the transmission gate is also introduced.
The physical structure of CMOS technology is presented, and parasitic bipolar transistors
are shown to exist within the integrated CMOS structure. If these bipolar devices become active,
a potentially destructive phenomenon called latchup can occur.
7.1 CMOS INVERTER TECHNOLOGY
As noted, CMOS requires a fabrication technology that can produce both NMOS and PMOS
transistors together on one IC substrate. The basic IC structure used to accomplish this task is
shown in Fig. 7.1. In this cross section, NMOS transistors are shown fabricated in a normal manner
in a p-type silicon substrate. A lightly doped n-type region, called the n-well, is formed in the
p-type substrate, and PMOS transistors are then fabricated in the n-well region, which becomes
the body of the PMOS device. Note that a large-area diode exists between the n-well and p-type
substrate. This pn diode must always be kept reverse-biased by the proper connection of VD D
and VSS (for example, 5 V and 0 V).
vI
VSS (0 V)
B
p+
VDD (5 V)
D
S
n+
n+
vO
D
B
S
p+
p+
n+
n-well
Ohmic
contact
NMOS transistor
PMOS transistor
Ohmic
contact
p-type substrate
Figure 7.1 n-well CMOS structure for forming both NMOS and PMOS transistors in a single silicon
substrate.
The connections between the transistors needed to form a CMOS inverter are shown in Fig. 7.1
and correspond to the circuit schematic for the CMOS inverter in Fig. 7.2. The inverter circuit
consists of one NMOS and one PMOS transistor. The NMOS transistor functions in a manner
identical to that of the switching device in the NMOS gates that we studied in Chapter 6. However,
the PMOS load device is also switched on and off under control of the logic input signal v I .
The CMOS logic gate can be conceptually modeled by the circuit in Fig. 7.2(b), in which
the position of the two switches is controlled by the input voltage v I . The circuit is designed so
464
Chapter 7
Complementary MOS (CMOS) Logic Design
VDD = 5 V
VDD = 5 V
VDD = 5 V
Ron p
Ron p
S
G
MP
vI = VDD
D
vI
vO = 0
vO
G
vI = 0
vO = VDD
D
MN
Ron n
Ron n
S
VSS
(a)
(b)
(c)
Figure 7.2 (a) A CMOS inverter uses one NMOS and one PMOS transistor. (b) A simplified model of
the inverter for a high input level. The output is forced to zero through the on-resistance of the NMOS
transistor. (c) Simplified model of the inverter for a low input level. The output is pulled to VD D through
the on-resistance of the PMOS transistor.
there will never be a conducting path between the positive and negative power supplies under
steady-state conditions. When the NMOS transistor is on, the PMOS transistor is off; if the PMOS
transistor is on, the NMOS device is off.
In the CMOS inverter of Fig. 7.2, the source of the PMOS transistor is connected to VD D , the
source of the NMOS transistor is connected to VSS (0 V in this case), and the drain terminals of
the two MOSFETs are connected together to form the output node. Also, the substrates of both
the NMOS and PMOS transistors are connected to their respective sources, and so body effect is
eliminated in both devices.
Simplified models for the CMOS inverter operation appear in Fig. 7.2(b) and 7.2(c). The input
signal controls the state of the two switches that effectively work as a single-pole double-throw
switch. In Fig. 7.2(b), the input is at a high input level (v I = VD D ), and the output is connected
to ground through the on-resistance of the NMOS transistor. In Fig. 7.2(c), the input is at a low
input level (v I = 0), and the output is connected to VD D through the on-resistance of the PMOS
transistor.
Before we explore the design of the CMOS inverter, we need parameters for the CMOS
devices, as given in Table 7.1. The NMOS parameters are the same as those given in Chapter 6.
In CMOS technology, the transistors are normally designed to have equal and opposite threshold
voltages: for example, VT O N = +1 V and VT O P = −1 V. Remember that K n = µn Cox
and
K p = µ p Cox and that hole mobility in the channel of the PMOSFET is approximately 40 percent
of the electron mobility in the NMOSFET channel. The values in Table 7.1 reflect this difference
because the value of K for the NMOS device is shown as 2.5 times that for the PMOS transistor.
TABLE 7.1
CMOS Transistor Parameters
VT O
γ
2φ F
K
NMOS DEVICE
PMOS DEVICE
1V
√
0.50 V
0.60 V
25 A/V2
−1 √
V
0.75 V
0.70 V
10 A/V2
7.1
CMOS Inverter Technology
465
Processing differences are also reflected in the different values for γ and 2φ F in the two types of
transistors.
Remember that the threshold voltage of the NMOS transistor is denoted by VT N and that of
the PMOS transistor by VT P :
VT N = VT O N + γ N
and
VT P = VT O P − γ P
VS B N + 2φ F N −
VB S P + 2φ F P −
2φ F N
2φ F P
(7.1)
For v S B N = 0, VT N = VT O N , and for v B S P = 0, VT P = VT O P .
Exercises: (a) What are the values of K p and K n for transistors with W/L = 20/1? (b) An
NMOS transistor has VSB = 3.3 V. What is the value of VT N ? (c) A PMOS transistor has
VBS = 3.3 V. What is the value of VT P ?
Answers: (a) 200 A / V2 , 500 A / V2 ; (b) 1.60 V; (c) −1.87 V
7.1.1 CMOS Inverter Layout
Two possible layouts for CMOS inverters appear in Fig. 7.3. In the left-hand layout, the lower
transistor is the NMOS device in the p-type substrate, whereas the upper transistor is the PMOS
device, which is within the boundary of the n-well. The polysilicon gates of the two transistors
are connected together to form the input v I , and the drain diffusions of the two transistors are
connected together by the metallization to form output v O . The sources of the NMOS and PMOS
devices are at the bottom and top of the drawing, respectively, and are connected to the ground
and power supply buss metallization. Each device has a local substrate contact connected to the
source of the transistor. In this particular layout, each transistor has a W/L of 2/1. In the right-hand
Substrate contact
vO
PMOS transistors
VDD
n-well
boundary
21
vI
p+
vI
vO
Polysilicon gate
Metal
VDD
21
n+
Ground
Substrate contact
NMOS transistor
Contact
Figure 7.3 Layout of two CMOS inverters.
Ground
466
Chapter 7
Complementary MOS (CMOS) Logic Design
layout, the two transistors appear side by side with a common polysilicon gate running through
both. Various options for the design of the W/L ratios of the transistors are a major focus of the
rest of this chapter.
7.2 STATIC CHARACTERISTICS OF THE CMOS INVERTER
We now explore the static behavior of CMOS logic gates. First, consider the CMOS inverter with
an input v I = +5 V (1 state), as shown in Fig. 7.4(a). For this input condition, vG S = +5 V for the
NMOS transistor, and vG S = 0 V for the PMOS transistor. For the NMOS device, vG S > VT N (1 V),
so a channel exists in the NMOS transistor, but the PMOS transistor is off because vG S = 0 V for
the PMOS device. Thus, the load capacitor C is eventually fully discharged through the NMOS
transistor, and v O reaches 0 V. Because the PMOS transistor is off, a dc current path does not
exist through M N and M P ! A simplified equivalent circuit for the inverter for a high input level
appears in Fig. 7.4(b). The output capacitance C is discharged to zero through the on-resistance
of the NMOS transistor.
If v I is now set to 0 V (0 state), as in Fig. 7.4(c), vG S becomes 0 V for the NMOS transistor,
and it is cut off. For the PMOS transistor, vG S = −5 V, a channel exists in the PMOS transistor,
VDD = 5 V
VDD = 5 V
Ronp
MP “Off”
vI = 5 V
VL = 0 V
vO = 0
vI = 5 V
“1”
MN “On”
C
(a)
Ronn
C
(b)
VDD = 5 V
VDD = 5 V
Ronp
MP “On”
vI = 0 V
VH = 5 V
vO = VDD
vI = 0
“0”
MN “Off”
(c)
C
Ronn
C
(d)
Figure 7.4 (a) CMOS inverter with the input high. M N is on and M P is off. (b) Simplified model of
the inverter for a high input level. Output capacitance C is discharged to zero through the on-resistance
of the NMOS transistor. (c) CMOS inverter with the input low. M N is off and M P is on. (d) Simplified
model of the inverter for a low input level. Output capacitance C is charged to VD D through the
on-resistance of the PMOS transistor.
7.2 Static Characteristics of the CMOS Inverter
467
and the load capacitor C charges to a value equal to the positive power supply voltage VD D (5 V).
Once a steady-state condition is reached, the currents in M N and M P must both be zero because
the NMOS transistor is off. The corresponding simplified equivalent circuit for the inverter for a
low input level appears in Fig. 7.4(d). In this case, output capacitance C is charged to VD D through
the on-resistance of the PMOS transistor.
Several important characteristics of the CMOS inverter are evident. The values of VH and VL
are equal to the positive and negative power supply voltages, and the logic swing V is equal to
the full power supply span. For the circuit in Fig. 7.4, VH = 5 V, VL = 0 V, and the logic swing
V = 5 V. Of even greater importance is the observation that the static power dissipation is zero,
because I D = 0 in both logic states!
7.2.1 CMOS Voltage Transfer Characteristics
Figure 7.5 shows the result of simulation of the voltage transfer characteristic (VTC) of a symmetrical CMOS inverter, designed with K P = K N . The VTC can be divided into five different
regions, as shown in the figure and summarized in Table 7.2. For an input voltage less than
5.0 V
VIL
VOH 1
Output voltage
4.0 V
2
MN saturated
MP linear
vO = vI + 1
MN off
3.0 V
MN and MP saturated
3
2.0 V
MP saturated
MN linear
1.0 V
VIH
VOL
0V
0V
5
vO = vI – 1
4
1.0 V
2.0 V
MP off
3.0 V
4.0 V
5.0 V
vI
Figure 7.5 CMOS voltage transfer characteristic may be broken down into the five regions outlined
in Table 7.2.
TABLE 7.2
Regions of Operation of Transistors in a Symmetrical CMOS Inverter
REGION
INPUT VOLTAGE v I
OUTPUT
VOLTAGE v O
NMOS
TRANSISTOR
PMOS
TRANSISTOR
1
2
3
4
5
v I ≤ VT N
VT N < v I ≤ v O + VT P
vI ∼
= VD D /2
v O + VT N < v I ≤ (VD D − |VT P |)
v I ≥ (VD D − |VT P |)
VH = VD D
High
VD D /2
Low
VL = 0
Cutoff
Saturation
Saturation
Triode
Triode
Triode
Triode
Saturation
Saturation
Cutoff
468
Chapter 7
Complementary MOS (CMOS) Logic Design
VT N = 1 V in region 1, the NMOS transistor is off, and the output is maintained at VH = 5 V by
the PMOS device.
Similarly, for an input voltage greater than (VD D − |VT P |) (4 V) in region 5, the PMOS
device is off, and the output is maintained at VL = 0 V by the NMOS transistor. In region 2,
the NMOS transistor is saturated, and the PMOS transistor is in the triode region. In region 3,
both transistors are saturated. The boundary between regions 2 and 3 is defined by the boundary
between the saturation and triode regions of operation for the PMOS transistor. Saturation of the
PMOS device requires:
|v DS | ≥ |vG S − VT P |
(5 − v O ) ≥ (5 − v I ) − 1
(7.2)
vO ≤ vI + 1
In a similar manner, the boundary between regions 3 and 4 is defined by saturation of the NMOS
device:
v DS ≥ vG S − VT N
vO ≥ vI − 1
(7.3)
In region 4, the voltages place the NMOS transistor in the triode region, and the PMOS transistor remains saturated. Finally, for the input voltage near VD D /2 (region 3), both transistors are
operating in the saturation region.
Exercise: Suppose v I = 2 V for the CMOS inverter in Fig. 7.4. (a) What is the range of
values of vO for which MN is saturated and MP is in the triode region? (b) For which values
are both transistors saturated? (c) For which values is MP saturated and MN in the triode
region?
Answers: (3 V ≤ vO ≤ 5 V); (1 V ≤ vO ≤ 3 V); (0 V ≤ vO ≤ 1 V)
Exercise: The ( W/L) N of MN in Fig. 7.4 is 10/1. What is the value of ( W/L) P required to
form a symmetrical inverter?
Answer: 25/1
Figure 7.6 shows the results of simulation of the voltage transfer characteristics for a CMOS
inverter with a symmetrical design (K P = K N ) for several values of VD D . Note that the output
voltage levels VH and VL are always determined by the two power supplies. As the input voltage
rises from 0 to VD D , the output remains constant for v I < VT N and v I > (VD D − |VT P |). For
this symmetrical design case, the transition between VH and VL is centered at v I = VD D /2. The
straight line on the graph represents v O = v I , which occurs for v I = VD D /2 for the symmetrical
inverter.
K n , then the transition shifts away from VD D /2. To simplify notation, a parameter
If K p =
K R is defined: K R = K n /K p . K R represents the relative current drive capability of the NMOS
and PMOS devices in the inverter. Voltage transfer characteristics for inverters with K R = 5, 1,
and 0.2 are shown in Fig. 7.7. For K R > 1, the NMOS current drive capability exceeds that of the
7.2 Static Characteristics of the CMOS Inverter
469
6.0 V
6.0 V
VDD = 5 V
4.0 V
VDD = 3 V
2.0 V
Output voltage
Output voltage
4.0 V
vO = vI
KR = 5
VDD = 4 V
vO = vI
VDD = 2 V
KR = 1
2.0 V
KR = 0.2
0V
0V
0V
1.0 V
2.0 V
3.0 V
vI
4.0 V
5.0 V
6.0 V
0V
1.0 V
2.0 V
3.0 V
4.0 V
5.0 V
vI
Figure 7.6 Voltage transfer characteristics for a
Figure 7.7 CMOS voltage transfer characteristics for
symmetrical CMOS inverter (K R = 1) with VD D = 5 V,
4 V, 3 V, and 2 V.
K R = 5, 1, and 0.2 for VD D = 5 V.
PMOS transistor, so the transition region shifts to v I < VD D /2. Conversely, for K R < 1, PMOS
current drive capability is greater than that of the NMOS device, and the transition region occurs
for v I > VD D /2.
As discussed briefly in Chapter 4, FETs do not actually turn off abruptly as indicated in
Eq. (4.9), but conduct small currents for gate-source voltages below threshold. This characteristic
enables a CMOS inverter to function at very low supply voltages. In fact, it has been shown
that the minimum supply voltage for operation of CMOS is only 2VT ln (2) V [2, 3]. At room
temperature this voltage is less than 40 mV!
Exercises: Equate the expressions for the drain currents of MN and MP to show that vO =
v I occurs for a voltage equal to VD D /2 in a symmetrical inverter. What voltage corresponds
to vO = v I in an inverter with K R = 10 and VD D = 4 V?
Answer: 1.48 V
7.2.2 Noise Margins for the CMOS Inverter
Because of the importance of the CMOS logic family, we explore the noise margins of the inverter
in some detail. VI L and VI H are identified graphically in Figs. 7.5 and 7.8 as the points at which
the voltage transfer characteristic has a slope of −1. First, we will find VI H .
For v I near VI H , the v DS of M P will be large and that of M N will be small. Therefore, we
assume that the PMOS device is saturated and the NMOS device is in its triode region. The two
drain currents must be equal, so i D N = i D P , and
vO
Kp
K n v I − VT N −
(7.4)
(v O ) =
(v I − VD D − VT P )2
2
2
For M N , vG S = v I and vG S = v O . For M P , vG S = v I − VD D and v DS = v O − VD D . Now
K R (2v I − 2VT N − v O )(v O ) = (v I − VD D − VT P )2
(7.5)
Chapter 7
Complementary MOS (CMOS) Logic Design
Slope = –1
VOH
4.0 V
Output voltage
470
2.0 V
0V
0V
Slope = –1
VOL
VIH
VIL
1.0 V
2.0 V
3.0 V
4.0 V
5.0 V
vI
Figure 7.8 CMOS voltage transfer characteristic, with VI L and VI H indicated.
in which K R = K n /K p . Solving for v O yields
v O = (v I − VT N ) ±
(v I − VT N )2 −
(v I − VD D − VT P )2
KR
(7.6)
Taking the derivative with respect to v I and setting it equal to −1 at v I = VI H is quite involved
(and is most easily done with a symbolic algebra package1 on the computer), but eventually yields
this result:
VI H =
2K R (VD D − VT N + VT P ) (VD D − K R VT N + VT P )
√
−
KR − 1
(K R − 1) 1 + 3K R
(7.7)
The value of VO L corresponding to VI H is
VO L =
(K R + 1)VI H − VD D − K R VT N − VT P
2K R
(7.8)
For the special case of K R = 1,
VI H =
5VD D + 3VT N + 5VT P
8
and
VO L =
VD D − VT N + VT P
8
(7.9)
VI L can be found in a similar manner using i D N = i D P . For v I near VI L , the v DS of M P will
be small and that of M N will be large, so we assume that the NMOS device is saturated and the
PMOS device is in its linear region. Equating drain currents:
v O − VD D
Kn
K p v I − VD D − VT P −
(v O − VD D ) =
(v I − VT N )2
2
2
or
(7.10)
(2v I − VD D − 2VT P − v O )(v O − VD D ) = K R (v I − VT N )2
1
For example, Mathematica, MAPLE, Macsyma, and so on.
7.2 Static Characteristics of the CMOS Inverter
471
Again, we solve for v O , take the derivative with respect to v I , and set the result equal to −1 at
v I = VI L . This process yields
VI L
√
2 K R (VD D − VT N + VT P ) (VD D − K R VT N + VT P )
√
=
−
KR − 1
(K R − 1) K R + 3
(7.11)
The value of VO H corresponding to VI L is given by
VO H =
(K R + 1)VI L + VD D − K R VT N − VT P
2
(7.12)
For the special case of K R = 1,
VI L =
3VD D + 5VT N + 3VT P
8
and
VO H =
7VD D + VT N − VT P
8
(7.13)
The noise margins for K R = 1 are found using the results in Eqs. (7.9) and (7.13):
NM H =
VD D − VT N − 3VT P
4
and
NM L =
VD D + 3VT N + VT P
4
(7.14)
For VD D = 5 V, VT N = 1 V and VT P = −1 V, the noise margins are both equal to 1.75 V.
Figure 7.9 is a graph of the CMOS noise margins versus K R from Eqs. (7.8) and (7.11) for
the particular case VD D = 5 V, VT N = 1 V, and VT P = −1 V. For a symmetrical inverter design
(K R = 1), the noise margins are both equal to 1.75 V in agreement with the results already
presented.
4
NMH
Noise margin (volts)
3
2
NML
1
0
0
2
6
8
10
4
Transconductance ratio KR
12
Figure 7.9 Noise margins versus K R for the CMOS inverter with VD D = 5 V and VT N = −VT P = 1 V.
Exercise: What is the value of K R for a CMOS inverter in which ( W/L) P = ( W/L) N ? Calculate the noise margins for this value of K R with VD D = 5 V, VT N = 1 V and VT P = −1 V.
Answers: 2.5; NM L = 1.30 V, NM H = 2.29 V
472
Chapter 7
Complementary MOS (CMOS) Logic Design
7.3 DYNAMIC BEHAVIOR OF THE CMOS INVERTER
Static power dissipation and the values of VH and VL do not really represent design parameters
in CMOS circuits. Instead, the choice of sizes of the NMOS and PMOS transistors is dictated by
the dynamic behavior of the logic gate — namely, by the desired average propagation delay τ p .
7.3.1 Propagation Delay Estimate
We can get an estimate of the propagation delay in the CMOS inverter by studying the circuit in
Fig. 7.10, in which the inverter is driven by an ideal step function. For t < 0, the NMOS transistor
is off and the PMOS transistor is on, forcing the output into the high state with v O = VH = VD D .
At t = 0, the input abruptly changes from 0 V to 5 V, and for t = 0+ , the NMOS transistor is on
(vG S = +5 V) and the PMOS transistor is off (v SG = 0 V). Thus, the circuit simplifies to that in
Fig. 7.10(b). The capacitor voltage is equal to VD D at t = 0+ , and the capacitor voltage begins
to fall as C is discharged through the NMOS transistor. The NMOS device starts conduction in
the saturation region with v DS = vG S = VD D , and enters the triode region of operation when
v DS = (vG S − VT N ) = (VD D − VT N ). The NMOS device continues to discharge C until its v DS
becomes zero. Therefore, VL = 0 V.
VDD = 5 V
MP
vI = 5 V
vI
vO (0+) = 5 V
vO
MN
MN
C
vO
vI
+5 V
+5 V
t
0V
t
0V
0
(a)
C
0
(b)
Figure 7.10 High-to-low output transition in a CMOS inverter.
A significant amount of effort can be saved by realizing that the set of operating conditions
in Fig. 7.10 is exactly the same as was used to determine τ P H L for the NMOS inverter with either
a resistive or depletion-mode load. Using Eq. (6.61),
τP H L
VH − VT N
2VT N
= Ronn C ln 4
−1 +
V H + VL
VH − VT N
where Ronn =
1
K n (VH − VT N )
(7.15)
For the CMOS inverter with VH = 5 V, VT N = 1 V, and VL = 0, τ P H L becomes
τ P H L = 1.29Ronn C =
0.32C
Kn
(7.16)
7.3
473
Dynamic Behavior of the CMOS Inverter
Now consider the inverter driven by a step function that switches from +5 V to 0 V at t = 0,
as in Fig. 7.11. For t < 0, the PMOS transistor is off and the NMOS transistor is on, forcing the
output into the low state with v O = VL = 0. At t = 0, the input abruptly changes from 5 V to
0 V. For t = 0+ , the PMOS transistor will be on (vG S = −5 V) and the NMOS transistor will be
off (vG S = 0 V). Thus, the circuit simplifies to that in Fig. 7.11(b). The voltage on the capacitor
at t = 0+ is equal to zero, and it begins to rise toward VD D as charge is supplied through the
PMOS transistor. The PMOS device begins conduction in the saturation region and subsequently
enters the triode region of operation. This device continues to conduct until v DS becomes zero,
when v O = VH = VD D . The same set of equations that was used to arrive at Eqs. (7.15) and
(7.16) apply to this circuit, and for the CMOS inverter with VD D = 5 V, and VT P = −1 V, τ P L H
becomes
τ P L H = 1.29Ron p C
for Ron p =
τP L H =
1
K p (VH + VT P )
(7.17)
0.32C
Kp
(7.18)
The only difference between Eqs. (7.16) and (7.18) is the value of Ronn and Ron p . From
Table 7.1, we expect K n to be approximately 2.5 times the value of K p . In CMOS, a “symmetrical”
inverter with τ P L H = τ P H L can be designed if we set (W/L) P = (K n /K p )(W/L) N = 2.5(W/L) N
in order to compensate for the difference in mobilities. Because of the layout design rules in many
MOS technologies, it is often convenient to design the smallest transistor with (W/L) = (2/1).
We use the symmetrical inverter design in Fig. 7.12, which has (W/L) N = (2/1) and (W/L) P =
(5/1) as our CMOS reference inverter in the subsequent design of more complex CMOS logic
gates.
Because we have designed this gate to have τ P L H = τ P H L , the average propagation delay is
given by
τp =
τP H L + τP L H
0.32C
= τP H L =
2
Kn
VDD = 5 V
VDD = 5 V
MP
MP
vI
vO
MN
(7.19)
vO (0+) = 0 V
VI = 0 V
C
C
VDD = 5 V
vI
MP
vO
+5 V
+5 V
vI
t
0V
t
0V
0
(a)
5
1
MN
vO
2
1
0
( b)
Figure 7.11 Low-to-high output transition in a
Figure 7.12 Symmetrical
CMOS inverter.
reference inverter design.
C
474
Chapter 7
Complementary MOS (CMOS) Logic Design
Exercise: Calculate the propagation delay of the reference inverter in Fig. 7.12 for
C = 1 pF.
Answer: 6.4 ns
7.3.2 Rise and Fall Times
In a CMOS inverter, the rise and fall times are approximately twice the corresponding propagation
delay times, and we use
t f = 2τ P H L
tr = 2τ P L H
and
(7.20)
Based on the results of the preceding exercise for the 1-pF load capacitance, the expected rise and
fall times are 12.8 ns.
To increase or decrease the speed of the CMOS inverter, the sizes of the transistors are changed.
The inverter in Fig. 7.13(a) has a delay of 1 ns because the W/L ratios of both transistors are
6.4 times larger than those in the reference inverter design in Fig. 7.12. The inverter in Fig. 7.13(b)
has a delay of 3.2 ns because its transistors are four times larger than those in the reference inverter,
but it is driving twice as much capacitance:
τ p = (6.4 × 2/4) ns
VDD = 5 V
VDD = 5 V
32
1
MP
vI
MP
vI
vO
MN
12.8
1
(a)
vO
MN
1 pF
20
1
8
1
2 pF
( b)
Figure 7.13 Scaled inverters: (a) τ p = 1 ns, (b) τ p = 3.2 ns.
Exercise: An inverter must drive a 5-pF load capacitance with τ p = 1 ns. Scale the reference inverter to achieve this delay.
Answer: ( W/L) P = 160/1 and ( W/L) N = 64/1
DESIGN
EXAMPLE 7.1
REFERENCE INVERTER DESIGN
In this example, we design a reference inverter to achieve a desired value of delay.
DESIGN Design a reference inverter to achieve a delay of 250 ps when driving a 0.1-pF load using a
SPECIFICATIONS 3.3-V power supply. Assume that the threshold voltages of the CMOS technology have been
reduced to VT N = −VT P = 0.75 V.
7.3
Dynamic Behavior of the CMOS Inverter
475
SOLUTION Specifications and Known Information: VD D = 3.3 V, C = 0.1 pF, τ p = 250 ps, VT N =
−VT P = 0.75 V
Unknowns: (W/L)n , (W/L) p
Approach: Use Eq. (7.15) to find the value of Ronn and (W/L)n ; (W/L) p = 2.5(W/L) p .
Assumptions: A symmetrical inverter design is desired; the K values are the same as Table 7.1:
K n = 25 A/V2 , K p = 10 A/V2
Analysis: Using Eq. (7.15),
Ronn =
=
W
L
=
n
τP H L
1
VD D − VT N
−1 +
C ln 4
V D D + VL
2
2.5 × 10−10 s
= 2020 3.3 − 0.75
1
10−13 F ln 4
−1 +
3.3 + 0
2
7.77
1
=
A
− VT N )
1
25 2 (2020 )(3.3 − 0.75) V
V
W
K n W
W
19.4
= = 2.5
=
L p
Kp L n
L n
1
1
=
K n Ronn (VD D
Check of Results: Let us double check the value of on-resistance for the PMOS device:
Ron p =
1
K p (VD D + VT P )
=
A
(19.4) 10 2
V
1
= 2020 ✔
(3.3 − 0.75) V
Discussion: The on-resistances are equal, so the rise and fall times should be the same. The
Ron C time constant is 200 ps, which appears consistent with our design goal.
Computer-Aided Analysis: Our design is checked in the SPICE circuit on the next page.
Source VS is a pulse source and the output waveform is the voltage across the capacitor.
From the output waveforms, we find symmetrical rise and fall times of approximately 260 ns,
confirming our design.
PULSE SOURCE DESCRIPTION (VS)
Initial voltage
Peak voltage
Delay time
Rise time
Fall time
Pulse width
Pulse period
0
3.3 V
0
2 ps
2 ps
3 ns
6 ns
SIMULATION PARAMETERS
Start time
Stop time
Time step
0
6 ns
5 ps
476
Chapter 7
Complementary MOS (CMOS) Logic Design
MP
VDD
VO
3.3 V
VS
MN
0.1 pF
C
(V)
+3.500
+3.000
vS
vO
+2.500
+2.000
+1.500
+1.000
+0.500
0
0
1
2
3
Time (ns)
4
5
6
Exercise: What would be the W/L ratios in Ex. 7.1 if the threshold voltages of the transistors were +0.5 V and −0.5 V?
Answers: 7.85/1, 19.6/1 (Ronn = 1820 )
7.3.3 Delay of Cascaded Inverters
Obviously, the ideal step-function input waveform used in the analysis leading to Eq. (7.15)
cannot be achieved in real circuits. The waveforms will have nonzero rise and fall times, and the
propagation delay estimate given by Eq. (7.15) is more optimistic than the delay encountered in
actual circuits. Let us use SPICE to help improve the propagation delay design equation through
simulation of the cascade of six identical inverters shown in Fig. 7.14(a). The first inverter is
driven by a pulse with a 5-ns width, a 10-ns period, and rise and fall times of 2 ps.
The outputs of the six inverters are shown in the waveforms in Fig. 7.14(b). The propagation
time between the step input and the output of the first inverter is approximately 0.25 ns in
agreement with the design of Ex. 7.1. However, the delay times of the other five inverters are
7.3
1
vS
2
C
3
C
477
Dynamic Behavior of the CMOS Inverter
4
C
5
C
6
C
C
(a)
+3.000
–v1
–v5
–v3
+2.000
+1.000
–v2
–v4
–v6
–v3
–v5
+0.000
0
(b)
+2.00
+4.00
Time (ns)
+6.00
+8.00
Figure 7.14 (a) Cascade of six identical inverters. (b) Output waveforms for six inverters using design
from Ex. 7.1. VS is a step function, VD D = 3.3 V and C = 0.1 pF.
significantly slower because of the rise and fall times of the waveforms driving each successive
inverter. Looking at every other inverter, we see that the waveforms are very similar and quickly
reach a periodic state. The average delay time through each inverter pair is 1 ns, corresponding
to τ P H L = τ P L H = 0.5 ns. This value is approximately two times that predicted by Eq. (7.15).
Based on these results, we will modify our design estimate for the propagation delays to be
τP H L ∼
= 2Ronn C
τP L H
1
VD D − VT N
−1 +
ln 4
V D D + VL
2
1
VD D + VT P
∼
−1 +
= 2Ron p C ln 4
VH
2
Ronn =
1
K n (VD D − VT N )
(7.21)
Ron p =
1
K p (VD D + VT P )
Exercise: What are the new equations [similar to Eqs. (7.16) and (7.17)] for τ P H L and τ PL H
for VD D = 5 V, VT N = 1 V, and VT P = −1 V?
Answers: τ P H L = 2.58RonnC = 0.644C/K n , τ PL H = 2.58Ron pC = 0.644C/K p
Exercise: What are the new equations [similar to Eqs. (7.16) and (7.17)] for τ P H L and τ PL H
for VD D = 3.3 V, VT N = 0.75 V, and VT P = −0.75 V?
Answers: τ P H L = 2.48RonnC = 0.971C/K n , τ PL H = 2.48Ron pC = 0.971C/K p
478
Chapter 7
Complementary MOS (CMOS) Logic Design
7.4 POWER DISSIPATION AND POWER DELAY
PRODUCT IN CMOS
7.4.1 Static Power Dissipation
CMOS logic is often considered to have zero static power dissipation. When the CMOS inverter is
resting in either logic state, no direct current path exists between the two power supplies (VD D and
ground). However, in very low power applications or in IC designs with extremely large numbers
of gates, static power dissipation can be important. The actual static power dissipation is nonzero
due to the leakage currents associated with the reverse-biased drain-to-substrate junctions of the
NMOS and PMOS transistors as well as with the large area of reverse-biased n-well (or p-well)
regions. The leakage current of these pn junctions flows between the supplies and contributes
directly to static power dissipation. Power dissipation resulting from leakage can be a serious
concern, particularly for battery-powered applications.
7.4.2 Dynamic Power Dissipation
There are two components of dynamic power dissipation in CMOS logic gates. As the gate charges
and discharges load capacitance C at a frequency f , the power dissipation is equal to that given
by Eq. (6.47) in Chapter 6:
PD = C VD2 D f
(7.22)
Power PD is usually the largest component of power dissipation in CMOS gates operating at high
frequency.
A second mechanism for power dissipation also occurs during switching of the CMOS logic
gate and can be explored by referring to Fig. 7.15, which shows the current through a symmetrical
CMOS inverter (with C = 0) as a function of the input voltage v I . The current is zero for
v I < VT N and v I > (VD D − |VT P |) because either the NMOS or PMOS transistor is off for these
conditions. For an input voltage exceeding VT N , a current path exists through both the NMOS and
PMOS devices, and the current reaches a peak for v I = v O = VD D /2. As v I increases further, the
current decreases back to zero. In the time domain, a pulse of current occurs between the power
6.0 V
Output voltage
80 µA
4.0 V
40 µA
2.0 V
Drain current
0V
0 µA
0V
2.0 V
4.0 V
6.0 V
vI
Figure 7.15 Supply current versus input voltage for a symmetrical CMOS inverter.
7.4
479
vO
Voltage
5.0 V
Power Dissipation and Power Delay Product in CMOS
0.0 V
vI
60 µA
Current
iDD
0 µA
0s
4 ns
8 ns
Time
12 ns
16 ns
Figure 7.16 SPICE simulation of the transient current pulses between the power supplies during
switching of a CMOS inverter.
supplies as the output switches state, as shown in Fig. 7.16. In very high speed CMOS circuits,
this second component of dynamic power dissipation can approach 20 to 30 percent of that given
by Eq. (7.22).
In the technical literature, this current pulse between supplies is often referred to as a “short
circuit current.” This reference is a misnomer, however, because the current is limited by the
device characteristics, and a short circuit does not actually exist between the power supplies.
Exercise: Calculate the value of the maximum current similar to that in Fig. 7.15 for the
inverter design in Fig. 7.12.
Answer: 56.3 A
7.4.3 Power-Delay Product
The power-delay product (PDP), defined in Sec. 6.3, is an important figure of merit for comparing
various logic technologies:
PDP = Pav τ P
(7.23)
For CMOS, the power consumed when charging and discharging the load capacitance C is usually
the dominant source of power dissipation. For this case, Pav = C VD2 D f . The switching frequency
f = (1/T ) can be related to the rise time tr , fall time t f , and the propagation delay τ P of the
CMOS waveform by referring to Fig. 7.17, in which we see that the period T must satisfy
T ≥ tr + ta + t f + tb
(7.24)
For the highest possible switching frequency, the times ta and tb approach 0, and the rise
and fall times account for approximately 80 percent of the total transition time. Assuming a
480
Chapter 7
Complementary MOS (CMOS) Logic Design
ta
tf
tr
tb
T
Figure 7.17 CMOS switching waveform at high frequency.
symmetrical inverter design with equal rise and fall times and using Eqs. (7.19) and (7.20) permits
Eq. (7.24) to be approximated by
T ≥
2tr
2(2τ P )
=
= 5τ P
0.8
0.8
(7.25)
A lower bound on the power-delay product for CMOS is then given by
PDP ≥
C VD2 D
C VD2 D
τP =
5τ P
5
(7.26)
The importance of using lower power supply voltages is obvious in Eq. (7.26), from which
it is clear that the PDP is reduced in proportion to the square of any reduction in power supply.
Moving from a power supply voltage of 5 V to one of 3.3 V reduces the power-delay product by
a factor of 2.5. The importance of reducing the capacitance is also clear in Eq. (7.26). The lower
the effective load capacitance, the smaller the power-delay product.
Exercise: (a) What is the power-delay product for the symmetrical reference inverter in
Fig. 7.12 operating from VD D = 5 V and driving an average load capacitance of 100 fF?
(b) Repeat for a 3.3-V supply.
Answers: 0.5 pJ; 0.18 pJ
7.5 CMOS NOR AND NAND GATES
The next several sections explore the design of CMOS gates, including the NOR gate, the NAND
gate, and complex CMOS gates. The structure of a general static CMOS logic gate is given in
Fig. 7.18 and consists of an NMOS transistor-switching network and a PMOS transistor-switching
network. For each logic input variable in a CMOS gate, there is one transistor in the NMOS network
and one transistor in the PMOS network. Thus, a CMOS logic gate has two transistors for every
input variable. When a conducting path exists through the NMOS network, a path must not exist
through the PMOS network and vice versa. In other words, the conducting paths must represent
logical complements of each other. CMOS forms an unusually powerful logic family, because it
is easy to realize both NOR and NAND gates as well as much more complex logic functions in a
7.5
VDD = 5 V
VDD = 5 V
VDD
10
1
MP
vI
PMOS switching
network
Logic
inputs
10
1
Y
NMOS switching
network
2
1
A
Figure 7.18 Basic CMOS logic gate structure.
481
CMOS NOR and NAND Gates
vO
MN
Y
2
1
B
5
1
2
1
C
C
Figure 7.19 Two-input CMOS NOR gate and reference inverter.
single gate. In Secs. 7.5.1 and 7.5.2, we will look at the NOR and NAND gate design. Then more
complex gate design will be discussed.
7.5.1 CMOS NOR Gate
The realization of a two-input CMOS NOR gate is shown in Fig. 7.19. For the NOR gate, the
output should be low when either input A or input B is high. Thus the NMOS portion of the gate
is identical to that of the NMOS NOR gate. However, in the CMOS gate, we must ensure that a
static current path does not exist through the logic gate, and this requires the use of two PMOS
transistors in series in the PMOS transistor network.
The complementary nature of the conducting paths can be seen in Table 7.3. A conducting
path exists through the NMOS network for A = 1 or B = 1 as indicated by the highlighted entries
in the table. However, a path exists through the PMOS network only when both A = 0 and B = 0
(no conducting path through the NMOS network).
TABLE 7.3
CMOS NOR Gate Truth Table and Transistor States
A
B
Y = A+B
NMOS-A
NMOS-B
PMOS-A
PMOS-B
0
0
1
1
0
1
0
1
1
0
0
0
Off
Off
On
On
Off
On
Off
On
On
On
Off
Off
On
Off
On
Off
In general, a parallel path in the NMOS network corresponds to a series path in the PMOS
network, and a series path in the NMOS network corresponds to a parallel path in the PMOS
network. (Bridging paths correspond to bridging paths in both networks.) We will study a rigorous
method for implementing these two networks shortly.
Transistor Sizing
We can determine the sizes of the transistors in the two-input NOR gate by using our knowledge
of NMOS gate design. In the CMOS case, we try to maintain the delay times equal to the
reference inverter design under the worst-case input conditions. For the NMOS network with
482
Chapter 7
Complementary MOS (CMOS) Logic Design
AB = 10 or 01, transistor A or transistor B must individually be capable of discharging the load
capacitance C, so each must be the same size as the NMOS device of the reference inverter. The
PMOS network conducts only when AB = 00 and there are two PMOS transistors in series. To
maintain the same on-resistance as the reference inverter, each PMOS device must be twice as
large: (W/L) P = 2(5/1) = 10/1. The resulting W/L ratios are indicated in Fig. 7.19.
Body Effect
In the preceding design, we ignored the influence of body effect. In the series-connected PMOS
network, the source of the interior PMOS transistor cannot be connected to its substrate. During
switching, its threshold voltage changes as its source-to-bulk voltage changes. However, once the
steady-state condition is reached, with v O = VH , for example, all the PMOS source and drain
nodes will be at a voltage equal to VD D . Thus, the total on-resistance of the PMOS transistors is
not affected by the body effect once the final logic level is reached. During the transient response,
however, the threshold voltage changes as a function of time and |VT P | > |VT O P |, which slows
down the rise time of the gate slightly. An investigation of this effect is left for Probs. 7.52 to 7.55.
Two-Input NOR Gate Layout
A possible layout for the two-input NOR gate is shown in Fig. 7.20. The two NMOS transistors
are formed in the substrate and each has a 2/1 W/L ratio. The PMOS transistors, each with
W/L = 10/1, are located in a common n-well. Note that the drain of the upper PMOS device
is merged with the source of the lower PMOS device to form the connection between these two
transistors. No contacts or metal are required to make this connection.
The gates of the NMOS and PMOS transistors are connected together with the metal level at
inputs A and B, and the drains of three transistors are connected together by the metal layer to
form output Y . Local substrate contacts are provided next to the sources of the NMOS transistors
and the upper PMOS device. Note the much larger area taken up by the PMOS devices caused by
the symmetrical gate design specification.
Substrate contact
Polysilicon gate
VDD
101
101
n-well
p+
Y
A
21
B
21
Ground
Substrate Contact
contact
n+
Metal
Figure 7.20 Layout of symmetrical two-input CMOS NOR gate. Note the large area of the PMOS
transistors relative to the NMOS devices.
7.5
CMOS NOR and NAND Gates
483
Three-Input NOR Gate
Figure 7.21 is the schematic for a three-input version of the NOR gate, and Table 7.4 is the truth
table. As in the case of the NMOS gate, the output is low when NMOS transistor A or transistor
B or transistor C is conducting. The only time that a conducting path exists through the PMOS
network is for A = B = C = 0. The NMOS transistors must each individually be able to
discharge the load capacitance in the desired time, so the W/L ratios are each 2/1 based on our
reference inverter design. The PMOS network now has three devices in series, so each must be
three times as large as the reference inverter device (W/L = 15/1).
It is possible to find the PMOS network directly from the truth table. From Table 7.3 for the
two-input NOR gate, we see that Y = AB and, using the identities in Table 6.7, the expression for
Y = A+ B. For the three-input NOR gate described by Table 7.4, Y = A B C and Y = A+ B +C.
The PMOS network directly implements the logic function Y = A B C, written in terms of
the complements of the input variables, and the NMOS network implements the logic function
Y = A + B + C, written in terms of the uncomplemented input variables. In effect, the PMOS
transistors directly complement the input variables for us! The two functions Y and Y for the
NMOS and PMOS networks need to be written in minimum form in order to have the minimum
number of transistors in the two networks.
VDD = 5 V
VDD = 5 V
15
1
MP
vI
vO
15
1
MN
15
1
2
1
A
5
1
2
1
Y
2
1
B
2
1
C
C
Figure 7.21 Three-input CMOS NOR gate and reference inverter.
TABLE 7.4
Three-Input NOR Gate Truth Table
A
B
C
Y = A+ B +C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
C
484
Chapter 7
Complementary MOS (CMOS) Logic Design
NMOS transistors
PMOS transistors
Figure 7.22 Shorthand notation for NMOS and PMOS transistors.
The complementing effect of the PMOS devices has led to a shorthand representation for
CMOS logic gates that is used in many VLSI design texts. This notation is shown by the right-hand
symbol in each transistor pair in Fig. 7.22. The NMOS and PMOS transistor symbols differ only
by the circle at the input of the PMOS gate. This circle identifies the PMOS transistor and indicates
the logical inversion operation that is occurring to the input variable. In this book, however, we
will continue to use the standard symbol.
7.5.2 CMOS NAND Gates
The NAND gate is also easy to realize in CMOS, and the structure and truth table for a two-input
static CMOS NAND gate are given in Fig. 7.23 and Table 7.5, respectively. From the truth table
for the NAND gate, we see that Y = AB, and the output should be low only when both input A
and input B are high. Thus, the NMOS switching network is identical to that of the NMOS NAND
gate with transistors A and B in series.
Expanding the equation for Y in terms of complemented variables, we have Y = A + B. If
either input A or input B is low, the output must be pulled high through a PMOS transistor, resulting
in two transistors in parallel in the PMOS switching network. Once again, there is one transistor
in the NMOS network and one transistor in the PMOS network for each logic input variable.
VDD = 5 V
5
1
5
1
VDD = 5 V
MP
Y
vI
4
1
A
5
1
vO
MN
2
1
C
C
4
1
B
Figure 7.23 Two-input CMOS NAND gate and reference inverter.
TABLE 7.5
CMOS NAND Gate Truth Table and Transistor States
A
B
Y = AB
NMOS-A
NMOS-B
PMOS-A
PMOS-B
0
0
1
1
0
1
0
1
1
1
1
0
Off
Off
On
On
Off
On
Off
On
On
On
Off
Off
On
Off
On
Off
7.6
Design of Complex Gates in CMOS
485
Transistor Sizing
We determine the sizes of the transistors in the two-input NAND gate by again using our knowledge
of NMOS design. There are two transistors in series in the NMOS network, so each should be
twice as large as in the reference inverter or 4/1. In the PMOS network, each transistor must
individually be capable of discharging the load capacitance C, so each must be the same size as
the PMOS device in the reference inverter. These W/L ratios are indicated in Fig. 7.23.
The Multi-Input NAND Gate
As another example, the circuit for a five-input NAND gate is given in Fig. 7.24. The NMOS
network consists of a series stack of five transistors with one MOS device for each input variable.
The PMOS network consists of a group of PMOS devices in parallel, also with one transistor for
each input. To maintain the speed on the high-to-low transition in the five-input gate, the NMOS
transistors must each be five times larger than that of the reference inverter, whereas the PMOS
transistors are each identical to that of the reference inverter.
VDD = 5 V
5
1
5
1
5
1
5
1
5
1
Y
10
1
A
10
1
10
1
10
1
10
1
C
B
C
D
E
Figure 7.24 Five-input CMOS NAND gate: Y = ABC D E.
Exercise: Draw a four-input NAND gate similar to the five-input gate in Fig. 7.24. What are
the W/L ratios of the transistors?
Answers: 8/1; 5/1
7.6 DESIGN OF COMPLEX GATES IN CMOS
Just as with NMOS design, the real power of CMOS is not realized if the designer uses only
NANDs, NORs, and inverters. The ability to implement complex logic gates directly in CMOS
is an advantage for CMOS design, just as it is in NMOS. This section investigates complex gate
design by exploring Examples 7.2 and 7.3.
486
Chapter 7
DESIGN
EXAMPLE 7.2
Complementary MOS (CMOS) Logic Design
COMPLEX CMOS LOGIC GATE DESIGN
This example presents the design of a CMOS logic gate with the same logic function as NMOS
design from Fig. 6.37 in Chapter 6. A graphical approach for relating NMOS and PMOS
transistor networks is introduced as part of the example.
DESIGN
SPECIFICATIONS Design a CMOS logic gate logic that implements the function Y = A + BC + B D.
SOLUTION Specifications and Known Information: Logic function Y = A + BC + B D or Y = A +
BC + B D. The NMOS network in Fig. 7.25(a) for Y is exactly the same as that of the
NMOS gate. (Note that Y is represented as a sum-of-products form.)
Unknowns: Topology of the PMOS network; W/L ratios of all the transistors
+5 V
A
B
C
D
3
PMOS
switch
network
2
B
Y
2
B
MB
4
1
A
MA
2
1
C
MC
4
1
D
1
A
1
C
MD
4
1
D
0
0
( b)
(a)
2
B
2
3
4
1
A
C
B
2
3
5
A
D
4
C
1
5
0
D
0
(c)
(d)
Figure 7.25 Steps in constructing graphs for NMOS and PMOS networks. (a) NMOS network.
(b) NMOS graph. (c) NMOS graph with new nodes added. (d) Graph with PMOS arcs added.
2
7.6
Design of Complex Gates in CMOS
487
Approach: In this case, we already have the NMOS network (Fig. 6.37) but need to construct
the corresponding PMOS network. A new graphical method for finding the PMOS network
will be introduced for this design. Once the PMOS circuit topology is found, then the transistor
W/L values can be determined.
Assumptions: Use a symmetrical design based on the reference inverter in Fig. 7.12.
Analysis: In this case, we have been given the NMOS network. First we construct a graph
of NMOS network, which is shown in Fig. 7.25(b). Each node in the NMOS network corresponds
to a node in the graph, including node 0 for ground and node 2 for the output. Each NMOS
transistor is represented by an arc connecting the source and drain nodes of the transistors and
is labeled with the logical input variable.
Next, we construct the PMOS network directly from the graph of the NMOS network.
First, place a new node inside of every enclosed path [nodes 4 and 5 in Fig. 7.25(c)] in the
NMOS graph. In addition, two exterior nodes are needed: one representing the output and one
representing VD D [nodes 2 and 3 in Fig. 7.25(c)]. An arc, ultimately corresponding to a PMOS
transistor, is then added to the graph for each arc in the NMOS graph. The new arcs cut through
the NMOS arcs and connect the pairs of nodes that are separated by the NMOS arcs. A given
PMOS arc has the same logic label as the NMOS arc that is intersected. This construction results
in a minimum PMOS logic network, which has only one PMOS transistor per logic input. The
completed graph is given in Fig. 7.25(d), and the corresponding PMOS network is shown in
Fig. 7.26. A transistor is added to the PMOS switching network corresponding to each arc in
the PMOS graph. Note that nodes 2 and 2 represent the same output node.
Final CMOS circuit
3
+5 V
15
1
A
4
15
1
C
7.5
1
B
5
15
1
D
2
Y
B
MB
4
1
1
A
MA
2
1
C
MC
4
1
D
MD
4
1
Figure 7.26 CMOS implementation of Y = A + BC + B D.
488
Chapter 7
Complementary MOS (CMOS) Logic Design
To complete the design of this CMOS gate, we must choose the W/L ratios of the transistors.
In the NMOS switching network, the worst-case path contains two transistors in series, and
transistors B, C, and D should each be twice as large as those of the reference inverter. Transistor
A should be the same size as the NMOS transistor in the reference inverter because it must be
able to discharge the load capacitance by itself. In the PMOS switching network, the worst-case
path has three transistors in series, and PMOS transistors A, C, and D should be three times
as large as the PMOS device in the reference inverter. The size of transistor B is determined
using the on-resistance method from Eq. (6.36), in which Ron represents the on-resistance of a
reference transistor with W/L = 1/1:
R
R
R
on + on = on
15
W
5
1
L B
1
or
W
L
=
B
7.5
1
The completed design appears in Fig. 7.26.
Figure 7.27 gives a second implementation of the same logic network; here nodes 2 and 3
in the PMOS graph have been interchanged. The conducting paths through the PMOS network
are identical, and hence the logic function is also the same.
+5 V
D
15
1
C
15
1
7.5
1
B
15
1
A
Y
B
A
MA
2
1
C
MB
MC
4
1
4
1
D
MD
4
1
Figure 7.27 Circuit equivalent to gate in Fig. 7.26.
Check of Results: Another approach can be used to check the PMOS network topology. Note
that the PMOS network implements the function obtained by expanding Y as a product of
sums:
Y = A + B(C + D) = A · (B + C D)
7.6
Design of Complex Gates in CMOS
489
The inversion of each variable is provided directly by the PMOS transistor (remember the
PMOS transistor symbol introduced in Fig. 7.22). A conducting path is formed through the
PMOS network when A is conducting, and either B is conducting, or C and D are both
conducting. The network structure appears to be correct. Thus, in summary, the NMOS network
implements Y as a sum-of-products, whereas the PMOS network implements the function Y
as a product-of-sums in the complemented variables.
Discussion: Note that the PMOS network in Fig. 7.26 could also be obtained from the NMOS
network by successive application of the series/parallel transformation rule. The NMOS network
consists of two parallel branches: transistor A and transistors B, C, and D. The PMOS network,
therefore, has two branches in series, one with transistor A and a second representing the
branch with B, C, and D. The second branch in the NMOS network is the series combination
of transistor B and a third branch consisting of the parallel combination of C and D. In the
PMOS network, this corresponds to transistor B being in parallel with the series combination
of transistors C and D. This process can be used to create the PMOS network from the NMOS
network, or vice versa. However, it can run into trouble when bridging branches are present, as
in Ex. 7.3.
Exercise: Draw another version of the circuit in Fig. 7.27.
Answer: The position of PMOS transistors C and D may be interchanged in Fig. 7.26 or
Fig. 7.27. Another possibility is to interchange the position of the NMOS transistors forming
the B(C + D) subnetwork.
DESIGN
EXAMPLE 7.3
COMPLEX CMOS GATE WITH A BRIDGING TRANSISTOR
In this example, we design a CMOS logic gate with the same logic function as NMOS design from Fig. 6.39 in Chapter 6. In this example, the logic gate contains a bridging transistor.
DESIGN Design the CMOS version of the gate in Fig. 6.39, Chapter 6, which implements the logic
SPECIFICATIONS function Y = AB + C E + AD E + C D B
SOLUTION Specifications and Known Information: Y = AB + C E + AD E + C D B or Y = AB +
C E + AD E + C D B. The NMOS network implementation of Y is exactly the same as that of
the NMOS gate in Fig. 6.39.
Unknowns: Topology of the PMOS network; W/L ratios of all the transistors
Approach: We have the NMOS network and need to construct the corresponding PMOS
network. Use the graphical method introduced in Ex. 7.2 to find the PMOS network. Once the
PMOS circuit topology is found, the transistor W/L values can be determined.
Assumptions: Use a symmetrical design based upon the reference inverter in Fig. 7.12.
490
Chapter 7
Complementary MOS (CMOS) Logic Design
+5 V
4
PMOS
network
2
Y = AB + CE + ADE + CDB
2
6
1
A
D
C
A
C
6
1
D
3
3
6
1
B
1
1
6
1
E
6
1
B
E
0
0
(a)
( b)
2
NMOS
5
A
A
C
C
5
4
D
3
1
2
4
D
2
6
B
B
E
E
6
0
(c)
(d)
Figure 7.28 (a) NMOS portion of CMOS gate. (b) Graph for NMOS network. (c) Construction of the
PMOS graph. (d) Resulting graph for the PMOS network.
Analysis: Figure 7.28(b) is the graph of the NMOS network. The corresponding graph for
the PMOS network is constructed in Fig. 7.28(c): new nodes 5 and 6 are added inside the
enclosed paths formed by arcs ACD and BED in Fig. 7.28(b), and nodes 2 and 4 are added
to represent the output and +5-V power supply. New arcs are added for each transistor. The
resulting CMOS gate design is given in Fig. 7.29. In this unusual case, the NMOS and PMOS
network topologies are identical. Transistor D is a bridging transistor in both networks. The
worst-case path in each network contains three devices in series, and all the transistors in
the CMOS gate are three times the size of the corresponding transistors in the reference
inverter.
Check of Results: A recheck of our work indicates that it is correct.
Discussion: For this case, it is not easy to check our work using the series/parallel transformations because of the bridging transistor in the network.
7.7
Minimum Size Gate Design and Performance
491
VDD
4
15
1
A
15
1
15
1
5
15
1
C
B
D
6
E
15
1
2
6
1
A
3
B
D
C
6
1
1
6
1
6
1
E
6
1
0
Figure 7.29 CMOS implementation of Y = AB + C E + AD E + C D B.
Exercise: Draw another version of the circuit in Fig. 7.29.
Answer: Either one or both of the NMOS and PMOS switching networks can be rearranged.
In the NMOS network, the positions of transistors A and B and transistors C and E can be
interchanged. Note that both of these changes must be done to retain the correct logic
function. In the PMOS network, the positions of transistors A and C and transistors B and
E can be interchanged. Again both sets of changes must occur together.
7.7 MINIMUM SIZE GATE DESIGN AND PERFORMANCE
Because there is one NMOS and one PMOS transistor for each logic input variable in static
CMOS, there is an area penalty in CMOS logic with respect to NMOS logic, that requires only
a single-load device regardless of the number of input variables. In addition, series paths in the
PMOS or NMOS switching networks require large devices in order to maintain logic delay. (See
Fig. 7.20.) However, in most logic designs, only the critical logic delay paths need to be scaled to
maintain maximum performance. If gate delay is not the primary concern, then considerable area
savings can be achieved if all transistors are made of minimum geometry. For example, the gate
of Fig. 7.26 is shown implemented with minimum size transistors in Fig. 7.30 (p. 492). Here, area
is being traded directly for increased logic delay. The total gate area for Fig. 7.30 is 16F 2 , where
F is the minimum feature size, whereas that of Fig. 7.26 is 66.5F 2 , an area four times larger.
492
Chapter 7
Complementary MOS (CMOS) Logic Design
+5 V
2
1
A
D
2
1
C
2
1
2
1
B
Y
2
1
B
2
1
A
2
1
C
D
2
1
(a)
VDD
Ground
Y
Polysilicon gate
A
PMOS graph
D
A
B
C
B
NMOS graph
B
C
A
C
D
D
Euler paths
Metal
PMOS devices
NMOS devices
p+
n+
n-well
(b)
Figure 7.30 (a) Minimum size implementation of a complex CMOS gate. (b) Layout of complex CMOS
gate in (a).
7.8 Dynamic Domino CMOS Logic
493
Let us estimate the worst-case propagation delay of this minimum size logic gate relative to
our reference inverter design. In the NMOS switching network, the worst-case path contains two
transistors in series, with W/L = 2/1, which is equivalent to the Ron of a 1/1 device as compared
to the reference inverter, in which W/L = 2/1. Thus, the high-to-low propagation delay for
this gate is twice that of the reference inverter τ P H L I : τ P H L = 2τ P H L I . The worst-case path in
the PMOS switching network contains three minimum geometry transistors in series, yielding an
effective W/L ratio of 2/3, versus 5/1 for the reference inverter. Thus the low-to-high propagation
delay is related to that of the reference inverter τ P L H I by
τP L H
5
= 12 τ P L H I = 7.5τ P L H I
3
The average propagation delay of the minimum size logic gate is
τp =
(τ P L H + τ P H L )
(2τ P L H I + 7.5τ P L H I )
9.5τ P L H I
=
=
= 4.75τ P L H I
2
2
2
remembering that the original inverter was a symmetrical design with
τP H L = τP L H
Thus, the propagation delay of the minimum size gate will be 4.75 times slower than the reference
inverter design when driving the same load capacitance and will be highly assymetrical.
Layout of the gate in Fig. 7.30 is shown implemented by two vertical linear arrays of transistors with common horizontal polysilicon gate stripes. The diffusions between various transistors
are interconnected on the metal level to create the desired circuit. This layout strategy requires
identification of a “Euler path” in the graphs of the PMOS and NMOS switching trees. The Euler
path connects all the transistors in the graph of the NMOS or PMOS network, but must only pass
through each transistor once and only once. The path may go through a given node more than
once. To create the layout in Fig. 7.30, the Euler paths in both the NMOS and PMOS networks
must have the same transistor order — in this case the paths have the common order ABCD.
7.8 DYNAMIC DOMINO CMOS LOGIC
Dynamic logic circuits were first developed as a means of reducing power in PMOS and NMOS
logic. Dynamic logic uses separate precharge and evaluation phases governed by a system clock
signal to eliminate the dc current path that exists in single-channel static logic gates. However, the
logical outputs are valid only during a portion of the evaluation phase of the clock. In addition,
static power represents only one component of power dissipation in high-speed systems, and
the power required to drive the clock signals that must connect to every dynamic logic gate can
be significant. The early PMOS and NMOS dynamic circuits used complicated two-phase and
four-phase clocking techniques. However, a more recently developed form of dynamic CMOS
logic is based on a single clock signal.
The circuit in Fig. 7.31 represents a general dynamic logic gate in a circuit family called
domino CMOS. Operation of the domino CMOS circuit begins with the clock signal in the low
state. M N C is off, which disables the current path to ground through the logic function block F.
The same clock signal turns on M PC , pulling node 4 high to VD D and forcing the inverter output
to be low.
When the clock signal goes high, the capacitance at node 4 is selectively discharged. If a
conducting path exists through the logic network F (that is, if F = 1), then node 4 is discharged
494
Chapter 7
Complementary MOS (CMOS) Logic Design
VDD
Clock
MPC
Z=F
4
Logic
function
F
Logic
inputs
Clock
3
Evaluate F
MNC
Evaluate F
Clock
Precharge
Precharge
t
Figure 7.31 Dynamic domino CMOS logic.
to zero, and the output of the inverter rises to a 1 level. If F = 0, no discharge path exists, the
voltage at node 4 remains high, and the output of the inverter remains at a 0.
Simulated waveforms for the single-input domino CMOS gate in Fig. 7.32(a) are shown in
Fig. 7.32(b) for the case of A = 1. After the clock goes high, the output rises following the delay
to discharge the capacitances at nodes 3 and 4 plus the delay through the inverter. The output
drops back to zero following the clock signal’s return to zero.
The inputs to a given domino CMOS gate, generated by other domino gates, make only
low-to-high transitions following the clock transition, and the functional evaluation during the
positive clock phase ripples through the gates like a series of dominos falling over — hence the
name domino logic. Figure 7.33 shows the ripple-through effect for the case of three domino
gates in series. Output O1 follows the rising edge of the clock and drives the input of O2 , and
output O3 responds to the change in O2 . Note that the outputs are all reset to zero at the same
time, following the falling edge of the clock.
External inputs that are not from other domino gates should remain stable during the evaluation phase of the clock. As with most CMOS circuits, power dissipation is set by the dynamic
power consumed in charging and discharging the capacitances at the various nodes. A major
advantage of the domino CMOS circuit is the requirement for only two PMOS transistors per
logic stage, no matter how complex the function F.
The observant reader has probably noticed that domino CMOS gates do not form a complete
logic family because only true output functions are available. However, this does not represent
a problem in system designs in which a register transfer structure exists, as in Fig. 7.34. In this
logic structure, data are stored in a static register (1), which can be designed to produce both true
and complemented data values at its outputs. Domino CMOS performs the combinational logic
functions on the positive phase of the clock signal, and the results of the logic operations are
clocked into register (2) on the falling edge of the clock signal.
Exercise: (a) Draw the circuit schematic for a domino CMOS gate for Z = AB + C.
(b) What power is required in a domino CMOS clock driver circuit that drives a 50-pF load
at 10 MHz if VD D = 5 V?
Answer: 6.25 mW
7.8 Dynamic Domino CMOS Logic
+3 V
MPC
Z=A
4
A
CL
3
MNC
Clock
(a)
4.0 V
Voltage
Clock
2.0 V
Output
0V
0
10 ns
20 ns
30 ns
40 ns
50 ns
Time
(b)
Figure 7.32 (a) Domino CMOS gate with a single input. (b) Waveforms for the clocked
domino circuit.
4.0 V
Voltage
Clock
O1
2.0 V
O2
O3
0V
0
10 ns
20 ns
30 ns
40 ns
Time
Figure 7.33 Outputs of three cascaded domino CMOS gates.
50 ns
495
496
Chapter 7
Complementary MOS (CMOS) Logic Design
DN
DO
R
e
g
i
s
t
e
r
QN
DN
DN
DO
CMOS
domino
logic
QO
DO
(1)
R
e
g
i
s
t
e
r
QN
QN
QO
(2) QO
Clock
Figure 7.34 Section of logic in a complex digital system.
7.9 CASCADE BUFFERS
In today’s high-density ICs, the input capacitance of a logic gate may be in the range of only
10 to 100 fF, and the propagation delay of a CMOS gate driving such a small load capacitance
can be well below 1 ns. However, there are many cases in which a much higher load capacitance
is encountered. For example, the wordlines in RAMs and ROMs represent a relatively large
capacitance; long interconnection lines and internal data buses in microprocessors also represent
significant load capacitances. In addition, the circuits that must drive off-chip data buses may have
to drive capacitances as large as 10 to 50 pF, a capacitance 1000 times larger than the internal
load capacitance. We know that the propagation delay of a CMOS gate is proportional to its load
capacitance, so if a minimum size inverter is used to drive such a large capacitance, then the delay
will be extremely long. If the inverter is scaled up in size to reduce its own delay, then its input
capacitance increases, slowing down the propagation delay of the previous stage.
7.9.1 Cascade Buffer Delay Model
It has been shown [4, 5] that a minimum overall delay can be achieved by using an optimized
cascade of several inverter stages, as depicted in Fig. 7.35. The W/L ratios of the transistors
are increased by the taper factor β in each successive inverter stage in order to drive the load
capacitance. In this analysis, the load capacitance is then C L = β N Co , in which Co is the input
capacitance of the normal reference inverter stage and N is the number of stages in the cascade
buffer. The analysis is simplified by assuming that the total capacitance at a given node is
dominated by the input capacitance of the next inverter. Thus, the capacitive load on the first
inverter is βCo , the load on the second inverter is β 2 Co , and so on. If the propagation delay of the
unit size inverter driving a load capacitance of Co is τo , then the delay of each inverter stage will
be βτo , and the total propagation delay of the N -stage buffer will be
τ B = Nβτo
1
CO
β
β2
β CO
β 2CO
(7.27)
β Ν−1
CL = β Ν CO
Figure 7.35 Cascade buffer for driving large capacitive loads.
7.9
Cascade Buffers
497
in which
βN =
CL
Co
(7.28)
Solving Eq. (7.28) for β yields
β=
CL
Co
1/N
(7.29)
and substituting this result into Eq. (7.27) yields an expression for the total propagation delay of
the buffer:
1/N
CL
τB = N
τo
(7.30)
Co
In Eq. (7.30), N increases as additional stages are added to the buffer, but the value of the
capacitance ratio term decreases with increasing N . The opposite behavior of these two factors
leads to the existence of an optimum value of N for a given capacitance ratio.
7.9.2 Optimum Number of Stages
The number of stages that minimizes the overall buffer delay can be found by differentiating
Eq. (7.30) with respect to N and setting the derivative equal to zero. The optimization can be
simplified by taking logarithms of both sides of Eq. (7.30) before taking the derivative:
1
CL
ln τ B = ln N + ln
+ ln τo
(7.31)
N
Co
Taking the derivative with respect to N yields:
d ln τ B
1
1
=
− 2 ln
dN
N
N
CL
Co
(7.32)
and setting Eq. (7.32) equal to zero gives the optimum value of N :
CL
Nopt = ln
Co
(7.33)
Substituting Eq. (7.33) into (7.29) yields the optimum value of the taper factor βopt and the
optimum buffer delay τ Bopt :
βopt =
CL
Co
[1/ ln(C L /Co )]
=ε
and
τ Bopt = ln
CL
Co
ετo
(7.34)
The optimum value of the taper factor is equal to the natural base ε ∼
= 2.72.
DESIGN
EXAMPLE 7.4
CASCADE BUFFER DESIGN
In digital chip designs, such as microprocessors and memory chips, we often must design
circuits that must drive high-capacitance loads. This example designs a buffer to drive a
50-pF load.
498
Chapter 7
Complementary MOS (CMOS) Logic Design
DESIGN Design a cascade buffer to drive a load capacitance of 50 pF if Co = 50 fF. Find the overall
SPECIFICATIONS delay for the buffer design for a 3.3-V supply with VT N = 0.75 V and VT P = −0.75 V.
SOLUTION Specifications and Known Information: C L = 50 pF; technology has Co = 50 fF.
Unknowns: The number of stages N , taper factor β, and relative size of each inverter in the
cascade buffer; overall buffer delay
Approach: Select the number of stages N needed using Eq. (7.33). Calculate the taper factor
using the selected value of N . Scale the reference inverter using N .
Assumptions: The value of Co (50 fF) is known for the symmetrical reference inverter in
Fig. 7.12.
Analysis: The optimum value of N is Nopt = ln C L /Co = ln(1000) = 6.91, and the optimum
delay is τ Bopt = 6.91 × (2.72) × to = 18.8to . N must be an integer, but either N = 6 or N = 7
can be used because the delay minimum is quite broad, as illustrated by these numeric results.
Using these two values of N yields
N = 6:
τ B = 6(10001/6 )τo = 19.0τo
N = 7:
τ B = 7(10001/7 )τo = 18.8τo
Little speed is lost by using the smaller value of N . The choice between N = 6 and N = 7 will
usually be made based on buffer area. For N = 6, the taper factor β is found using Eq. (7.29):
1/N √
CL
50 pF 1/6
β=
=
= (1000)1/6 = 10 = 3.16
Co
50 fF
Each successive stage of the cascade buffer is 3.16 times larger than the preceding stage, and
the result appears in Fig. (7.36). The transistor sizes (NMOS, PMOS) for the six inverters are
(2/1, 5/1), (6.33/1, 15.8/1), (20/1, 50/1), (63.3/1, 158/1), (200/1, 500/1), and (633/1, 1580/1).
0
1
1
Co
2
3
4
5
6
3.16
10
31.6
100
316
3.16 Co
10 Co
31.6 Co
100 Co
316 Co
1000 Co
Figure 7.36 Optimum buffer design.
For N = 6, we already found τ B = 19.0τo , and we need the value of τo . For the symmetrical
inverter designs,
1
2C
VD D − VT N
τo ∼
−1 +
C ln 4
=
K n (VD D − VT N )
V D D + VL
2
2(50 fF)
3.3 − 0.75
1
τo ∼
ln
4
−
1
+
= 0.97 ns
=
2(25 A/V2 )(3.3 − 0.75)
3.3 + 0
2
and the estimated buffer delay is τ B = 18.4 ns.
Check of Results: A recheck of calculations indicates the work is correct. We now check the
overall buffer delay using SPICE.
7.9
Cascade Buffers
499
Computer-Aided Analysis: The output waveforms for the cascade buffer in Fig. 7.36 appear
below. The first inverter is driven by a pulse having a 25-ns width, a 50-ns period, and rise and
fall times of 2 ps. The propagation delay of the full buffer is 17.0 ns. This is slightly shorter than
our estimate because the delay of the first inverter is shortened by the fast rise and fall times of
the input signal. The delay between the output of inverters 1 and 6 should be 15.8τo = 15.3 ns,
and SPICE also yields an identical result.
+3.000 V
–v1
–v3
–v5
–v0
–v4
–v2
–v6
+2.000 V
+1.000 V
–v2
–v4
–v6
–v1
–v3
–v5
0
0
+10
+20
+30
Time (ns)
+40
+50
Discussion: The buffer optimization just discussed is based on a set of very simple assumptions
for the change in nodal capacitance with buffer size. Many refinements to this analysis have
been published in the literature, and those more complex analyses indicate that the optimum
tapering factor lies between 3 and 4. The results in Eqs. (7.29), (7.30), and (7.33) should be
used as an initial guide, with the final design determined using circuit simulation based on a
given set of device and technology parameters.
Exercise: Suppose we try to drive the 50-pF capacitance in Ex. 8.4 by adding only one
additional buffer stage, i.e., N = 2. What is the relative size of the buffer stage? What is the
overall delay?
Answers: 31.6, 63.2τ o
Exercise: Prove that z1/ ln z = ε.
Exercise: What would be the relative inverter sizes for the cascade buffer example if N
were chosen to be 7? Compare the total buffer area for N = 6 and N = 7.
Answers: 1, 2.68, 7.20, 19.3, 51.8, 139, 372; 462 times the unit inverter area versus 593
times
500
Chapter 7
Complementary MOS (CMOS) Logic Design
7.10 THE CMOS TRANSMISSION GATE
The CMOS transmission gate in Fig. 7.37 is a circuit useful in both analog and digital design.
The circuit consists of NMOS and PMOS transistors, with source and drain terminals connected
in parallel and gate terminals driven by opposite phase logic signals indicated by A and A. The
transmission gate is used so often that it is given the special circuit symbol shown in Fig. 7.37(c).
For A = 0, both transistors will be off, and the transmission gate represents an open circuit.
When the transmission gate is in the conducting state (A = 1), the input and output terminals
are connected together through the parallel combination of the on-resistances of the two transistors,
and the transmission gate represents a bidirectional resistive connection between the input and
output terminals. The individual on-resistances Ron p and Ronn , as well as the equivalent onresistance REQ , all vary as a function of the input voltage v I , as shown in Fig. 7.38. The value of
REQ is equal to the parallel combination of Ron p and Ronn :
REQ =
Ron p Ronn
Ron p + Ronn
(7.35)
In Fig. 7.38, the PMOS transistor is cut off (Ron p = ∞) for v I ≤ 1.36 V, and the NMOS transistor
is cut off for v I ≥ 3.64 V. For the parameters used in Fig. 7.38, the equivalent on-resistance is
always less than 20 k, but it can be made smaller by increasing the W/L ratios of the n- and
p-channel transistors.
Exercise: What W/L ratios are required in the transmission gate in Fig. 7.38 to ensure that
REQ ≤ 1 k if the W/L ratios of both transistors are the same?
Answer: W/L = 20/1
A
0V
A
5V
100
Ronn
NMOS
vO
0V
5V
vI
PMOS
A
A
5V
0V
(b) On
(a) Off
Ronp
vO
Resistance ( kΩ)
0V
5V
vI
80
60
40
20
A
REQ
0
vI
vO
–20
0
A
1
2
3
4
Input voltage (V)
5
6
(c)
Figure 7.38 On-resistance of a transmission gate,
Figure 7.37 CMOS transmission gate in (b) on state
and (a) off state. (c) Special circuit symbol for the
transmission gate.
including body effect (VT O N = 0.75 V, VT O P =
−0.75 V, γ = 0.5 V0.5 , 2φ F = 0.6 V, K p = 20 A/V2 ,
K n = 50 A/V2 ).
7.11 CMOS Latchup
501
7.11 CMOS LATCHUP
The basic CMOS structure has a potentially destructive failure mechanism called latchup that
was a major concern in early implementations and helped delay early adoption of the technology.
By the mid-1980s, technological solutions were developed that effectively surpress the latchup
phenomenon. However, it is important to understand the source of the problem that arises from
the complex nature of the integrated structure that produces parasitic bipolar transistors. These
bipolar transistors are not normally off, but can conduct under some transient fault conditions.
In the cross section of the CMOS structure in Fig. 7.39(a), a pnp transistor is formed by the
source region of the PMOS transistor, the n-well, and the p-type substrate, and an npn transistor
is formed by the source region of the NMOS transistor, the p-type substrate, and the n-well. The
physical structure connects the npn and pnp transistors together in the equivalent circuit shown in
Fig. 7.39(b). Rn and R p model the series resistances existing between the external power supply
connections and the internal base terminals of the bipolar transistors.
If the currents in Rn and R p in the circuit model in Fig. 7.39(b) are zero, then the base-emitter
voltages of both bipolar transistors are zero and both devices are off, and the total supply voltage
(VD D − VSS ) appears across the reverse-biased well-to-substrate junction that forms the collectorbase junction of the two parasitic bipolar transistors. However, if a current should develop in the
base of either the npn or the pnp transistor, latchup can be triggered and high currents can destroy
the structure. In the latchup state, the current is limited only by the external circuit components.
VSS (0 V)
B
S
p+
VDD (5 V)
vO
D
D
n+
n+
S
p+
p+
B
n+
n-well
npn transistor
Rn
Rp
pnp transistor
p-type substrate
(a)
RC
1
2
25 Ω
VDD
2 kΩ
Rn
VEB
iDD
VECSAT
iBP
RL
VDD
3
2 kΩ
iCP
ββN iBN
iBN
VCESAT
4
Rp
VBE
500 Ω
VSS
0
(b)
VEB
(c)
Figure 7.39 (a) CMOS structure with parasitic npn and pnp transistors identified. (b) Circuit including
shunting resistors Rn and R p for SPICE simulation. See text for description of R L . (c) Regenerative
structure formed by parasitic npn and pnp transistors.
Complementary MOS (CMOS) Logic Design
The problem can be more fully understood by referring to Fig. 7.39(c), in which Rn and R p
have been neglected for the moment. Suppose a base current i B N begins to flow in the base of the
npn transistor. This base current is amplified by the npn current gain β N and must be supplied
from the base of the pnp transistor. The pnp base current is then amplified further by the current
gain β P of the pnp transistor, yielding a collector current equal to
i C P = β P i B P = β P (β N i B N )
(7.36)
However, the pnp collector current i C P is also equal to the npn base current i B N . If the product
of the two current gains β P β N exceeds unity, then all the currents will grow without bound. This
situation is called latchup. Once the circuit has entered the latchup state, both transistors enter
their low impedance state, and the voltage across the structure collapses to one diode drop plus
one emitter collector voltage:
V = VE B + VCESAT = VB E + VECSAT
(7.37)
The shunting resistors Rn and R p shown in Fig. 7.39 actually play an important role in
determining the latchup conditions in a real CMOS structure. As mentioned before, latchup
would not occur in an ideal structure for which Rn = 0 = R p — modern CMOS technology uses
special substrates and processing to minimize the values of these two resistors.
The results of SPICE simulation of the behavior of the circuit in Fig. 7.39(b) for representative
circuit elements are presented in Fig. 7.40. Resistor R L is added to the circuit to provide a leakage
path across the collector-base junctions to initiate the latchup phenomenon in the simulation.
Prior to latchup in Fig. 7.40, all currents are very small, and the voltage V (2) at node 2 is
directly proportional to the input voltage VD D . At the point that latchup is triggered, the voltage
200 mA
External circuit
limited current
100 mA
iDD
Chapter 7
0A
Latchup trigger point
–100 mA
(a)
2.0 V
V(2)
502
0V
0V
1.0 V
2.0 V
3.0 V
VDD
4.0 V
5.0 V
6.0 V
(b)
Figure 7.40 SPICE simulation of latchup in the circuit of Fig. 8.31(a): (a) current from VD D , (b) voltage
at node 2.
7.11 CMOS Latchup
503
across the CMOS structure collapses to approximately 0.8 V, and the current increases abruptly
to (VD D − 0.8)/RC . The current level is limited only by the external circuit component values.
Large currents and power dissipation can rapidly destroy most CMOS structures.
Under normal operating conditions, latchup does not occur. However, if a fault or transient
occurs that causes one of the source or drain diffusions to momentarily exceed the power supply
voltage levels, then latchup can be triggered. Ionizing radiation or intense optical illumination are
two other possible sources of latchup initiation.
Note that this section actually introduced another form of modeling. Figure 7.39(a) is a
cross section of a complex three-dimensional distributed structure, whereas Figs. 7.39(b) and
7.39(c) are attempts to represent or model this complex structure using a simplified network
of discrete transistors and resistors. Note too that Fig.7.39(b) is only a crude model of the real
situation, so significant deviations between model predictions and actual measurements should
not be surprising. It is easy to forget that circuit schematics generally represent only idealized
models for the behavior of highly complex circuits.
ELECTRONICS IN ACTION
CMOS–The Enabler for Handheld Technologies
Starting with science fiction stories of the 1940s, moving on to space-going movies of the
50s and 60s, and eventually finding its way into the Star Trek voyages, powerful handheld
sensing, computing, and communication technologies have been a dream of many an author.
Enabling those dreams has also been the goal of many microelectronic circuit designers in the
last 30 years. The beginnings of the integrated circuit era in the 1960s gave us a peek at the
possibilities, but the realization was still elusive due to a lack of functional density and power
consumption too high to enable battery powered operation.
In the1980s, CMOS technologies became widely available. Finally, we had a technology
that promised to combine high computational power and low power consumption in a way that
would lead to the handheld devices envisioned by authors years ago. As CMOS transistors
continued to be scaled to smaller and smaller sizes during the 1990s, handheld devices such as
cell phones, GPS receivers, and PDAs were introduced and then rapidly improved from year
to year.
Memory
Battery
Power
Management
Display
Backlight
CPU
IrDA
Bluetooth
(a) Handheld Personal
Digital Assistant (PDA)
(b) PDA Block Diagram
I/O
Controller
Serial I/O
504
Chapter 7
Complementary MOS (CMOS) Logic Design
PDAs are complex devices and typically include a central processing unit (CPU), memory, input/output circuits, power management, touchscreen, liquid-crystal display, and various
optional modules such as Bluetooth radio, infrared, and other interfaces. In total, a PDA will
typically contain several million transistors. The extremely low standby current of CMOS logic
enables the designer to build complex capabilities that only dissipate significant power when
activated.
Throughout this chapter, we have assumed that a CMOS transistor has zero current when
the gate-source voltage is less than the threshold voltage. This property is responsible for
the extremely low standby-power dissipation of CMOS logic. However, in practice the current is not exactly zero, a small sub-threshold current (approximately 10−11 – 10−9 amps)
flows when the device is OFF (See Fig. 4.44). This would seem to be an insignificant current,
but when multiplied by gate counts of several million, it can add up to a sizable limitation on battery lifetime. Modern sub 100 nm gate-length processes have such a large subthreshold leakage current that designers are being forced to invent new logic forms to reduce
the leakage currents, and processes are being modified to incorporate multiple thresholds to
better control the leakage current power dissipation. These new CMOS logic forms build
on the logic topologies developed in this chapter and are a topic of advanced VLSI design
courses.
SUMMARY
•
CMOS inverters: In this chapter, we discussed the design of CMOS logic circuits beginning
with the design of a reference inverter. The shape of the voltage transfer characteristic (VTC)
of the CMOS inverter is almost independent of power supply voltage, and the noise margins
of a symmetrical inverter can approach one-half the power supply voltage. The design of
the W/L ratios of the transistors in a CMOS gate is determined primarily by the desired
propagation delay τ P , which is related directly to the device parameters K n , VT N , K p , and
VT P , and the total load capacitance C.
•
CMOS logic gates: In CMOS logic, each gate contains both an NMOS and a PMOS switching network, and every logical input is connected to at least one NMOS and one PMOS
transistor. NAND gates, NOR gates, and complex CMOS logic gates can all be designed
using the reference inverter concept, similar to that introduced in Chapter 6. As for NMOS
circuitry, complex CMOS gates can directly implement Boolean logic equations expressed
in a sum-of-products form. In contrast to NMOS logic, which has highly asymmetric rise
and fall times, symmetrical inverters in which t f and tr are equal can easily be designed in
CMOS, although there can be a significant area penalty. A number of examples of styles
for the layout of CMOS inverters and more complex logic gates were presented.
•
Body effect: Body effect has a smaller influence on CMOS design than on NMOS design
because the source-bulk voltages of all the transistors in a CMOS gate become zero in the
steady state. However, the source-bulk voltages are nonzero during switching transients,
and the body effect degrades the rise and fall times and propagation delays of CMOS logic.
•
Dynamic power dissipation and power delay product: Except for very low power applications, CMOS power dissipation is determined by the energy required to charge and
discharge the effective load capacitance at the desired switching frequency. A simple expression for the power-delay product of CMOS was developed. For a given capacitive load,
the power and delay of the CMOS gate may be scaled up or down by simply modifying
the W/L ratios of the NMOS and PMOS transistors.
Summary
•
Static power dissipation: For low-power applications, particularly where battery life is
important, leakage current from the reverse-biased wells and drain-substrate junctions can
become an important source of power dissipation. This leakage current actually places a
lower bound on the power required to operate a CMOS circuit.
•
“Short circuit” current: During switching of the CMOS logic gate, a pulse of current
occurs between the positive and negative power supplies. This current causes an additional
component of power dissipation in the CMOS gate that can be as much as 20 to 30 percent
of the dissipation resulting from charging and discharging the load capacitance.
•
Cascade buffers: High capacitance loads are often encountered in logic design, and cascade
buffers are used to minimize the propagation delay associated with driving these large
capacitance values. Cascade buffers are widely used in wordline drivers and for on-chip
and off-chip bus driver applications.
•
Dynamic logic: Dynamic logic circuits, such as domino CMOS, operate on two phases — a
precharge phase and a logic evaluation phase. This circuit family requires only a single
PMOS transistor in each gate (plus an output inverter), thus reducing the large silicon area
overhead traditionally associated with static CMOS logic circuits. Dynamic circuits are
also used to reduce power consumption in many applications.
•
The CMOS transmission gate: A new bidirectional circuit element, the CMOS transmission
gate that utilizes the parallel connection of an NMOS and a PMOS transistor was introduced.
When the transmission gate is on, it provides a low-resistance connection between its input
and output terminals over the entire input voltage range. We often find the transmission
gate used in circuit implementations of both the D latch and the master-slave D flip-flop.
(See Chapter 8).
•
Latchup: An important potential failure mechanism in CMOS is the phenomenon called
latchup, which is caused by the existence of parasitic npn and pnp bipolar transistors in the
CMOS structure. A lumped circuit model for latchup was developed and used to simulate
the latchup behavior of a CMOS inverter. Special substrates and IC processing are used to
minimize the possibility of latchup in modern CMOS technologies.
KEY TERMS
Cascade buffer
CMOS transmission gate
CMOS reference inverter
Complementary MOS (CMOS)
Complex logic gate
Domino CMOS
Dynamic logic
Euler path
Evaluation phase
Fall time
Latchup
NAND gate
NOR gate
On-resistance
Parasitic bipolar transistors
Power-delay product
Precharge phase
Propagation delay
Rise time
Symmetrical CMOS inverter
Taper factor
Transmission gate
505
506
Chapter 7
Complementary MOS (CMOS) Logic Design
REFERENCES
1. F. M. Wanlass and C. T. Sah, “Nanowatt logic using field-effect metal-oxide-semiconductor
triodes,” IEEE International Solid-State Circuits Conference Digest, vol. VI, pp. 32–33,
February 1963.
2. J. D. Meindl and J. A. Davis, “The fundamental limit on binary switching energy for terascale
integration (TSI),” IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1515–1516,
October 2000.
3. R. M. Swanson and J. D. Meindl, “Ion-implanted complementary MOS transistors in lowvoltage circuits,” IEEE Journal of Solid-State Circuits, vol. SC-7, no. 2, pp. 146–153, April
1972.
4. H. C. Lin and L. W. Linholm, “An optimized output stage for MOS integrated circuits,” IEEE
Journal of Solid-State Circuits, vol. 10, pp. 106–109, April 1975.
5. R. C. Jaeger, “Comments on An optimized output stage for MOS integrated circuits,” IEEE
Journal of Solid-State Circuits, vol. 10, pp. 185–186, June 1975.
PROBLEMS
Use K n = 25 A/V2 , K p = 10 A/V2 , VT N = 1 V,
and VT P = −1 V unless otherwise indicated. For
simulation purposes, use the values in Appendix B.
7.1 CMOS Inverter Technology
7.1. Calculate the values of K n and K p for NMOS
and PMOS transistors with a gate oxide thickness of 160 Å. Assume that µn = 500 cm2 /V · s,
µ p = 200 cm2 /V · s, and the relative permittivity
of the gate oxide is 3.9. (ε0 = 8.854 × 10−14 F/cm)
7.2. Draw a cross section similar to that in Fig. 7.1 for a
CMOS process that uses a p-well instead of an nwell. Show the connections for a CMOS inverter,
and draw an annotated version of the corresponding circuit schematic. (Hint: Start with an n-type
substrate and interchange all the n- and p-type
regions.)
∗
7.3. (a) The n-well in a CMOS process covers an area of
1 cm × 0.5 cm, and the junction saturation current
density is 500 pA/cm2 . What is the total leakage
current of the reverse-biased well? (b) Suppose the
drain and source regions of the NMOS and PMOS
transistors are 4 m × 10 m, and the saturation
current density of the junctions is 100 pA/cm2 . If
the chip has 5 million inverters, what is the total leakage current due to the reverse-biased junctions when v O = 5 V? Assume VD D = 5 V and
VSS = 0 V. (c) When v O = 0 V?
∗
7.4. A particular interconnection between two logic
gates in an IC chip runs one-half the distance across
a 5-mm-wide die. If the line is 2 m wide and the
7.5.
7.6.
7.7.
7.8.
oxide (εr = 3.9, ε0 = 8.854 × 10−14 F/cm) beneath
the line is 1 m thick, what is the total capacitance
of this line, assuming that the capacitance is three
times that predicted by the parallel plate capacitance formula. Assume that the silicon beneath
the oxide represents a conducting ground plane.
The CMOS inverter in Fig. 7.41 has VD D = 3.3 V
and VSS = 0 V. What are the values of VH and VL
for this inverter? (b) Repeat for VD D = 2.5 V.
The CMOS inverter in Fig. 7.41 has VD D = 3.3 V,
VSS = 0 V, (W/L) N = 4/1, and (W/L) P = 10/1.
What are the values of VH and VL for this inverter?
(b) Repeat for (W/L) N = 4/1 and (W/L) P = 4/1.
The CMOS inverter in Fig. 7.41 has VD D = 2.5 V,
VSS = 0 V, (W/L) N = 4/1, and (W/L) P = 10/1.
What are the values of VH and VL for this
inverter? (b) Repeat for (W/L) N = 6/1 and
(W/L) P = 15/1.
The CMOS inverter in Fig. 7.41 has
VD D = 3.3 V and VSS = 0 V. If VT N = 0.75 V and
VDD
MP
vI
vO
MN
–VSS
Figure 7.41
Problems
507
current of 1.5 mA and maintain VL = 0.6 V. When
VT P = −0.75 V, what are the regions of operation
v O = VH , the CMOS inverter must source a current
of the transistors for (a) VI = VL ? (b) VI = VH ?
of 60 A and maintain VH = 2.4 V. What are the
(c) VI = VO = 1.65 V?
minimum W/L ratios of the NMOS and PMOS
7.9. The CMOS inverter in Fig. 7.41 has VD D = 2.5 V
transistors required to meet these specifications?
and VSS = 0 V. If VT N = 0.60 V and VT P =
Assume VD D = 5 V.
−0.60 V, what are the regions of operation of
7.16. The outputs of two CMOS inverters are accidenthe transistors for (a) VI = VL ? (b) VI = VH ?
tally tied together, as shown in Fig. 7.43. What
(c) VI = VO = 1.25 V?
is the voltage at the common output node if the
7.10. (a) The CMOS inverter in Fig. 7.41 with
NMOS and PMOS transistors have W/L ratios of
(W/L) N = 20/1 and (W/L) P = 50/1 is operat20/1
and 40/1, respectively? What is the current
ing with VD D = 0 V and −VSS = −5.2 V. What
in
the
circuit?
are VL and VH ? (b) If (W/L) N = 10/1 and
(W/L) P = 10/1?
+5 V
+5 V
7.11. (a) Calculate the voltage at which v O = v I for
I
a CMOS inverter with K n = K p . (Hint: Always
remember that i D N = i D P .) Use VD D = 5 V,
MP1
MP2
VT N = 1 V, VT P = −1 V. (b) What is the current I D D from the power supply for v O = VI if 0 V
5V
(W/L) N = 2/1? (c) Repeat the calculation in (a)
MN1
MN2
for a CMOS inverter with K n = 2.5K p . (d) What is
the current I D D from the power supply for v O = VI
if (W/L) N = 2/1?
7.12. (a) Repeat Prob. 7.11 for VD D = 3.3 V, VT N =
Figure 7.43
0.75 V, and VT P = −0.75 V. (b) Repeat Prob.
7.11 for VD D = 2.5 V, VT N = 0.60 V, and
7.17. What are the noise margins of a minimum size
VT P = −0.60 V.
CMOS inverter in which both W/L ratios are 2/1
and VD D = 5 V and VT N = −VT P = 1 V?
7.2 Static Characteristics of the CMOS Inverter
7.18.
What are the noise margins for a symmetrical
7.13. Simulate the VTC for a CMOS inverter with
CMOS inverter operating with VD D = 3.3 V and
K n = 2.5K p . Find the input voltage for which
VT N = −VT P = 0.75 V? (b) Repeat for a CMOS
v O = v I and compare to the value calculated by
inverter
having (W/L) N = (W/L) P operating
hand.
with VD D = 3.3 V and VT N = −VT P = 0.75 V?
7.14. The CMOS gate in Fig. 7.42 is called pseudo7.19. Use SPICE to plot the VTC for a CMOS
NMOS. Find VH and VL for this gate.
inverter with (W/L) N = 2/1, (W/L) P = 5/1,
+5 V
VD D = 3.3 V, VSS = 0 V, VT N = 0.75 V, and VT P =
−0.75 V. Repeat if the threshold voltages
are mismatched with values VT N = 0.85 V and
MP 1
1
VT P = 0.65 V. Repeat for (W/L) N = 2/1 and
(W/L) P = 4/1 with the original threshold voltvO
ages. Plot the three curves on one graph.
vI
MN
4
1
Figure 7.42
∗∗
7.15. A CMOS inverter is to be designed to drive a single
TTL inverter (which will be studied in Chapter 9).
When v O = VL , the CMOS inverter must sink a
7.20. (a) Plot a graph of the noise margins of the CMOS
inverter (similar to Fig. 7.9) for VD D = 3.3 V,
VT N = 0.75 V, and VT P = −0.75 V. (b) Repeat
Prob. 7.11 for VD D = 2.5 V, VT N = 0.60 V, and
VT P = −0.60 V.
7.3 Dynamic Behavior of the CMOS Inverter
7.21. What are the rise time, fall time, and average propagation delay for a symmetrical CMOS inverter
508
Chapter 7
Complementary MOS (CMOS) Logic Design
with (W/L) N = 2/1, (W/L) P = 5/1, VD D = 5 V,
and C = 0.25 pF?
7.22. What are the rise time, fall time, and average propagation delay for a minimum size CMOS inverter
in which both W/L ratios are 2/1? Assume a load
capacitance of 0.5 pF and VD D = 5 V.
7.23. What are the rise time, fall time, and average propagation delay for a symmetrical CMOS inverter
with (W/L) N = 2/1, (W/L) P = 5/1, C = 0.20 pF,
VD D = 3.3 V, VT N = 0.75 V, and VT P = −0.75 V?
7.24. What are the rise time, fall time, and average propagation delay for a symmetrical CMOS inverter
with (W/L) N = 2/1, (W/L) P = 5/1, C = 0.15 pF,
VD D = 2.5 V, VT N = 0.60 V, and VT P = −0.60 V?
7.25. What are the sizes of the transistors in the CMOS
inverter if it must drive a 1-pF capacitance with
an average propagation delay of 3 ns? Design the
inverter for equal rise and fall times. Use VD D =
5 V, VT N = 1 V, VT P = −1 V.
chain, and compare your results to the formulas
developed in the text. (c) Discuss the differences
between the results in (a) and (b).
7.4 Power Dissipation and Power Delay Product
in CMOS
7.31. A certain packaged IC chip can dissipate 2 W. Suppose we have a CMOS IC design that must fit on
one chip and requires 1 million logic gates. What is
the average power that can be dissipated by each
logic gate on the chip? If the average gate must
switch at 5 MHz, what is the maximum capacitive load on a gate for VD D = 5 V? For VD D =
3.3 V?
7.32. A high-performance CMOS microprocessor design requires 5 million logic gates and will be
placed in a package that can dissipate 20 W.
(a) What is the average power that can be dissipated by each logic gate on the chip? (b) If a supply voltage of 3.3 V is used, what is the average
current that must be supplied to the chip?
7.33. (a) The n-well in a CMOS process covers an area
of 5 mm × 10 mm, and the junctions saturation
current density of the junction is 400 pA/cm2 .
What is the total leakage current of the reversebiased well? (b) Suppose the drain and source regions of the NMOS and PMOS transistors are each
1 m × 2.5 m in size, and the saturation current
density of the junctions is 150 pA/cm2 . If the chip
has 75 million inverters, what is the total leakage
current when v O = 3.3 V? Assume VD D = 3.3 V.
(b) Repeat for v O = 0 V?
7.34. A high-speed CMOS microprocessor has a 64-bit
address bus and performs a memory access every
10 ns. Assume that all address bits change during every memory access and that each bus line
represents a load of 25 pF. (a) How much power
is being dissipated by the circuits that are driving
these signals if the power supply is 5 V? (b) Repeat
for 3.3 V.
7.26. Design a symmetrical CMOS reference inverter to
provide a delay of 1 ns when driving a 10-pF load.
(a) Assume VD D = 5 V. (b) Assume VD D = 3.3 V
and VT N = −VT P = 0.75 V.
7.27. Design a symmetrical CMOS reference inverter
to provide a propagation delay of 400 ps for
a load capacitance of 100 fF. Use VD D = 2.5 V,
VT N = 0.60 V, and VT P = −0.60 V.
7.28. Design a symmetrical CMOS reference inverter
to provide a propagation delay of 200 ps for
a load capacitance of 100 fF. Use VD D = 1.5 V,
VT N = 0.50 V, and VT P = −0.50 V.
∗
7.29. Use SPICE to determine the characteristics of the
CMOS inverter for the design given in Fig. 7.12 if
C = 100 fF. (a) Simulate the voltage transfer function. (b) Determine tr , t f , τ P H L , and τ P L H for this
inverter with a square wave input. What must be
the total effective load capacitance C based on the
propagation delay formula developed in the text?
∗∗
7.30. Use SPICE to simulate the behavior of a chain
of five CMOS inverters similar to those in
Fig. 7.13(b). The input to the first inverter should
be a square wave with 0.1-ns rise and fall times and
a period of 100 ns. (a) Calculate tr , t f , τ P H L , and
τ P L H using the input and output waveforms from
the first inverter in the chain and compare your results to the formulas developed in the text. (b) Determine tr , t f , τ P H L , and τ P L H from the waveforms
at the input and output of the fourth inverter in the
∗
7.35. (a) A CMOS inverter has (W/L) N = 20/1,
(W/L) P = 20/1, and VD D = 5 V. What is the peak
current in the logic gate and at what input voltage
does it occur? (b) Repeat for VD D = 3.3 V.
∗
7.36. (a) A CMOS inverter has (W/L) N = 2/1,
(W/L) P = 5/1, and VD D = 3.3 V. Assume VT N =
−VT P = 0.7 V. What is the peak current in the
logic gate and at what input voltage does it occur?
(b) Repeat for VD D = 2.0 V.
Problems
7.37. What is the power-delay product for the inverter in
Prob. 7.21? How much power does the inverter dissipate if it is switching at a frequency of 100 MHz?
7.38. (a) What is the power-delay product for the inverter
in Prob. 7.23? (b) Estimate the maximum switching frequency for this inverter. (c) How much
power does the inverter dissipate if it is switching at the frequency found in (b)?
7.39. (a) What is the power-delay product for the inverter
in Prob. 7.24? (b) Estimate the maximum switching frequency for this inverter. (c) How much
power does the inverter dissipate if it is switching at the frequency found in (b)?
and fall times and a period of 40 ns. (a) Determine tr , t f , τ P H L , and τ P L H from the waveforms
at the input and output of the fourth inverter in
the chain, and compare your results to the formulas developed in the text. (b) Repeat the simulation for (W/L) P = (W/L) N = 2/1, and compare
the results to those obtained in (a).
7.5 CMOS NOR and NAND Gates
7.45. (a) Draw the circuit schematic for a four-input
NOR gate. What are the W/L ratios of the transistors based on the reference inverter design in
Fig. 7.21? (b) What should be the W/L ratios if the
NOR gate must drive twice the load capacitance
with the same delay as the reference inverter?
7.40. Plot the power-delay characteristic for the CMOS
inverter family based on an inverter design in
which (W/L) N = (W/L) P . Assume the load capacitance C = 0.2 pF. Use VD D = 5 V and vary the
power by changing the W/L ratios.
∗∗
∗∗
7.46. (a) Draw the circuit schematic for a four-input
NAND gate. What are the W/L ratios of the transistors based on the reference inverter design in
Fig. 7.23? (b) What should be the W/L ratios
if the NOR gate must drive three times the load
capacitance with the same delay as the reference
inverter?
7.41. Ideal constant-electric-field scaling of a MOS
technology reduces all the dimensions and voltages by the same factor α. Assume that the capacitor C in Eq. (7.26) is proportional to the total gate
capacitance of the MOS transistor: C = Cox
W L,
and show that constant-field scaling results in a
reduction of the PDP by a factor of α 3 .
7.47. Draw the circuit schematic of a three-input NOR
gate. Suppose the PMOS transistors are chosen to
have (W/L) P = 2/1. What are the corresponding
W/L ratios of the NMOS devices, if the gate is to
have symmetrical delay characteristics?
7.42. For many years, MOS technology was scaled by
reducing all the dimensions by the same factor α,
but keeping the voltages constant. Assume that
the capacitor C in Eq. (7.26) is proportional to
the total gate capacitance of the MOS transistor:
C = Cox
W L, and show that this geometry scaling
results in a reduction of the PDP by a factor of α.
∗∗
7.43. Use SPICE to simulate the behavior of a chain of
five CMOS inverters with the same design as in
Fig. 7.12 with C = 0.25 pF. The input to the first
inverter should be a square wave with 0.1-ns rise
and fall times and a period of 30 ns. (a) Calculate
tr , t f , τ P H L , and τ P L H using the input and output
waveforms from the first inverter in the chain, and
compare your results to the formulas developed in
the text. (b) Determine tr , t f , τ P H L , and τ P L H from
the waveforms at the input and output of the fourth
inverter in the chain, and compare your results to
the formulas developed in the text. (c) Discuss the
differences between the results in (a) and (b).
∗∗
7.44. Use SPICE to simulate the behavior of a chain of
five CMOS inverters with the same design as in
Fig. 7.12 with C = 1 pF. The input to the first inverter should be a square wave with 0.1-ns rise
509
7.48. Draw the circuit schematic of a four-input NOR
gate. Suppose the PMOS transistors are chosen to
have (W/L) P = 2/1. What are the corresponding
W/L ratios of the NMOS devices, if the gate is to
have symmetrical delay characteristics?
7.49. Draw the circuit schematic of a three-input NAND
gate. Suppose the NMOS transistors are chosen to
have (W/L) N = 2/1. What are the corresponding
W/L ratios of the PMOS devices, if the gate is to
have symmetrical delay characteristics?
7.50. Draw the circuit schematic of a four-input NAND
gate. Suppose the NMOS transistors are chosen to
have (W/L) N = 2/1. What are the corresponding
W/L ratios of the PMOS devices, if the gate is to
have symmetrical delay characteristics?
7.51. Design a circuit to multiply two one-bit numbers.
(Hint: Construct a truth table for output bit M
based on two inputs A and B.) Choose the W/L
ratios based on the inverter in Fig. 7.12.
∗∗
7.52. Use SPICE to determine the characteristics of the
two-input CMOS NOR gate given in Fig. 7.19
with a load capacitance of 1 pF. Assume that γ = 0
510
Chapter 7
Complementary MOS (CMOS) Logic Design
for all transistors. (a) Simulate the voltage transfer
function by varying the voltage at input A with the
voltage at input B fixed at 5 V. (b) Repeat the simulation in (a) but now vary the voltage at input B
with the voltage at input A fixed at 5 V. Plot the
results from (a) and (b) and note any differences.
(c) Determine tr , t f , τ P H L , and τ P L H for this inverter with a square wave input at input A with the
voltage at input B fixed at 5 V. (d) Determine tr ,
t f , τ P H L , and τ P L H for this inverter with a square
wave input at input B with the voltage at input A
fixed at 5 V. (e) Compare the results from (c) and
(d). (f) Determine tr , t f , τ P H L , and τ P L H for this
inverter with a single square wave input applied to
both inputs A and B. Compare the results to those
in (c) and (d).
∗∗
7.53. Repeat (a) and (b), Prob. 7.52, using the nonzero
values for the parameter γ from the device parameter tables.
∗∗
7.54. Use SPICE to determine the characteristics of the
two-input CMOS NAND gate given in Fig. 7.23
with a load capacitance of 1 pF. Assume that γ = 0
for all transistors. (a) Simulate the voltage transfer
function by varying the voltage at input A with the
voltage at input B fixed at 5 V. (b) Repeat the simulation in (a) but now vary the voltage at input B
with the voltage at input A fixed at 5 V. Plot the
results from (a) and (b) and note any differences.
(c) Determine tr , t f , τ P H L , and τ P L H for this inverter with a square wave input at input A with the
voltage at input B fixed at 5 V. (d) Determine tr ,
t f , τ P H L , and τ P L H for this inverter with a square
wave input at input B with the voltage at input
A fixed at 5 V. (e) Compare the results from (c)
and (d). (f) Determine tr , t f , τ P H L , and τ P L H for
this inverter with a single square wave input applied to both inputs A and B. Compare the results
to those in (c) and (d).
∗∗
7.55. Repeat (a) and (b), Prob. 7.54, using the nonzero
values for the parameter γ from the device parameter tables.
+5 V
Logic
inputs
A to F
PMOS network
Y
A
B
C
D
E
F
Figure 7.44
7.59. (a) What is the logic function implemented by the
gate in Fig. 7.45? (b) Design the PMOS transistor network. Select the device sizes for both the
NMOS and PMOS transistors to give a delay of
approximately one-third the delay of the CMOS
reference inverter.
7.60. (a) What is the logic function implemented by the
gate in Fig. 7.46? (b) Design the PMOS transistor network. Select the device sizes for both the
NMOS and PMOS transistors to give a delay of
approximately one-half the delay of the CMOS
reference inverter.
7.56. What are the worst case rise and fall times and
average propagation delays of the CMOS gate in
Fig. 7.27 for a load capacitance of 1.25 pF?
7.61. (a) What is the logic function implemented by the
gate in Fig. 7.47? (b) Design the NMOS transistor network. Select the device sizes for both the
NMOS and PMOS transistors to give a delay similar to that of the CMOS reference inverter.
7.57. (a) How many transistors are needed to implement the CMOS gate in Fig. 7.30 using depletionmode NMOS? (b) Compare the total gate area of
the CMOS and NMOS designs if they are both
7.62. (a) What is the logic function implemented by the
gate in Fig. 7.48? (b) Design the NMOS transistor network. Select the device sizes for both the
NMOS and PMOS transistors to give a delay of
7.6 Design of Complex Gates in CMOS
∗∗
designed for a 10-ns average propagation delay
for a load capacitance of 1 pF.
7.58. (a) What is the logic function implemented by the
gate in Fig. 7.44? (b) Design the PMOS transistor network. Select the device sizes for both the
NMOS and PMOS transistors to give a delay similar to that of the CMOS reference inverter.
511
Problems
+5 V
+5 V
Logic
inputs
A to E
PMOS network
A
B
C
D
E
F
Y
A
B
C
D
Y
Logic
inputs
A to F
E
NMOS network
Figure 7.45
Figure 7.47
+5 V
Logic
inputs
A to G
+5 V
PMOS network
A
B
Y
C
D
C
F
E
E
B
D
F
Y
G
Logic
inputs
A to F
A
Figure 7.46
approximately one-third the delay of the CMOS
reference inverter.
7.63. Design a CMOS logic gate that implements the
logic function Y = ABC + D E, based on the
CMOS reference inverter. Select the transistor
sizes to give the same delay as that of the reference inverter if the load capacitance is the same as
that of the reference inverter.
NMOS network
Figure 7.48
7.64. Design a CMOS logic gate that implements the
logic function Y = A(B + C(D + E)), based on
the CMOS reference inverter. Select the transistor
sizes to give the same delay as that of the reference
inverter if the load capacitance is the same as that
of the reference inverter.
7.65. Design a CMOS logic gate that implements the
logic function Y = A(BC + D E) and is twice as
512
Chapter 7
Complementary MOS (CMOS) Logic Design
fast as the CMOS reference inverter when loaded
by a capacitance of 2C.
7.66. Design a CMOS logic gate that implements the
logic function Y = A(B + C D) + E and has the
same logic delay as the CMOS reference inverter
when driving a capacitance of 4C.
7.67. Design a complex gate implementation of a onebit half adder for which the sum bit is described by
S = X ⊕ Y , and the carry bit is given by C = A · B.
Choose the W/L ratios based on the reference inverter design in Fig. 7.12. Assume that true and
complement values of each variable are available
as inputs. (Note: Two gate designs are needed, one
for S and one for C.)
7.68. Design a complex gate implementation of a 1-bit
full adder for which the ith sum bit is described by
Si = X i ⊕Yi ⊕Ci−1 , and the ith carry bit is given by
Ci = X i ·Yi + X i ·Ci−1 +Yi ·Ci−1 . Choose the W/L
ratios based upon the reference inverter design in
Fig. 7.12. Assume that true and complement values of each variable are available as inputs. (Note:
Two gate designs are needed, one for Si and one
for Ci .)
7.69. Design a complex gate implementation of a 2-bit
parallel multiplier. [Note: The circuit should produce a 4-bit output (e.g., 112 ×112 = 10012 ), and a
separate circuit should be designed for each output
bit.] Choose the W/L ratios based on the inverter
in Fig. 7.12.
2/1 transistors and drives a load capacitance of
1 pF? Assume VD D = 5 V.
7.74. (a) Use a transient simulation in SPICE to find the
average propagation delay of a cascade connection of 10 minimum size inverters (W/L = 2/1)
in series. Assume each has a capacitive load C of
200 fF and VD D = 5 V. (b) Repeat for a cascade of
10 symmetrical reference inverters with the same
design as in Fig. 7.12, and compare the average
propagation delays.
7.8 Dynamic Domino CMOS Logic
7.75. (a) Draw the circuit schematic for a two-input
domino CMOS OR gate. Assume that true and
complement values of each variable are available as inputs. (b) Repeat for a two-input domino
CMOS AND gate.
7.76. (a) Draw the circuit schematic for a two-input
domino CMOS NOR gate. Assume that true and
complement values of each variable are available as inputs. (b) Repeat for a two-input domino
CMOS NAND gate.
7.77. (a) Draw the circuit schematic for a three-input
domino CMOS OR gate. Assume that true and
complement values of each variable are available
as inputs. (b) Repeat for a three-input domino
CMOS AND gate.
7.78. (a) Draw the circuit schematic for a three-input
domino CMOS NOR gate. Assume that true and
complement values of each variable are available
as inputs. (b) Repeat for a three-input domino
CMOS NAND gate.
7.7 Minimum Size Gate Design and Performance
7.70. The three-input NOR gate in Fig. 7.21 is implemented with transistors all having W/L = 2/1.
What is the propagation delay for this gate for a
load capacitance C = 400 fF? Assume VD D = 5 V.
What would be the delay of the reference inverter
for C = 400 fF?
7.71. The five-input NAND gate in Fig. 7.24 is implemented with transistors all having W/L = 2/1.
What is the propagation delay for this gate for a
load capacitance C = 180 fF? Assume VD D = 5 V.
What would be the delay of the reference inverter
for C = 180 fF?
7.72. What are the worst-case values of τ P H L and τ P L H
for the gate in Fig. 7.29 when it is implemented
using only 2/1 transistors and drives a load capacitance of 1 pF? Assume VD D = 5 V.
7.73. What is the worst-case value of τ P H L for the gate
in Fig. 7.44 when it is implemented using only
∗
7.79. (a) Suppose that inputs A0 , A1 , and A2 are all 0
in the domino CMOS gate in Fig. 7.49, and the
clock has just changed to the evaluate phase. If A0
now changes to a 1, what happens to the voltage
at node B if C1 = 2C2 ? (Hint: Charge sharing occurs between C1 & C2 .) (b) Now A1 changes to
a 1 — what happens to the voltage at node B if
C3 = C2 ? (c) If the output inverter is a symmetrical design, what is the minimum ratio of C1 /C2
(assume C3 = C2 ) for which the gate maintains a
valid output?
7.80. Draw the mirror image of the gate in Fig. 7.49
by replacing NMOS transistors with PMOS transistors and vice versa. Assume the logic inputs
remain the same and write an expression for the
logic function Z .
Problems
VDD
Clock
Z
B
C1
A0
A1
C2
A2
C3
Figure 7.49
7.81. Draw the circuit schematic for a domino CMOS
gate that implements the product of sums (POS)
logic function Z = (A + B)(C + D). Assume that
true and complement values of each variable are
available as inputs.
7.82. Draw the circuit schematic for a domino CMOS
gate that implements the sum of products (SOP)
logic function Z = AB + C D. Assume that true
and complement values of each variable are available as inputs.
7.83. Draw the circuit schematic for a domino CMOS
gate that implements the product-of-sums (POS)
logic function Z = (A + B)(C + D)(E + F).
Assume that true and complement values of
each variable are available as inputs. (Remember
DeMorgan’s theorem.)
7.84. Draw the circuit schematic for a domino CMOS
gate that implements the sum-of-products (SOP)
logic function Z = AB + C D + E F. Assume
that true and complement values of each variable
are available as inputs. (Remember DeMorgan’s
theorem.)
7.9 Cascade Buffers
7.85. Design an optimized cascade buffer to drive a load
capacitance of 4000Co . (a) What is the optimum
number of stages? (b) What are the relative sizes of
each inverter in the chain (see Fig. 7.36). (c) What
is the delay of the buffer in terms of τo ?
∗∗
7.86. Assume that the area of each inverter in a cascade
buffer is proportional to the taper factor β and that
the unit size inverter has as area Ao . Write an expression for the total area of an N -stage cascade
513
buffer. In the example in Fig. 7.36, buffers with
N = 6 and N = 7 have approximately the same delay. Compare the area of these two buffer designs
using your formula.
7.10 The CMOS Transmission Gate
7.87. (a) Calculate the on-resistance of an NMOS transistor with W/L = 20/1 for VG S = 5 V, VS B = 0 V,
and VDS = 0 V. (b) Calculate the on-resistance of a
PMOS transistor with W/L = 20/1 for VSG = 5 V,
VS B = 0 V, and VS D = 0 V. (c) What do we mean
when we say that a transistor is “on” even though
I D and VDS = 0?
7.88. A transmission gate is built with transistors that
have K p = K n . Show that REQ is independent of
the input voltage v I for input voltages for which
both transistors are on. For what range of v I is
REQ constant
√ if VT O N = 0.75 V, VT O P = − 0.75 V,
γ = 0.5 V, and 2φ F = 0.6 V?
7.89. A certain analog multiplexer application requires
the equivalent on-resistance REQ of a transmission gate to always be less than 250 .
What are the minimum values of W/L for the
NMOS and PMOS transistors
√ if VT O N = 0.75 V,
VT O P = −0.75 V, γ = 0.5 V, 2φ F = 0.6 V, K p =
10 A/V2 , and K n = 25 A/V2 ?
7.90. (a) What are the voltages at the nodes in
the pass-transistor networks in Fig. 7.50? For
NMOS
√ transistors, use VT O = 0.75 V, γ =
0.55 V, and 2φ F = 0.6 V. For PMOS transistors,
VT O = −0.75 V. (b) What would be the voltages
if transmission gates were used in place of each
transistor?
+5 V
+5 V
+5 V
0V
0V
0V
+5 V
(a)
+5 V
(b)
Figure 7.50
514
Chapter 7
Complementary MOS (CMOS) Logic Design
7.11 CMOS Latchup
7.91. Simulate CMOS latchup using the circuit in
Fig. 7.37(b) and plot graphs of the voltages at
nodes 2, 3, and 4 as well as the current supplied
by VD D . Discuss the behavior of the voltages and
identify important voltage levels, current levels,
and slopes on the graphs.
7.92. Repeat Prob. 7.91 if the values of Rn and R p are
reduced by a factor of 10.
7.93. Draw the cross section and equivalent circuit, similar to Fig. 7.39, for a p-well CMOS technology.
Additional Problems
7.94. (a) Verify Eq. (7.9). (b) Verify Eq. (7.13).
∗∗
τ
7.95. (a) Calculate the sensitivity SKpn = (K n /τ p )
(dτ p /d K n ) of the propagation delay τ p in
Eq. (7.19) to changes in K n . If the IC processing causes K n to be 25 percent below
its nominal value, what will be the percentage change in τ p ? (b) Calculate the sensitivity
τ
SVpT N = (VT N /τ p )(dτ p /d VT N ) of the propagation
delay τ p in Eq. (7.19) to changes in VT N . If the
IC processing causes VT N to change from a nominal value of 0.75 V to 0.85 V, what will be the
percentage change in τ p ?
7.96 Calculate logic delay versus input signal rise time
for a minimum size inverter with a load capacitance of 1 pF for 0.1 ns ≤ tr ≤ 5 ns.