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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 4, JULY 2006
Model-Based Generation of Low Distortion
Currents in Grid-Coupled PWM-Inverters
Using an LCL Output Filter
Bruno Bolsens, Student Member, IEEE, Karel De Brabandere, Student Member, IEEE,
Jeroen Van den Keybus, Student Member, IEEE, Johan Driesen, Member, IEEE, and
Ronnie Belmans, Senior Member, IEEE
Abstract—In this paper, a single phase inductance–capacitance–inductance (LCL) output stage for grid coupled inverters
is designed and built. An accurate model and observer of the
output filter and the distorted grid voltage are implemented. The
paper deals with the construction of a 14-state model, and the
feedback control loop to obtain adequate closed loop response.
Simulations indicate a good performance of the controller, with a
total harmonic current distortion (THD) below 1%. Experimental
results confirm simulations, and illustrate the correct operation of
the Kalman observer to estimate the distorted grid voltage (THD
3%). The observer only uses the inverter current measurement
as input. The output filter effectively reduces the pulsewidth
modulation harmonics in the grid current.
Index Terms—Active front end, active power filter, harmonics,
inverter current control, inductance–capacitance–inductance
(LCL) output stage design, low grid current distortion, power
quality, voltage source inverter (VSI).
I. INTRODUCTION
N THE literature on shunt active power filters, many topologies are found incorporating only an inductor as an output
filter between inverter and utility grid [1]–[4]. However, it has
been shown that such an output filter may not suffice to meet
standards on harmonics emission, such as IEEE 519 or IEC
61000-3-2 [5], mainly because of the high current ripple due
to the switching mode inverter. To further reduce the effect of
these pulsewidth modulation (PWM) harmonics, more complex
output filters can be used, such as an inductance–capacitance
(LC) or an inductance–capacitance–inductance (LCL) topology
[6], [7]. In this paper, the hardware design and the construction
of a state space control loop of an LCL output topology, such as
in Fig. 1, is treated.
A practical setup is made, using a generic single phase PWM
inverter and a digital signal processor (DSP) prototyping platform. Comparisons are made between the LCL topology and
others, such as L or LC topologies. The final evaluation criterion is the total harmonic distortion (THD) of the current drawn
from the grid.
I
Manuscript received October 14, 2004; revised June 21, 2005. This work
was supported by the Belgian “Fonds voor Wetenschappelijk Onderzoek Vlaanderen” and the Belgian IWT-GBOU Research Project on Embedded Generation.
Recommended by Associate Editor H. du T. Mouton.
The authors are with the Department of Electrical Engineering, Katholieke
Universiteit Leuven, Leuven B-3001, Belgium (e-mail: bruno.bolsens@esat.
kuleuven.ac.be).
Digital Object Identifier 10.1109/TPEL.2006.876840
Fig. 1. Topology of the LCL output stage.
II. EXPERIMENTAL DESIGN
A. Hardware Design
The hardware designer has to determine optimal values for
the parameters L , C, and L , for a given PWM inverter with
following constraints:
;
• rated dc link voltage
;
• rated IGBT current
.
• inverter switching frequency
In grid coupled applications, the bandwidth of the reference
signal can vary significantly, depending on the application. For
instance, if the purpose is to build an active filter, the bandwidth
requirements are higher than for an active front-end, where only
the fundamental frequency is concerned.
This work uses a superposition concept, where the influence
of the grid and the inverter voltage is analysed separately, and
subsequently summed to obtain a complete model. The influence of the inverter voltage is treated in following paragraphs,
and allows to derive output stage design criteria. The influence
of the grid voltage is covered by the grid oscillator model, that
is used while constructing the control loop, in Section II-C.
To study the effect of the choice of L L , and C on electric
quantities, such as the grid current , the inverter current , the
capacitor current , and the capacitor voltage , the following
transfer functions can be calculated, from the inverter voltage
to these respective states (note that the parallel sign // is
used to describe the equivalent impedance of a parallel connection of two impedances) as (1)–(4), shown at the bottom of the
0 a single L output stage is modelled. As
next page. When
can be seen, the impedances L and L are added.
Equations (1)–(4) also include the transfer functions when
0 . These solutions can be easily
there is no damping
split into poles and zeroes, while the more general third-order
solution cannot.
0885-8993/$20.00 © 2006 IEEE
BOLSENS et al.: MODEL-BASED GENERATION OF LOW DISTORTION CURRENTS
Fig. 2. Bode diagram of the different transfer functions.
Furthermore, these resistances are parasitic elements of the
reactive components, and therefore small. This is beneficiary for
the overall efficiency of the LCL output stage.
Interpreting these transfer functions, it becomes clear that in
the transfer to the grid current , the output stage behaves like
a large inductance L
L for low frequencies. The Bode diagrams of the current responses are plotted in Fig. 2.
On the other hand, the LCL output stage acts as a third-order
filter for high frequencies. The resonating equivalent elements
are the parallel connection L L and the capacitor C. Their
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resonance frequency should therefore be chosen in such a way
harmonics are adequately supthat switching frequency
pressed, while still providing enough bandwidth for the reference signal [8]. Beyond the resonance frequency, the response
decays steeply at a rate of 60 dB/decade.
For the example at hand, this frequency was chosen to be
700 Hz. This choice establishes a first relation between the unknowns L L , and C.
The next design step is to determine the total output inducL . To achieve this, a form of bandwidth criterion is
tance L
used.
A high bandwidth requires a high voltage range of the inverter
output. If the peak grid voltage is , the worst case of available voltage range occurs when the grid voltage is maximal (or
– is availminimal). In these cases, only the difference
able for control. This value immediately determines the worst
rate-of-change (the steepness) of the reference current
(5)
If the reference current contains steeper parts, it may depend
on their location in the phase of the grid whether the available
voltage will be sufficient or not.
This steepness condition can also be expressed in terms of
harmonics (nth harmonic):
L
(6)
(1)
(2)
(3)
(4)
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 4, JULY 2006
where is the grid pulsation and
the peak value of the
harmonic current. The phase of the harmonic versus the grid
voltage fundamental is not considered here, neither are simultaneously occurring harmonics—the worst case is taken. Clearly
for an increasing harmonic number, a given inverter can produce
proportionally less current.
If the reference current contains only a 50-Hz component, the
depends on the phase angle of this
required inverter voltage
current. If the current is purely active, the voltage of the inverter
must be equal to the grid voltage, but shifted in phase. If reactive
currents are necessary, the inverter voltage is in phase with the
grid voltage, and with
• a larger amplitude than the grid for capacitive current;
• a smaller amplitude than the grid for inductive current.
This corresponds to the situation of active/reactive power
transport on an overhead line, where the impedance is mainly
reactive. Hence, if no capacitive reactive compensation is
can be taken
needed, the active front end’s dc link voltage
smaller.
With the bandwidth criterion in mind, a proper value for L
L can be chosen respecting the rated values
and
of the inverter. This establishes a second relation between the
design parameters of the LCL output, in the example, L L
10 mH.
The only degree of freedom left is to distribute the 10 mH over
L and L . This choice does not affect the transfer function from
to grid current
(see Fig. 2). All other
inverter voltage
transfer functions, however, are involved. In Fig. 2, and three
cases are shown.
1 mH, L
9 mH. C is 57.4 F (dashed).
• L
5 mH, L
5 mH. C is 20.7 F (dotted).
• L
9 mH, L
1 mH. C is 57.4 F (full line).
• L
The value of C is adjusted to maintain the resonance frequency at 700 Hz. As seen, to obtain a minimal current in the
inverter and the capacitor, the value of L must be large compared to L . Apparently, the optimum lies at an infinitely small
value for L .
However, the capacitor value C increases. Large capacitors
in the output stage are a drawback: when the inverter is not operating, the capacitors cause a (large) reactive grid current, including harmonics due to the voltage distortion. When the inverter operates, it has to supply the same current by itself to the
output stage to avoid unwanted grid currents. Therefore, large
capacitors put a large current burden on the inverter, leaving less
useful current for the application. The inverter rated current is
to be compared to the reactive current of the output stage at no
operation. This criterion defines L L .
L , the inverter current
Furthermore, in the case where L
L present:
behaves as if there were only an inductance of L
the straight line of in Fig. 2 is only affected at the resonance
frequency. This allows the use of a current ripple criterion to
estimate the current ripple in the inverter.
This relation between the design parameters concerns the amplitude of the saw tooth waveform due to the PWM effect. The
effect is maximum when the effective PWM duty cycle is 50 %.
The expected variation of the current during one PWM period is
L
(7)
Fig. 3. Bode diagrams of laboratory output currents (I =U
).
Fig. 4. Bode diagrams of input admittance (I =E).
Again, this variation of the inverter current is to be compared
to the rated inverter current. Usually, the switching frequency
can be adjusted to meet this criterion.
For a given inverter, with its current rating and current measurement range, the effect of the saw tooth current (7) and the
necessary reactive current at no-load must be considered simultaneously. For instance, if an inverter has a rated current and
measurement range of 15 A, the saw tooth current and the reactive current should not exceed 5 A. This way, the controller has
a free control range of 10 A. Taking these criteria into consideration, the complete output stage can be designed to optimally
fit the rating of the given inverter.
B. Laboratory Output Stage
In the laboratory, two output stages have been put to test. The
first contains no resistive damping elements, apart from the parasitic resistance of the inductances. The second one is intentionally damped. The parameter values are (for the case without
4.1 mH,
0.95
C
20 F, L
damping): L
1.5 mH and
1.5 . The output stage with damping has
31.5 .
Figs. 3 and 4 show Bode diagrams of the influence (of, respecand the grid voltage ) on the
tively, the inverter voltage
current of primary interest, i.e., the grid current . The lower
traces correspond to the damped output filter, while the upper
traces concern the output filter with no damping. The arrows indicate the grid frequency of 50 Hz and the switching frequency
of 7.2 kHz, to illustrate the suppression of the latter.
BOLSENS et al.: MODEL-BASED GENERATION OF LOW DISTORTION CURRENTS
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Note the appearance in Fig. 4 of a transmission zero due to
the parallel resonance of L and C near 550 Hz. Signals on the
grid near 1 kHz may also excite the resonance frequency of the
undamped filter.
Taking a look at the aforementioned design criteria, and
450 V,
230 V, the undamped topology is
taking
estimated to produce currents with a maximal steepness of
L
(8)
In practice, a rate limiter is inserted in the signal path of the
reference current to obtain a rate limitation to 8 kA/s.
The four-switch topology of the inverter, operating at
3.6 kHz, produces an effective switching frequency (as seen by
the output stage) of 7.2 kHz.
Following saw tooth current is hence estimated:
(9)
Finally, the expected reactive current of the capacitors of the
output stage, can be estimated (only the fundamental is considered here)
(10)
These values can be summed and compared with the rated inverter current.
This gives a no-load burden of 4.63 A of the inverter, rated at
15 A leaving about 10 A of grid current available for control.
Fig. 5. Developing the 14-state discrete-time model.
The inverter voltage output and its effect on the LCL output
stage can efficiently be described in the discrete-time domain,
since the assumption that the output voltage is constant during
the PWM period is valid here (Fig. 5, left).
1) Grid Voltage Influence Model: A continuous-time oscillation at frequency is determined by following state space
description:
C. Control Loop Design
(11)
Once the hardware has been designed, it is possible to construct the control loop. In this work, the controller is implemented using a state space description. In a first step, a correct input/output model must be developed. Fig. 5 shows the
approach used: the superposition principle is used to obtain the
influence of grid and inverter voltage on the LCL stage separately, and subsequently, these influences can be summed to obtain the complete system description. This sum is indicated at
the bottom of Fig. 5.
The LCL output stage is connected to the inverter and the grid.
The grid is modelled as a voltage oscillator. If modelled using a
discrete-time oscillator, the output can be connected directly to
the discrete-time model of the LCL output stage (Fig. 5, right).
This approach assumes the grid voltage to be constant during
one sample time.
In reality, the grid voltage evolves continuously in time, and
a description using a discrete time oscillator introduces a small
phase and gain error. To avoid this, the grid is modelled using
a continuous-time oscillator and the resulting voltage is applied
to the continuous-time model of the LCL output stage. Subsequently, the combined model can be discretized (Fig. 5, middle).
The states and are complementary, and leads e by exactly 90 . The complete grid voltage model, incorporating oscillators at 50, 100, 150, 250, and 350 Hz, hence becomes (12),
shown at the bottom of the next page.
As can be understood from the matrix product at the bottom
line in (12), the output of the system is the sum of all states.
The states are only internal oscillator states, that do not appear
at the output. The input is noise, and may change amplitude
and/or phase over time, corresponding to the real behaviour of
the grid voltage, which is never exactly 50 Hz all the time. The
model requires 10 states.
The oscillator output voltage is subsequently connected to
the corresponding input of the continuous-time model of the
output stage. This state space model has been derived from the
fundamental equations (Kirchhoff’s Laws applied to Fig. 1)
[10], [11]. There are three reactive elements (LCL), and this
yields a third-order system. The inputs, in vector , are the
and the grid voltage . The state variables
inverter voltage
are the currents through L and L , as well as the capacitor
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 4, JULY 2006
voltage. They are also the output of the system. Note that the
sign conventions of Fig. 1 are respected
(13)
Fig. 6. Grid current I response on noise input impulse.
The resulting continuous-time model is finally discretized
(using zero-order hold), and represents an accurate model for
the influence of the grid voltage e on the states
, and u
of the output stage. To illustrate the 13-state combined model,
of the
the following signal is applied to the noise input N
model:
(14)
This impulse signal excites the grid oscillator at once, and the
strength is such that the grid voltage output becomes 230 V
at 50 Hz. The response of the grid current is indicated in Fig. 6,
showing that the LCL output stage is underdamped.
The inverter voltage is assumed to be zero, i.e., a short circuit,
explaining the large current. The steady state value can also be
calculated using complex numbers
(15)
2) Inverter Voltage Influence Model: The effect of the
inverter output voltage is entirely described in the discrete-time
domain, and requires the conversion of the continuous-time
model (13). Furthermore, to account for the delay effect of any
digital control loop, a delay block is inserted before the
input of the LCL output stage, providing the necessary delay
in the model. This system also introduces a noise input w for
Fig. 7. Combining the system matrices.
the process noise of the inverter operation. Altogether, both
and ,
systems take four states: the LCL output states
.
as well as the delayed control voltage
3) Combining the Influences in One Model: In previous sections, two models are derived: a 13-state model to describe the
effect of the grid voltage on the output stage, and a four-state
model for the influence of the inverter voltage on the output
stage.
Both discrete-time models are now combined, and the reand are added, acsponses for corresponding states of
cording to the superposition principle. This can only be done if
the system matrices of both separate systems contain a common
part, indicated by the shaded square on Fig. 7. The two original
system matrices are displayed in bold lines: the upper left matrix
(12)
BOLSENS et al.: MODEL-BASED GENERATION OF LOW DISTORTION CURRENTS
is the four-state inverter influence, and the bottom right matrix
is the 13-state grid voltage influence. The resulting system matrix is 14 14.
4) State Observer Design: To reduce the number of sensors
only the measurement of the inverter current is used to estimate
all 14 states. As this system is fully observable through the inverter current measurement (the observability matrix is of full
rank), a stationary Kalman estimator can be built. The inputs to
and
the estimator are the reference inverter output voltage
the current measurement of .
The measurement noise of is obtained by monitoring samples of a dc current over a longer period, and calculating the
50 mA.
variance. This yields
The process noise inputs are w (inverter) and W, the ten grid
is estimated at 0.5 V
.
voltage oscillator noise inputs.
The ten “noise” inputs for the grid estimation have been determined by trial and error, as practiced by [9]. The reason is that
if the convergence is too fast, the measurement noise results in
a noisy signal of the oscillator output, and audible noise in the
inductance L in the output stage. On the other hand, if it is too
slow, the settling time is large, and large currents appear before
the grid voltage is estimated properly. These noise parameters
40 V/s.
are set at
5) Reduced State Vector—Disturbance Decoupling: If the
system’s state is known, the state vector can be fed back to the
input to obtain a good closed-loop performance. The system
at hand, however, is not fully controllable, due to the internal
grid voltage oscillators. To solve this problem, a reduced
state vector is created, containing only the controllable states
and . To eliminate the contribution of the
grid voltage on the system’s states, a compensating voltage is
fed to the inverter reference input. It is impossible however,
to eliminate the grid voltage effect in all states at once. In this
work, the most important state is the grid current , and the
compensating voltage is calculated to obtain a grid current
free of disturbance. This implies immediately that the three
other states still contain grid frequency components. In fact, the
has to track the grid voltage e perfectly to
capacitor voltage
0, and charging of C is done through .
obtain
The calculation of the compensating voltage is done by considering following transfer functions from grid voltage e and
to the states
,
and
:
inverter voltage
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the grid voltage effect in the grid current, following complex division is done for every frequency:
(17)
The resulting five complex numbers are split into their real
and imaginary components and are the feedback gain from the
to the
state vector’s oscillator components
inverter reference input to perform compensation.
The second step is to erase the effect of the grid voltage
and the compensating voltage in the remaining three states. To
achieve this, following four complex numbers are calculated for
every frequency
(18)
The same procedure applies: all complex numbers are split
into real and imaginary part and make up a 4 10 gain matrix.
are multiIf again the 10 oscillator states
plied, the resulting 4 1 vector erases the grid voltage effect in
the remaining states.
This concludes the construction of a reduced state vector.
6) State Feedback: The reduced state vector represents
as only input, and
the state of a reduced system, having
and
as states and output. State feedback
for this fourth-order system can be made by pole placement
techniques or an other criterion. In this work, a linear-quadratic
regulator is designed using Matlab. The cost function J minimized, puts the stress on the grid current :
(19)
7) Reference Input: The final step is the insertion of the reference signal in the controller.
In this work, the reference is fed to the voltage reference input
of the inverter, through an appropriate static gain. To optimize
the step response of the system, an additional preconditioning
filter can be inserted. An overview of the Simulink control loop
is given in Fig. 8.
(16)
D. Laboratory DSP System Description
The control algorithm is converted from the data flow description in MATLAB/Simulink to “C”-code using MATLAB’s
Real-Time Workshop feature. The algorithm is then executed in
a software framework on a Texas Instruments C6711 150-MHz
digital signal processor (DSP). The total processor load is 89%
with the algorithm running at 7.2 kHz. An FPGA daughtercard
on top of the C6711 DSK board (accommodating the C6711
DSP) generates the PWM signals and provides an interface to
the IGBT PWM inverter and the current transducers.
These eight transfer functions are evaluated in the complex
domain (in continuous-time resp. discrete-time) for the five frequencies of the voltage oscillator. To obtain the cancellation of
III. SIMULATIONS AND MEASUREMENTS
Simulations are carried out to evaluate the system’s convergence after startup. The voltage observer must provide an ac-
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 4, JULY 2006
Fig. 8. Overview of the control loop. Numbers indicate vector dimensions.
Fig. 9. Grid voltage estimator convergence at startup.
Fig. 11. Grid current for various output stages (PWM disabled).
Fig. 10. Suppression of the grid influence on inverter and grid current.
curate estimate of the grid voltage for the control loop to work
properly.
Figs. 9 and 10 show that the observer is capable of suppressing the influence on the grid current. The reference signal
is a 5-A square wave, not synchronized to the grid. The lighter
trace in Fig. 10 is the inverter current, clearly showing current
saw tooth ripple due to the PWM switching. Also the grid influence is felt in the inverter current, but not in the grid current
after the output stage filtering.
Measurements are carried out on the laboratory LCL and LC
output stage, to evaluate the effect of different topologies, and
damping.
In Fig. 11, the PWM inverter is disabled, and the grid current is the capacitive output stage current. The grid voltage is
also shown. For clarity, the currents for the various cases are
given an artificial offset. The upper current trace is for the undamped LCL topology, the middle trace for an LC topology,
and the bottom trace for a well damped LCL topology. Clearly,
the undamped LCL system shows resonance, though the amplitude is not large. If an LC topology is used, the small parasitic grid inductance resonates with the capacitor, explaining the
higher resonance frequency. Only the well damped LCL system
of the bottom trace shows no resonance. Note that all currents
are highly distorted due to the voltage distortion of 2%–3%. The
peak value of this current is to be compared to the expected value
of 1.8 A when designing the output stage, and where only the
fundamental is considered.
In Fig. 12, the control loop is operational, and the reference
grid current is zero. As in the remaining figures, the lighter trace
BOLSENS et al.: MODEL-BASED GENERATION OF LOW DISTORTION CURRENTS
1039
Fig. 12. Inverter and grid current, various output stages (control operational).
Fig. 14. Inverter and grid current for square wave reference.
Fig. 13. Inverter and grid current for LCL (upper) versus LC (lower) output
stage.
shows the inverter current, while the black trace is the grid current, after passing the output stage. The grid voltage is also displayed in each figure.
Both damped LCL and undamped LCL topologies are shown
in Fig. 12, each on a different offset. The undamped topology
(upper traces) still exhibits a little resonance, negligible on the
full scale of the current. The small active current drawn from
the grid covers the power losses inside the PWM inverter, and
keeps the dc link voltage at 450 V.
Also clearly visible is the amplitude of the saw tooth current
in the inverter, expected to be about 2.79 A. Since the rated inverter current is about 15 A, positive and negative, the upper and
lower boundaries of the figure are also the inverter’s boundaries.
Even at no-load a part of the inverter’s current range is used.
is given.
In Fig. 13, a reactive reference current of 5 A
The PWM harmonics are well suppressed, and the grid current
has a THD of only 0.93%. The current is 90 out of phase with
respect to the grid voltage. As can be seen, the reference current
consumes about the entire inverter current range. The figure also
shows the inferior performance of the LC output stage, compared to the undamped LCL topology (shown on a different
offset).
To assess the performance of the controller on higher bandwidth applications, a square wave reference current of 5 A is
taken (not synchronized to the grid frequency). The slope of this
signal is also limited to 8 kA/s. Figs. 14 and 15 show a global
and detailed picture of the various currents. Note that the saw
tooth inverter current is minimal when the grid voltage crosses
zero. Finally, Fig. 16 shows the current transients when the inverter suddenly switches off. Clearly, the output stage resonance
Fig. 15. Detail of Fig. 14.
Fig. 16. Transient grid current when the inverter switches off.
slowly fades away. The influence of the oscillatory current on
the grid voltage is also noticeable.
IV. CONCLUSION
In this paper, the hardware design and control aspects of
a single phase LCL output stage are treated. By designing a
control loop that observes the grid voltage and distortion, a
very good grid current performance is achieved. Total harmonic
distortion reaches values below 1%, even in the presence of
a voltage distortion of 2%–3%. The LCL output stage also
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 4, JULY 2006
efficiently suppresses the switching frequency currents in the
grid. The control loop requires only the measurement of the
inverter current.
Future research is focusing on optimizing the control loop
parameters, and reducing the DSP load, so that more DSP computation time is available for more complex algorithms, such as
coupled to the grid. Also the exUPS-devices, active filters,
tension to a three-phase application is studied.
Karel De Brabandere (S’05) received the M.Sc.
degree in electrotechnical engineering from the
Catholic University of Leuven (K.U. Leuven),
Belgium, in 2000 where he is currently pursuing the
Ph.D. degree in the control of grid-connected power
electronic inverters for the integration of distributed
energy resources in island grids and the utility grid.
His research interests include power electronics,
digital control, distributed power systems, and
microgrids.
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Bruno Bolsens (S’05) received the M.Sc. degree
in electrotechnical engineering from the Catholic
University of Leuven (K.U. Leuven), Belgium,
in 2000 where he is currently pursuing the Ph.D.
degree in power electronic circuits with limited
electromagnetic interference properties in electric
distribution networks.
His research interests include power electronics,
digital control, inverter topologies, power quality, and
EMC issues.
Jeroen Van den Keybus (S’05) was born in Belgium
in 1975. He received the M.S. and Ph.D. degrees in
electrical engineering from the Catholic University of
Leuven (K.U. Leuven), Belgium, in 1998 and 2003,
respectively.
He is currently a Research Assistant with the
Electrical Engineering Department, K.U. Leuven,
where he performs research in the area of power
electronics, and has a wide working knowledge
and expertise in designing complex digital systems
using reconfigurable and dedicated signal processing
components.
Johan Driesen (S’93–M’97) was born in Belgium in
1973. He received the M.Sc. and Ph.D. degrees from
the Catholic University of Leuven (K.U. Leuven),
Belgium, in 1996 and 2000, respectively.
He is currently an Associate Professor at K.U.
Leuven and teaches power electronics and drives.
From 2000 to 2001, he was a Visiting Researcher
in the Imperial College of Science, Technology
and Medicine, London, U.K. In 2002, he was with
the University of California, Berkeley. Currently,
he conducts research on distributed generation,
including renewable energy systems, power electronics and its applications, for
instance in drives and power quality.
Ronnie Belmans (S’77–M’84–SM’89) received the
M.Sc. and Ph.D. degrees in electrical engineering
from the Catholic University of Leuven (K.U.
Leuven), Belgium, in 1979 and 1984, respectively,
and the Special Doctorate and Habilitierung degrees from the Rheinisch-Westfdlische Technische
Hochschule Aachen (RWTH), Aachen, Germany, in
1989 and 1993, respectively.
Currently, he is a full Professor with K.U. Leuven,
teaching electric power and energy systems. He is
also a Guest Professor at Imperial College of Science,
Medicine and Technology, London, U.K. His research interests include technoeconomic aspects of power systems, power quality, and distributed generation.
Dr. Belmans Chairman of the Board of Directors of ELIA (the Belgian transmission grid operator).