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A Local Passive Time Interpolation Concept
for Variation-Tolerant High-Resolution
Time-to-Digital Conversion
Stephan Henzler, Member, IEEE, Siegmar Koeppe, Dominik Lorenz, Winfried Kamp, Ronald Kuenemund, and
Doris Schmitt-Landsiedel, Member, IEEE
Abstract—Time-to-digital converters (TDCs) are promising
building blocks for the digitalization of mixed-signal functionality
in ultra-deep-submicron CMOS technologies. A short survey on
state-of-the-art TDCs is given. A high-resolution TDC with low
latency and low dead-time is proposed, where a coarse time quantization derived from a differential inverter delay-line is locally
interpolated with passive voltage dividers. This high-resolution
TDC is monotonic by construction which makes the concept very
robust against process variations. The feasibility is demonstrated
by a 90 nm demonstrator which uses a 4x interpolation and provides a time domain resolution of 4.7 ps. An integral nonlinearity
of 1.2 LSB and a differential nonlinearity of 0.6 LSB are achieved.
The resolution restrictions imposed by an uncertainty of the stop
signal and local variations are derived theoretically.
Index Terms—Digital calibration, digital PLL, high-resolution
time interval measurement, passive time interpolation, pulse
shrinking, time-to-digital converter (TDC), Vernier TDC.
I. INTRODUCTION
H
IGH-RESOLUTION time-to-digital- converters (TDCs)
become increasingly popular for time-of-flight measurements, full speed testing, e.g., jitter measurement, clock
data recovery, measurement and instrumentation, and digital
phase-locked loops (PLLs) [1]. This arises from the scaling
difficulties of mixed-signal circuits in the deep-submicron
regime: While voltage levels decrease continuously noise does
not scale, so the signal-to-noise ratio (SNR) degrades. The
ratio, decreases
analog device performance, e.g., the
considerably below the 100 nm technology node. Moreover,
the application of well known circuit techniques like cascodes
is limited for supply voltages of 1.0 V and below. Since most
applications have stringent performance requirements in terms
of signal-to-noise and distortion ratio, i.e., resolution, the design of mixed-signal building blocks becomes more and more
difficult and power intensive. Regarding area, the analog scaling
factor considerably lags behind the digital one so the relative
portion of analog and mixed-signal blocks increases even if
functionality is continuously shifted towards the digital domain.
Manuscript received November 21, 2007; revised February 24, 2008. This
work was supported in part by the German Federal Ministry of Education and
Research (BMBF) under the SIGMA65 project, Grant 01M3080.
S. Henzler, S. Koeppe, W. Kamp, and R. Kuenemund are with the Advanced
Systems and Circuits Department, Infineon Technologies AG, 81726 Munich,
Germany (e-mail: Stephan.Henzler@infineon.com).
D. Lorenz and D. Schmitt-Landsiedel are with the Institute for Technical
Electronics, Technische Universitaet Muenchen, 80290 Muenchen, Germany.
Digital Object Identifier 10.1109/JSSC.2008.922712
On the other hand, digital CMOS circuits take best advantage
of technology scaling in terms of area, gate delay, and to some
extent power consumption. As technology development is
mainly driven by digital requirements this is not surprising, but
means that in the deep-submicron regime the scaling of time
resolution is superior to voltage resolution [2]. This implies
the superior scaling properties of TDCs. In the past most
signal processing tasks have been digitized and implemented
inside a mixed-signal shell, e.g., consisting of data converters.
Currently there is an upcoming trend to digitize parts or even
complete mixed-signal blocks. The all-digital PLL [2] for
instance is a precursor for this final rush for digitalization.
Minimizing the analog portion in such systems means not only
better scaling properties but enables completely new options
like the reconfiguration of filters or the presetting, storage, and
recovery of internal states. In this context TDCs are considered
to be important building blocks. Below the 100 nm node the
delay scaling decelerates, especially in low-power technologies
where leakage currents play an important role. However, the
area and delay scaling of digital building blocks are still the
drivers for scaling. So mixed-signal systems based on TDCs
will benefit most from technology scaling.
In this paper, we will discuss a new concept for high-resolution TDCs. The coarse time quantization of an inverter delayline is subdivided by a local passive interpolation (LPI) technique. This enables not only sub-gate-delay resolution but also
minimizes the latency and the dead-time of the converter. The
delay-line inside the converter is intrinsically monotonic, so
the TDC appears to be very robust against process variations.
The remainder of this paper is organized as follows. First, an
overview on existing TDCs is given in Section II. In Section III
the principle of the local passive interpolation time-to-digital
converter (LPI-TDC) is explained. Section IV discusses implementation details and Section V describes measurement results
for a 90 nm demonstrator. Finally, Section VI discusses the resolution limitations of the converter.
II. A SHORT SURVEY ON TIME-TO-DIGITAL CONVERTERS
A. Principle of Operation
The basic task of a TDC is to quantize the time interval between a start and a stop signal and to provide a digital representation. The difference between a TDC and a simple counter
is the high resolution in the order of a few picoseconds. Counters can quantize coarse time intervals by simply counting the
number of reference clock cycles fitting into the respective time
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HENZLER et al.: LOCAL PASSIVE TIME INTERPOLATION CONCEPT FOR VARIATION-TOLERANT HIGH-RESOLUTION TDC
interval. However, with increasing resolution requirements the
reference clock frequency becomes unreasonably high with respect to power consumption or cannot at all be generated and
handled in a CMOS circuit. Time-to-digital converters are asynchronous circuits in a sense that they provide an extremely high
time resolution which is not based on an external time reference. As will be shown later, some TDCs do utilize a reference
frequency. This reference frequency, however, is used only for
calibration or coarse time quantization, but does not determine
the overall resolution.
The very first TDCs were actually time-to-voltage-to-digital converters [1]. In these converters the time interval to be
measured is converted into an analog voltage in a first phase,
e.g., by using a charge pump. In a second step, a conventional
analog-to-digital converter (ADC) translates the voltage equivalent of the time interval into the digital domain. Although very
high resolution has been reported, the attractiveness of these
converters decreases for technologies below the quarter micron
node. This stems from the fact that the converter itself is mainly
an analog circuit. The design challenges in deep-submicron
technologies with strongly scaled supply voltages and relatively
high threshold voltages are the same as for other mixed-signal
circuits. The resolution, the scalability, the robustness and the
area and power consumption are limited by the internal ADC,
so the time domain yields no profit compared to the voltage
domain.
One popular TDC approach, especially attractive for deepsubmicron technologies, is the use of digital delay-lines (see
Fig. 1) [3]. A start signal propagates along a line of digital delay
elements. The output node of each delay element is connected
to the data input of a flip-flop or latch. The state of the delay-line
is sampled, e.g., on the rising edge of the stop signal. The position of the signal transition, e.g., one-zero transfer in the pseudo
thermometer code is visible at the output nodes of the flip-flops,
and is a measure for the time difference between the start and
the stop signal. The advantages of this circuit are obvious: It
uses only two very simple and small cells, namely digital delay
elements and flip-flops. The resolution is given by the delay
of a digital buffer or inverter. Hence, both the resolution and
the area scale according to the digital scaling factors. As there
are no current sources, power is only consumed during conversion phase. Most analog design issues which are critical in the
time-to-voltage-to-digital converter are considerably relaxed for
the delay-line based TDC. Currently, the maximum resolution
is achieved with an inverter delay-line. The alternating signal
polarity, however, has to be considered during the design of the
line: For simple CMOS inverters the delays for rising and falling
transitions as well as the signal slopes cannot be matched across
all process corners. Tunable delay elements are not desirable
as their increased circuit complexity causes a higher delay. An
equal difficulty arises from the meta-stability curves for a logical
high or low signal at the input of the flip-flops. To circumvent
these difficulties two delay-lines or even a differential delay-line
connected to totally symmetrical differential flip-flops should be
used [see Fig. 1(b)].
The length of the delay-line increases linearly with the time
interval to be measured. To avoid a high area and power consumption, a reference clock signal can be used for a coarse time
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Fig. 1. Basic structure of a digital delay-line based time-to-digital converter
(TDC). Delay elements consisting of CMOS buffers (a) allow for a very regular
structure but yield only half the resolution of an inverter based TDC (b).
quantization and a TDC for the measurement of the residue at
the beginning and the end of the interval [4]. Alternatively, the
delay-line may be bent to a ring of delay elements where the
rising edge of the start signal propagates cyclically. As will be
discussed below, this does not only limit the number of circuit
elements but also improves the linearity of the converter.
B. TDC Calibration Techniques
One difficulty common to all delay-line based TDCs is the dependence of the time resolution on the delay variation caused by
global process variations. There are two strategies to cope with
this issue. The first one illustrated in Fig. 2 again is an analog approach. The TDC is embedded into a delay-locked loop (DLL)
and the delay along the complete delay-line or along an appropriate fraction is locked to the period of a reference signal [5].
The delays may be tuned via the supply voltage or current limiting header and footer devices. Again a considerable amount
of analog circuitry has to be added to the system. Thereby, all
the analog drawbacks are still present in the TDC design and
the area scaling is degraded. The second approach is purely digital: The period of a known reference signal is measured periodically, e.g., during idle periods of the system. The resulting
measurement value is used to correct all further measurement
results during the digital post-processing. However, the quantization of both the actual measurement and the reference measurement may cause numeric issues like a non-monotonic phase
characteristics even if the TDC provides monotonic measurements. This effect is a drawback of the digital calibration but
can be mitigated by a sufficiently high resolution. Most applications work with normalized values, anyway: In a digital PLL
for instance the time difference between a rising reference edge
and a rising edge of the local oscillator is normalized to the period. If both time measurements are done with the same TDC,
i.e., subject to the same process variations, the global variation
impact cancels out during the digital normalization.
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Fig. 2. Time-to-digital converter operated in a delay-locked-loop which makes the overall delay equal to an external time reference independent of process variations or environmental conditions. The loop filter and the charge pump are analog components which is in contradiction to a purely digital approach.
Other than that, environmental variations, i.e., voltage and
temperature variations, necessitate a regular calibration. However, if this is feasible the digital calibration is nearly for free
as the digital infrastructure required for the normalization is already there due to other post-processing tasks [6], [7]. In the
GHz domain the signal period is that small that the delay line
can be designed long enough to capture a full period? This allows for continuous calibration without the need for calibration
intervals.
C. TDC Concepts for Sub-Gate Delay Resolution
In the deep-submicron regime, increasing leakage currents
preclude further constant field scaling. As a consequence the
speed leverage of new technologies is moderate, especially in
the field of low-power. Hence, without new architectural concepts TDC resolution will not improve significantly for the next
couple of technology nodes. Time-to-digital converters with
sub-gate delay resolution have been developed for applications
that require a resolution higher than one inverter delay.
In principle, parallel scaled delay elements [5] may provide
a high sub-gate delay resolution. The drive strength or the load
of parallel inverters or buffers is slightly modified in order to
alter their delay. The drawback with this approach is the missing
causal relation among the signal edges occurring at the outputs
of the inverters, so local process variations may easily disarrange the switching sequence of the inverters. To some extent
a digital correction can compensate for this effect, however, it
is difficult for the designer to guarantee for a certain resolution
and linearity.
The Vernier TDC [8]–[10] utilizes a technique known as the
Nonius principle in the context of slide gauges [Fig. 3(a)]. Both
the start and the stop signal are delayed in independent delaylines. The delay elements for the stop signal are designed for
slightly faster signal propagation than the delay elements for the
start signal. Therefore, in each stage the stop signal catches up
more and more with the start signal. Early-late-detectors, e.g.,
flip-flops, detect the buffer stage where the stop signal outruns
the start signal, so providing a measure for the initial time difis given by the delay difference
ference. The resolution
. Assuming local process variations of the
buffer delays, the time difference between the start and the stop
confidence only if
edge in a certain stage is reduced with a
. This can be seen as a simple rule
of thumb for an upper bound of the TDC resolution. In practice
the variations of the early-late-detectors, i.e., of the flip-flops degrade the resolution further. One stage consisting of two buffers,
i.e., four inverters, and an early-late-detector is required to re, the consolve one LSB. According to
version time increases linearly with the time interval and even
hyperbolically with increasing resolution. The same holds for
Vernier
the area consumption, thus, for large and small
TDCs become both slow and area expensive.
Another TDC concept which is also based on unequally sized
inverters is the pulse shrinking TDC [11] illustrated in Fig. 3(b).
First, the start and the stop signal are used to generate a pulse
with a pulsewidth equal to the time difference. Again, this pulse
propagates in a chain or in a ring of delay elements. Some of
these delay elements, the so-called pulse shrinking elements,
. After
have the property to modify the pulsewidth by one
two inverters a pulse with an initial pulsewidth has a mod. For
ified pulsewidth given by
symmetrical rising and falling delays or for asymmetrical but
equal inverters the pulsewidth does not change. However, for
unequally sized inverters the pulsewidth is changed by
. The input time interval can be measured by detecting the pulse shrinking element after which the
pulse vanishes. One pulse shrinking element plus a pulse de, so the latency as well as
tector is required to resolve one
the power and area consumption rapidly grows with increasing
dynamic range and resolution (delay line). To guarantee that the
pulsewidth is reduced in each stage even under process variconfidence) the resolution is again limited
ations (with a
. To limit the length of the chain the pulse
to
can be also propagated in a looped delay-line with a single
pulse shrinking element [11]. As the complete pulse must fit
. Even without
into the loop, the minimum length is
any pulse shrinking elements the pulse width is altered in each
due to local process variiteration by
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of several TDCs can be compared by adopting the established
for
ADC figures of merit, namely
for the area, where
the power and
is the power consumption,
the maximum conversion rate,
the area, and
the effective number of bits.
Fig. 3. Basic circuit structure of (a) a Vernier delay-line based TDC and (b) a
pulse shrinking TDC.
ations. (
describes a normal distribution with mean m
and standard deviation .) The pulse shrinking element must at
least compensate for the variation induced pulse growing, so the
resolution is degraded with increasing dynamic range. Tuneable
pulse shrinking elements could avoid this drawback, however,
the calibration is much more difficult than the simple tuning of
delay-line.
D. TDC Performance Metrices
Functionally, TDCs are very similar to ADCs except the fact
that not a continuous voltage but a continuous time interval is
quantized. Hence, all performance figures describing the step
function of ADCs (e.g., offset and gain error, differential and
integral nonlinearity) may be also used for a TDC characteristics. The dynamic range of a TDC is the maximum time interval that can be measured without any saturation effects. The
conversion time or the latency, respectively, describe how long
it takes after a start or stop signal before the measurement result is available. The dead time is the minimum time between
two acquisitions before a new measurement can be started. For
TDCs with sub-gate delay resolution the interpolation factor IF
is a useful quantity to review
defined by
which resolution is provided by the technology and which additional resolution is accomplished by circuit techniques. The
noise performance of a TDC is usually described by the single
shot precision: If a constant time interval is measured repeatedly, the digital output values vary with a standard deviation that
is called single shot precision. The area and power consumption
E. Linearity of Delay-Line Based TDCs
Global process variations and varying operating conditions
affect all delay elements, causing gain and offset errors. By applying a calibration measure these effects can be cancelled out.
Local variations like random dopant fluctuation or line edge
roughness, however, affect each transistor independently and result in uncorrelated delay variations along the chain of delay
elements. These delay variations accumulate along the chain.
So the delay of a chain consisting of n elements varies with
. Operating the TDC
a standard deviation equal to
within a DLL makes the overall delay equal to a fixed reference
delay. This reduces the maximum uncertainty by a factor of
which is a moderate benefit compared to the considerable effort required for the DLL (see Fig. 4 for schematic illustration).
A better linearity can be achieved by keeping the delay-line as
short as possible. A high dynamic range is preserved by folding
the chain into a loop, so the start signal can traverse the same
delay-line multiple times. A counter determines the number of
loop cycles. Depending on the TDC approach a loop configured
as ring oscillator or as ring-shaped shift register which propagates pulses is possible. Consequently, for good linearity a short
delay-line in a loop configuration should be applied. However,
in a looped TDC the layout is a very critical point as the feedback path causes asymmetries and so nonlinearity. Another critical point is the control logic of the loop. As the stop signal
is completely asynchronous to any other signal in the TDC the
sampling of this stop signal and the disabling of the loop counter
is very important [7]. A LSB error in the loop counter is not acceptable because it corresponds to a full cycle of the TDC and
is therefore not an LSB error of the overall result.
III. PRINCIPLE OF LPI TIME-TO-DIGITAL CONVERSION
The local passive interpolation TDC achieves a sub-gate
delay resolution by subdividing the coarse time interval given
by an inverter delay line. The basic principle is similar to the
voltage interpolation in interpolating flash or folding ADCs
[12] and is illustrated in Fig. 5. Assume two rising signal
. Single-stage
transitions with a skew of one inverter delay
CMOS gates provide a signal transition time in the order of
the gate delay. If the rise-time is larger than the gate delay, the
second signal starts rising while the first signal still increases.
defined by
A new signal
(1)
shows its transition in between those of the two generating sigand . Together with a comparator latch detecting the
nals
crossing of the midlevel, the new signal can be used to quantize
and
. A passive voltage dithe time interval in between
vider as shown in Fig. 6 can be connected between
and
to generate the interpolated signals defined by (1). Parallel sampling gives a high-resolution thermometer code but at the same
low latency and dead-time as for the coarse inverter based TDC.
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Fig. 4. Uncertainty of the signal arrival time at a certain node in a delay-line caused by process variations. Uncorrelated variations accumulate along the chain, so
long delay-lines suffer from large uncertainty. A gain compensation, e.g., by a DLL approach, or a short delay-line configured in a loop reduce this uncertainty.
Fig. 5. Principle of time step interpolation by creating intermediate edges in
between two logically equivalent signals with a skew of one inverter delay T .
Fig. 6. Possible implementations of resistive interpolators. Resistor based interpolator (left) and diode based interpolator with reset transistors (right).
In contrast to the Vernier and pulse shrinking TDC this means
that the measurement time does not increase with increasing
resolution.
It is worth mentioning that the time interpolation in the
LPI-TDC is monotonic by construction. The sequential inverter
chain is monotonic even under strong variations due to the
causality in the delay line [6]. The interpolated signals are
linear dependent on the signals generated by the inverters. The
passivity assures a monotonic local interpolation as an interpolated signal is always smaller than all interpolated signals
further above in the interpolator and always larger than all
signals below. The interpolated signal is exactly parallel to the
generating signals
and
only in the middle of the transition
region. Indeed this is sufficient as the comparators detect the
crossing of the midlevel only. The passive interpolation is also
the reason why the LPI TDC is said to be robust against local
variations. If the delay of an inverter stage varies, the passive
interpolation translates this variation to a subdivided variation
of the intermediate signals. The sequence of the interpolated
signals remains unchanged even for strongly varying resistors.
The switching sequence of parallel scaled delay elements for
example can be disordered by local variations. This may result
in missing codes in the converter characteristic. Local variations
also alter the sampling behaviour of the comparators which
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Fig. 7. Design tradeoff for the passive interpolators between good linearity and low power consumption.
Fig. 8. Truly monotonic differential inverter delay-line illustrating the principle of local passive time interpolation (LPI). The coarse transitions generated by the
inverters are further resolved by monotonic voltage dividers. Differential sense amplifiers sample the chain on a rising edge of the stop signal.
may disorder the switching sequence of all types of TDCs.
Therefore, the sampling elements must be carefully designed.
The voltage divider formula according to (1) holds only if
there is no current drawn from the intermediate nodes. However,
the intermediate nodes are loaded by the input capacitances of
the sampling elements. For the interpolated signals to follow the
input signals instantaneously, the resistor values have to be low
enough. A good starting point for the circuit optimization can
from
to
, where
be derived by the Elmore delay
is the lowest interpolation voltage, i.e.,
in Fig. 6:
(2)
where
is the capacitance at the interpolation nodes and
is the rise-time of the original signal. As small resistors
mean large cross currents there is a tradeoff between a good
linearity and a low power consumption. Fig. 7 illustrates this
tradeoff. For the case on the left-hand side, the resistor values are
to large which results in a weak interpolation. On the right-hand
side, the interpolation is much better, but the power consumption
illustrated by the current profile in the resistors is also higher.
The figure in the middle shows a tradeoff between an acceptable
nonlinearity and power consumption.
Two logically equivalent signals with a skew of only one incannot be realized with single ended static
verter delay
CMOS logic. The large delay of buffers would require unattractively low signal slopes. Hence, according to Fig. 8 two coupled
inverter chains are used to propagate both the start signal and the
inverted start signal. Now, two rising signals with a skew of
are available at a node A in the first delay chain and at the output
node B of the subsequent inverter in the second delay chain.
Therefore, the delay chain in Fig. 8 provides a set of skewed
and a set of skewed copies of
copies of the start signal
aligned to the first set. The aligned
the inverted start signal
and complementary signals at the inputs of the chain are generated by a balanced clock splitter. On the rising edge of the stop
signal the state of the LPI delay chain is sampled by differential
comparators connected to the pairs of complementary signals
.
A LPI delay line according to Fig. 8 can be combined with any
existing TDC architectures, for instance the multistage TDC [9]
or the reference recycling TDC [5]. It can be used open-loop,
in a ring or in a DLL structure. In contrast to Vernier [8] or
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Fig. 9. Layout cutout of the LPI delay chain with delay elements (1), polysilicon resistors (2), and sense-amplifiers (3). Latches and clock tree are located in
a different power domain and substrate well than the delay chain.
pulse shrinking [11] TDCs both the latency and the dead-time
are extremely low, i.e., equivalent to a basic delay-line TDC with
coarse quantization. The complete thermometer code is available one clock-to-Q delay of the sampling latches after the stop
edge and no deskewing is required. The overall latency depends
on the digital post processing. A new conversion can be triggered as soon as the thermometer code is latched into the post
processor. For the same resolution the LPI chain is by a factor
of IF (level of local interpolation) shorter than a Vernier chain.
This allows for area and power efficient TDCs and improves
linearity.
IV. IMPLEMENTATION ASPECTS AND DEMONSTRATOR
The linearity of ohmic resistors makes salicide blocked
polysilicon resistors the first choice for the interpolators. Integrated resistors are said to be (area) expensive and inaccurate.
However, as the time constants for charging the intermediate
nodes must be lower than the rise time of the base signals the
resistors are small and the resistor length is usually limited
by the design rules related to the salicide blocking mask. The
interpolation is defined by a resistor ratio. Hence, global resistance variations are not critical. No additional process steps
are required as salicide blocking is usually needed for ESD
devices anyhow. Thermal noise in the resistors causes kT/C
noise at the inputs of the comparators. However, due to the
large signal slopes in the order of one inverter delay the noise
voltage translates into a negligible time uncertainty.
PN-diodes have been checked to allow for compact interpolator implementations (Fig. 6). Depending on the orientation of
these diodes, only rising or falling signals can be interpolated
and the internal nodes must be discharged by reset transistors
before the next interpolation event. Transistor based interpolators, i.e., transmission gates or diode connected transistors require relatively large devices and suffer from voltage dependent
resistance especially for medium voltages. As the gate of these
transistors has to be connected to a constant potential the layout
becomes less symmetrical compared to ohmic resistors.
A 7-bit TDC is implemented in a 90 nm standard CMOS technology with a nominal supply voltage of 1.2 V. A fourfold local
passive interpolation uses polysilicon resistors. For matching
reasons a fully symmetrical interdigitated layout style is used
for the two delay chains (Fig. 9). All signal wires are completely
Fig. 10. Dependence of flip-flop delay on signal arrival time for nominal
process parameters (right) and local process variations (left). For TDC applicais relevant (not the classical setup time used for
tions the blackout time T
the timing description of flip-flops in synchronous circuits).
shielded to avoid cross coupling which would degrade the alignment of the complementary signals even in a symmetric design.
Cross-coupled inverters are inserted as coupling elements to assure the phase alignment under local parameter variations.
Any skew of the local stop signals results in a nonlinearity of
the converter characteristics. Thus, the stop signal is distributed
via an H-tree in which all driver outputs of the last two levels
are connected (clock mesh). The latency along the tree results
in an offset error of the converter characteristics which is compensated in the digital domain. The delay chains are located in
an insulated substrate well (triple well process). A heavily decoupled power supply network separated from the power supply
of the sampling flip-flops and the distribution tree of the stop
signal allows for monotonic signal propagation in the chain.
So the distribution of the stop signal and the activity of the
flipflop cannot cause nonlinearities in the converter characteristics. Power supply noise may degrade the dynamic resolution
of the TDC. Nonetheless, the low delay of basic inverters makes
them the first choice for TDC applications even if other delay elements like differential amplifiers are preferable with respect to
power supply rejection.
Sense amplifier based flip-flops [13] with fully symmetrical
layout and symmetrical connections to the delay chain are used
as sampling elements. The precharge of the internal senseamp
nodes avoids history effects from prior conversions. The footer
and the differential pair
and
in Fig. 8
transistor
over
curve shown in
are large to achieve the sharp
Fig. 10 and to minimize comparator offset. This sharp characteristic is essential to preserve the high resolution of the delay
chain during the sampling process. In conventional logic designs the data signal fed to a register must be stable at least the
setup time prior to the clock signal. In a TDC however, there
is always a comparator, namely in the region of the signal transition, where the data signal arrives very late. Hence, in TDC
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Fig. 11. On-chip measurement unit to stimulate the TDC and to map the TDC measurement result to an absolute time interval.
applications the setup time is meaningless. More relevant is the
data-to-clock time where the registers fail completely to sample
the input signal. We refer to this particular data-to-clock interval
. Due to the setup time violations in the
as blackout time
TDC, metastability is an issue when the measurement result is
over
transferred into a synchronous logic domain. A sharp
curve reduces the risk of metastability in the comparators.
Other than that Fig. 10 shows the impact of local process variations on the metastability curves of the comparators and so on
the blackout time. This variation causes a sampling uncertainty
and limits the maximum resolution of the TDC.
provided
To convert the pseudo thermometer code word
is first
by the comparators to a digital phase information,
passed to a bubble correction stage which removes erroneous
transitions. In a next step, the thermometer code is converted to
a binary representation.
V. EXPERIMENTAL VERIFICATION
The acquisition of a TDC characteristics requires a time interval sweep, i.e., the time interval between the start and the stop
signal has to be increased with a picosecond accuracy. Two independent signal sources are not suitable because they suffer
from uncorrelated jitter. In this paper the on-chip characterization unit shown in Fig. 11 is used to stimulate the TDC. Therefore, a single signal edge is propagated in two independent delay
chains providing a start and a stop signal to the TDC. The delay
of the first delay line is fixed, whereas the second delay line can
be tuned. A coarse tuning is achieved by inserting additional
delay elements into the signal path. A fine delay tuning with a
resolution below one buffer delay is enabled by an additional
analog delay line consisting of current starved inverters. The
TDC characteristics which includes all nonlinearity information is acquired by repeated TDC measurements with increasing
time delay along the second delay line. However, the absolute
time interval corresponding to a certain output word, and so the
absolute time resolution of the TDC cannot be extracted from
these measurements. For that purpose, the delays along both
delay lines and so the skew between the start and the stop signal
are to be measured separately. This is done by connecting both
delay lines in a ring-oscillator-like structure. The number of cy, e.g., derived from
cles during a well-known time interval
the system quartz, is counted. The skew between a signal propagated along the first and along the second delay line is then
determined according to
where
and
are the number of cycles of the first and
second ring-oscillator, respectively. The combination of these
two measurements results in a converter characteristic with absolute time reference. Fig. 12 shows the resulting step function which is measured for the 90 nm demonstrator [7]. With
a supply voltage of 1.2 V the resolution is 4.7 ps. Fig. 13 and
Fig. 14 show the integral nonlinearity (INL) and the differential nonlinearity (DNL), respectively. The maximum values of
LSB and
LSB show that the
4x interpolation was a reasonable choice and encourages for an
even higher resolution. A comparison of these measurement results with recently published TDCs is given in Table I. It can
be seen, that among the variation robust concepts the best resolution and linearity is achieved. The power and area values are
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Fig. 14. Measured differential nonlinearity.
Fig. 12. Measured converter characteristics.
Fig. 15. Sampling in the vicinity of the signal transition.
Fig. 13. Measured integral nonlinearity.
also very good. However, the comparison is difficult as it is often
not clear which peripheral components are included in the published values.
VI. RESOLUTION LIMITS
Local passive interpolation theoretically allows for an arbitrary fine resolution. Nevertheless, the actual resolution is limited by delay variations in the LPI delay chain and the variations of the sampling time. In this context only local variations
have to be considered as global variations are cancelled out either by a DLL approach or by normalization to the clock period
in the digital domain. Hence, the limitations due to local variations around the global process corner of interest are investiof the
gated next. As shown in Fig. 10, the blackout time
sampling latches is negative and the actual sampling instance is
. Both the arrival time
of the stop
given by
vary locally with the standard
signal and the blackout time
and
. Assuming uncorrelated Gaussian disdeviations
tributions, varies with
.
The inverter delays vary independently with a standard deviation . However, the signal arrival times are strongly correlated
as local delay variations accumulate along the chain. The signal
. If
arrival time after the th inverter varies with
a maximum integral nonlinearity of
is requested
with a confidence of three sigma this results in an upper res. Fig. 15 takes addiolution limit of
tionally the clock variation into account. All times are subject to
with mean value
and standard
Gaussian variations
deviation according to
HENZLER et al.: LOCAL PASSIVE TIME INTERPOLATION CONCEPT FOR VARIATION-TOLERANT HIGH-RESOLUTION TDC
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TABLE I
COMPARISON OF RECENTLY REPORTED TDC PERFORMANCES
VII. CONCLUSION
Fig. 16. Error probability of delay-line sampling under process variations.
where
describes the position of the stop edge
] and the local variawithin the interval [
tion of the
th inverter stage. The sampling instances are
(common path in the
composed of a correlated component
clock-tree) and an uncorrelated component (which reflects itself as an independent component in the blackout time variation
of each latch). Integrating the product of the independent probability density functions under the boundary conditions
and
results in the probability for correct operath
tion, i.e., the th latch samples a HIGH signal and the
latch a LOW signal.
. The
Fig. 16 shows scenario simulations for various
standard deviation of the sampling instance is normalized to
. For the delays
is assumed. It can be seen
that for resolutions below 5 [AU] no reliable decision is possible throughout the complete interval. With this investigation
the maximum acceptable variability of the delay elements and
the sampling instance can be estimated.
As the scaling of time resolution is superior to voltage resolution the need for high-resolution TDCs will certainly increase.
However, high-precision TDCs are not simply digital circuits
off-the-shelf which can be designed quickly or even synthesized automatically. As the operating principle is digital all the
advantages of digital circuits apply to the TDC. The design,
however, has to be done in a full-custom style, i.e., considering
the analog signal waveforms, signal synchronization, etc., and
keeping analog criteria like noise, power supply integrity and
matching in mind. Also technological aspects like variations
have to be taken into account. In this paper we have presented
a local passive time interpolation technique for high-resolution
TDCs with minimum latency and minimum dead-time. The feasibility, potential and resolution limitations have been demonstrated on the basis of a 90 nm, 1.2 V TDC implementation
with a resolution of 0.25 inverter delays. The maximum measured nonlinearity, namely the INL of only 1.2 LSB and the
DNL of only 0.6 LSB show that a sub-gate delay resolution
can be accomplished reliably with the local passive interpolation technique. This enables TDCs with a very high resolution
even if the delay scaling might decelerate in future low-power
technologies.
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Dominik Lorenz received the Dipl.-Ing. degree in
electrical engineering from the Technical University
of Munich (TUM), Germany, in 2007.
From 2006 to 2007, he was with Infineon
Technologies, Advanced Systems and Circuits
Department, where he worked on time-to-digital
converters. In 2007, he joined the Institute for
Electronic Design Automation, Technical University
of Munich, where he is currently working towards
the Dr.-Ing. degree. His research interests are in
reliability of integrated circuits, especially the
age-related performance degradation of digital circuits.
Stephan Henzler (M’06) received the Dipl.-Ing. degree in electrical engineering from the Technical University Munich (TUM), Germany, in 2002, and the
Dr.-Ing. degree in 2006.
From 2002 to 2005, he was with the Institute for
Technical Electronics, Technical University Munich,
where he worked on low-power digital integrated
circuit design and leakage reduction techniques. In
2005, he joined the Advanced Systems and Circuits
Department of Infineon Technologies AG, Munich,
where he works on high-speed/high-performance
digital integrated circuits, power-aware design and variability in deep-submicron CMOS technologies. He has authored or co-authored more than 30
technical publications, and holds several patents. He is a visiting Lecturer at
TUM for high-speed/high-performance digital circuit design.
Dr. Henzler is a member of the German Association of Electrical Engineers
(VDE) and the IEEE.
Ronald Kuenemund was born in Munich, Germany,
in 1958. He received the Dipl.-Ing. degree in electrical engineering from the Technical University of
Munich, Germany, in 1985.
In 1985, he joined the Central Research and Development department of Siemens AG in Munich, where
he worked on the design of CMOS circuits for digital signal processing. With the foundation of Infineon Technologies AG in 1999, he moved to the Corporate Logic Department where he worked on application-specific digital full-custom circuits. He is currently working as Senior Staff Engineer on CAD and methodology for digital
full-custom design in the Base Technology and Services department at Infineon,
Munich, Germany.
Siegmar Koeppe received the Diploma in electrical
engineering from the University of Hannover, Germany, in 1983.
After working three years as a research assistant in
the field of fault modelling and simulation of digital
CMOS circuits, he joined Siemens Research Labs,
Munich, Germany, in September 1987. His activities
cover concept engineering, circuit design, characterization, test strategies, and project management. He
has contributed to many projects, mainly in the area
of digital full-custom design. His current interests are
the design of high-speed circuits and topics of test and fault modeling and simulation. He holds around 24 patents worldwide.
In 2004, Mr. Koeppe was appointed “Principal Advanced Systems and
Circuits.”
Winfried Kamp received the Diploma in computer
science from the Technical University of Darmstadt,
Germany, in 1984.
He joined Siemens Research Labs, Munich,
Germany, in January 1985. Since 1999, he has been
with Infineon Technologies in several predevelopment departments. His activities cover concept
engineering, circuit design and verification, design
flow automation for digital full-custom design, and
project management. He has contributed to many
projects, mainly in the area of digital full-custom
design. His current interests are new design methodologies at the interface
between digital full- and semi-custom designs. He is head of the Digital
Full-Custom Design Department.
In 2001, Mr. Kamp was appointed “Principal Advanced Macros and Architectures.”
Doris Schmitt-Landsiedel (M’80) received the Dipl.
Ing. degree in electrical engineering from the Technical University of Karlsruhe, Germany, the diploma
in physics from the University of Freiburg, Germany,
and the Dr. rer. nat. degree from the Technical University of Munich, Germany.
She joined the Corporate Research and Development Department of Siemens AG, Munich, in 1981.
There she worked on scaling problems in MOS
devices and on the design of high-speed logic and
SRAM circuits. Since 1989, she has been Manager
of a research section with projects in future generation memory design, analog
and digital CMOS and BICMOS circuits, and design-based yield analysis.
Since 1996, she has been a Professor of electrical engineering and Director of
the Institute for Technical Electronics at the Technical University of Munich.
She is a member of the German Scientific Council. Her research interests are in
microelectronics including mixed-signal and low-power circuits design, design
for manufacturability, and circuits with novel devices.