Vol. 36, No. 1
Journal of Semiconductors
January 2015
GaN HEMT with AlGaN back barrier for high power MMIC switch application
Ren Chunjiang(任春江)Ž , Shen Hongchang(沈宏昌), Li Zhonghui(李忠辉),
Chen Tangsheng(陈堂胜), Zhang Bin(张斌), and Gao Tao(高涛)
National Key Laboratory of Monolithic Integrated Circuits and Modules, Nanjing Electron Devices Institute,
Nanjing 210016, China
Abstract: 0.25 m GaN HEMT with AlGaN back barrier for high power switch application has been presented. By
introducing AlGaN back barrier, the buffer layer breakdown voltage for the metal-organic chemical vapor deposited
AlGaN/GaN hetero-structure on 3-inch SiC substrate showed a considerable increment, which was nearly 4 and
2 of that for the conventional GaN buffer layer and GaN buffer layer with Fe doped, respectively. GaN switch
HEMTs with source to drain spacing of 2, 2.5, 3, 3.5 and 4 m were fabricated on the AlGaN/GaN epitaxial material
with AlGaN back barrier and estimated off state power handling for the GaN switch HEMTs were 25.0, 46.2, 64.0,
79.2, and 88.4 W, respectively. A demonstrator DC–12 GHz GaN SPDT MMIC switch was designed in reflective
series-shunt-shunt configuration based on the GaN HEMT, with a source to drain spacing of 2.5 m. The developed
SPDT MMIC switch showed a maximum insertion loss of 1.0 dB and a minimum isolation of 30 dB at a frequency
range of DC–12 GHz. A power handling capability of 44.1 dBm was achieved at 10 GHz for the MMIC switch
with continuous wave power compression measurement.
Key words: AlGaN/GaN; HEMT; back barrier; MMIC; high power; switch
DOI: 10.1088/1674-4926/36/1/014008
EEACC: 2570
1. Introduction
High power switches have been widely used in a variety
of RF transmitter/receiver (T/R) modules. High power handling capability and high isolation characteristics should simultaneously be met for high power switch devices. Previously, a PIN diode dominated as a switching device because of
its low-loss, high-isolation, and high-power handling capabilityŒ1 5 . However, for the PIN diode, which is a current-driven
device, the power consumption is large and this restricts its application in the case of power consumption sensitivity. In addition, a PIN diode is a vertical device and it is not easy for
high power MMICs switch designing or integrating with other
microwave components, such as low noise amplifiers, phase
shifters, etc., to form multi-function MMICs. MMIC switches
or multi-function MMICs are required for the miniaturization
tendency of modern microwave systems.
A field effect transistor (FET) consumes much less power
because it is a voltage-driven device. A FET is also a horizontal
device, which makes it convenient for use in MMIC switches
or multi-function MMICs designs, and high power MMIC
switches based on GaAs FETs have been reported with various configurationsŒ6 11 . These devices are restricted by the
breakdown voltage and current density, which means that the
power handling capability of GaAs FET based MMIC switches
is limited to several watts. A GaN HEMT, which is known as
a wide-band gap semiconductor device, has higher saturation
current density and breakdown voltage compared to conventional GaAs FETs. The power handling capability of the GaN
switches can be much higher than that of GaAs FET switches.
Recently, GaN high-power switches have also been reported,
and their power handling capability has exceeded 100 W at
S-band, 40 W at C-band, 20 W at X-band, and 10 W at KubandŒ11 14 .
GaN HEMTs with an AlGaN back barrier have been developed for high frequency use, such as Ka, V and W band power
MMICs application. The AlGaN back barrier exhibits a wider
band-gap compared to the conventional GaN buffer layer and
it improves 2DEG confinement in the channel and breakdown
voltage of the GaN HEMT. The enhanced breakdown voltage
brings benefits to GaN HEMT, not only for microwave power
application but also for switch operation.
In this paper, a 0.25 m GaN HEMT with AlGaN back
barrier for a high power switch application has been presented.
An AlGaN/GaN hetero-structure with an AlGaN back barrier was designed and deposited on 3-inch SiC substrate by
the metal-organic chemical vapor deposition (MOCVD). GaN
switch HEMTs for various source to drain spacing were fabricated and the HEMT with source to drain spacing of 2.5 m
exhibited a drain to gate breakdown voltage exceeding 70 V
and maximum drain saturation current of 1.3 A/mm. A DC–12
GHz single-pole double-throw (SPDT) switch was designed in
reflective series-shunt-shunt configuration based on the GaN
HEMT, with source to drain spacing of 2.5 m for demonstration purposes. The SPDT switch showed a maximum insertion
loss of 1.0 dB and a minimum isolation of 30 dB at a frequency
range of DC–12 GHz. Measured continuous wave power handling was 44.1 dBm at 10 GHz and 40 V control voltage.
2. Device structure and processing
For switch application FETs, the power handling of offstate and on-state in a 50  system may be estimated with the
† Corresponding author. Email: rencj2010@sina.com
Received 18 March 2014, revised manuscript received 3 August 2014
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© 2015 Chinese Institute of Electronics
J. Semicond. 2015, 36(1)
Ren Chunjiang et al.
Table 1. Effect of buffer layer type on the buffer breakdown voltage.
Buffer layer type
Breakdown voltage (V)
Conventional GaN
90
GaN with Fe doped
170
AlGaN back barrier
350
Figure 1. A schematic cross section of the AlGaN/GaN heterostructure
with AlGaN back barrier.
following equations:
Poff D MinŒ.Vbd
Vc /2 =25; .Vc
Vp /2 =25/;
2
Pon D 25Imax
;
(1)
(2)
where Vc is the control voltage, Vbd is the gate–drain breakdown voltage, Vp is the pinch-off voltage, and Imax is the maximum channel current. From Equation (1) it can be estimated
that the maximum power handling for a FET in off-state appears at Vc D .Vbd C Vp //2, which means the control voltage
is centered between the voltage of breakdown and pinch-off.
Thus, the maximum power handling Poff-max for a FET in offstate can be described as:
Poff
max
D .Vbd
Vp /2 =100:
(3)
To increase the off-state power handling capability, it
is necessary to improve the breakdown voltage of the FET.
Breakdown voltage can be boosted by enlarging the source–
drain spacing dimension, which simultaneously increases the
on resistance of the FET and brings more insertion loss. However, the increased insertion loss is not desirable. Another alternative way is to improve the FET’s breakdown voltage by
minimizing the leakage current of the buffer layer. For a GaN
HEMT, doping the GaN buffer layer with Fe atoms or introducing an AlGaN back barrier layer can effectively reduce device
leakage current. In this research, the AlGaN/GaN heterostructure with AlGaN back barrier is preferred.
A schematic cross section of the AlGaN/GaN heterostructure with AlGaN back barrier is shown in Figure 1. The epitaxial material consists of a 20 nm AlN nucleation layer, a 0.8 m
AlGaN back barrier layer, a 0.4 m GaN channel layer, a 20 nm
unintentionally doped (UID) AlGaN barrier layer with Al mole
fraction of 0.28, and a 2 nm UID-GaN cap layer. An AlGaN
back barrier layer instead of a traditional GaN buffer layer was
introduced to improve breakdown voltage of the buffer layer.
The mole fraction of the AlGaN back barrier layer was selected
to be 0.05 to avoid crystal relaxation. All epitaxial layers in Figure 1 were grown by MOCVD on 3-inch SiC substrate in the
Nanjing Electron Devices Institute. The 2-dimensional electron gas (2DEG) density and Hall mobility measured at room
temperature were 0.96 1013 cm 2 and 1950 cm2 /(Vs), respectively.
The breakdown voltage for buffer layers of conventional
GaN, GaN with Fe doped and AlGaN back barrier was characterized as shown in Table 1. The breakdown voltage was defined as buffer leakage current, which reached 1 A/mm for
Figure 2. Designed 6 100 m gate width GaN HEMT for characterization.
drain to source spacing of 4 m. The conventional GaN buffer
suffered high background carrier concentration, which can be
as high as 1 1017 cm 3 , which exhibited the lowest breakdown voltage of 90 V. With the Fe atoms doping compensation, the breakdown voltage for GaN buffer was increased to
170 V. The AlGaN back barrier showed the highest breakdown
voltage of 350 V, 4 and 2 of that for the conventional GaN
buffer layer and GaN buffer layer with Fe doped, respectively.
The GaN switch HEMT features a centered gate and a symmetric layout with respect to the source and drain. The gate
connected field plate was introduced to improve the breakdown
voltage by minimizing the peak electric field intensity near the
gate. GaN HEMTs with source drain spacing of 2, 2.5, 3, 3.5
and 4 m were designed for characterization. The gate width
was selected to be 6 100 m and the HEMT was in a common
gate configuration, with an 8 k gate resistor for decoupling
the circuit from the common gate ground. Figure 2 shows the
designed 6 100 m gate width GaN HEMT for characterization.
Device processing begins with Ohmic contact lithography
and electron beam evaporating Ti/Al/Ni/Au. After the Ohmic
metal lift-off, a rapid thermal annealing at 850 ıC in N2 ambient for 30 s was performed to realize source and drain electrode
Ohmic contact. A SiN passivation layer was deposited and the
device’s isolation was accomplished by BC ion implantation.
E-beam lithography was performed to define 0.15 m opening
patterns on DUV resist, which was followed by a reactive ion
etching (RIE) to get the 0.25 m gate footprint. After the DUV
resist stripping, a BCl3 based ICP gate recessing was carried
out to control the threshold voltage to around –3.2 V. The etching time dependence of threshold voltage showed a linearized
relationship with the slope of 12 mV/s between etching time,
and threshold voltage and a recessing time of 130 s was finally
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Ren Chunjiang et al.
Figure 3. (a) Three and (b) two terminal breakdown voltage for the GaN switch HEMTs.
performed. The second e-beam lithography was done to define
the top portion of the gate with the integrated field plate. Ni/Au
gate metal was evaporated and lifted off to form the 0.25 m
field plated gate. Gate passivation with SiN, contact pad opening, and electroplating for inter-connection were done to finish
the device’s fabrication.
3. GaN switch HEMT characterization
Three and two terminal breakdown voltage for the 2.5 m
drain source spacing GaN switch HEMT with buffer layers of
conventional GaN, GaN with Fe doped and AlGaN back barrier
are shown in Figures 3(a) and 3(b), respectively. Breakdown
voltage was defined as the point at which the leakage current
exceeds 1 mA/mm. As expected, the device with conventional
GaN buffer exhibited the lowest three and two terminal breakdown voltage and that with AlGaN back barrier showed the
highest breakdown voltage. The outstanding breakdown behavior of the AlGaN back barrier GaN HEMT is attractive for
high power switch application according to Equation (1).
On state resistance Ron and gate to drain breakdown voltage BVgd were characterized for the GaN switch HEMT in Figure 2 with AlGaN back barrier as shown in Table 2. The maximum RF power handling capability for off-state GaN HEMTs
is also estimated in Table 2 from Equation (3), the pinchoff voltage was selected to be 3:0 V for the maximum RF
power handling estimation. Ron increased almost linearly as
the source to drain spacing increased due to the introduced resistance by the epitaxial material. The gate to drain breakdown
voltage also increased but showed saturation with source to
drain spacing increasing. The saturation of breakdown voltage
with increasing of source to drain spacing can be attributed to
premature breakdown of GaN channel layer under the gate. The
un-doped GaN channel layer that suffered high background
carrier concentration exhibited the lowest breakdown voltage,
as shown in Table 1.
The design target in this paper for demonstrator DC–12
GHz GaN SPDT MMIC switch is to obtain a power handling
of over 43 dBm at a control voltage of 40 V with minimized
insertion loss. The GaN HEMT with source to drain spacing
of 2 m showed insufficient breakdown voltage for 40 V
control voltage operating. While for the HEMT with source
Table 2. Characteristics summary for the GaN switch HEMT with 2,
2.5, 3, 3.5, and 4 m drain source spacing.
SD spacing (m)
2
2.5
3
3.5
4
Ron (mm)
1.9
2.1
2.5
2.8
3.1
BVgd (V)
53
71
83
92
97
Poff-max (W)
25.0
46.2
64.0
79.2
88.4
to drain spacing of 3 m, the relative large on state resistance
would increase the insertion loss of the SPDT MMIC switch.
Finally, for the trade off, GaN HEMT with source to drain spacing of 2.5 m was chosen as candidate for the target SPDT
MMIC switch design.
Small signal S-parameters were characterized on a wafer
for the 6 100 m gate width GaN switch HEMT in Figure
2, with a source to drain spacing of 2.5 m. The frequency dependence of insertion loss and isolation extracted from small
signal S-parameters for on state (Vg D 0 V) and off state (Vg D
40 V), respectively, is shown in Figure 4. The HEMT showed
insertion loss less than 0.4 dB at a frequency range of DC–12
GHz. For power handling capability characterization, the 6 100 m gate width GaN switch HEMT was assembled in fixture. The insertion loss for on state was measured with the increasing of input power level at 10 GHz and Vg D 0 V and the
results are shown in Figure 5. The power handling capability
with 0 dB and 1 dB compression was 42.0 dBm and 44.5 dBm,
respectively. The P0dB value is very good agreement with theoretical predicted results from Equation (2), where the maximum current Imax is 1.3 A/mm for the developed GaN switch
HEMT.
4. GaN MMIC switch designing and characterizing
The DC–12 GHz GaN SPDT MMIC switch is designed in
a reflective series-shunt-shunt architecture, as shown in Figure
6. The circuit is designed for 43 dBm input power handling
and the control voltage is 40 V. The control voltage can be
applied from either side of the switch. The gate width for the
series and shunt GaN HEMTs should be carefully arranged.
As mentioned previously, all of the HEMTs in Figure 6 have a
source to drain spacing of 2.5 m. Series GaN HEMTs Q3 and
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Figure 6. Electric circuit schematic for the designed SPDT MMIC
switch.
Figure 4. Frequency dependence of insertion loss and isolation for the
6 100 m gate width GaN switch HEMT.
Figure 7. Photograph of the GaN SPDT switch.
Figure 5. Insertion loss versus input power for the 6 100 m gate
width GaN switch HEMT at 10 GHz.
Q4 are the same gate width of 6 100 m, which can meet
the goal for over 43 dBm power handling in both on state and
off state, as shown previously. The gate width for shunt GaN
HEMTs of Q2 and Q5 is 4 35 m, while for Q1 and Q6 is
4 120 m. Due to the lack of a suitable nonlinear transistor model, a linear equipment circuit model was used for the
GaN MMIC switch designing with the ADS circuit simulation
tool and the MMIC switch was finalized with EM simulation
utilizing momentum simulating module embedded in ADS. A
photograph of the fabricated GaN MMIC switch is shown in
Figure 7.
Small signal S-parameter data was characterized on a
wafer at a control voltage of 40 V for the DC–12 GHz GaN
MMIC switch. The measured small signal S -parameter results for insertion loss and isolation are plotted in Figure 8.
The GaN MMIC switch showed an insertion loss of less than
1.0 dB and an isolation of above 30 dB at a frequency range of
DC–12 GHz. Power handling capability was characterized in
fixture. Continuous wave (CW) power compression results at
10 GHz for various control voltage are shown in Figure 9. At a
control voltage of –20 V, the MMIC switch showed a premature power compression due to the control voltage limitation
according to Equation (1). For control voltage of 30 V and
Figure 8. Measured small signal insertion loss and isolation results for
the GaN SPDT switch.
40 V, the power handling capability was limited by the maximum current that the series GaN HEMT channel can offer.
The 1 dB power compression point of 44.1 dBm is achieved
at control voltage of 40 V for the GaN MMIC switch. The
P 1dB value of the GaN MMIC switch, accounting for the insertion loss of the circuits, achieved very good agreement with
the value that measured from the single 6 100 m gate width
GaN switch HEMT, as shown in Figure 5.
5. Conclusions
An AlGaN back barrier was introduced to develop GaN
switch HEMT and GaN high power SPDT MMIC switch. The
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Ren Chunjiang et al.
Figure 9. CW power data for the GaN SPDT switch at various control
voltage.
breakdown voltage and potential off state power handling capability for the GaN switch HEMT were considerably increased
by the AlGaN back barrier. A DC–12 GHz GaN SPDT MMIC
switch with a power handling capability of over 43 dBm was
designed, and the MMIC switch showed a maximum insertion
loss of 1.0 dB and a minimum isolation of 30 dB in the frequency range of DC–12 GHz. To our knowledge, this is the first
time that an AlGaN back barrier has been applied to switch applications and the results show the superiority of a GaN HEMT
with an AlGaN back barrier for high power RF switching applications.
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