Article
Effects of etching holes on
complementary metal oxide
semiconductor–
microelectromechanical systems
capacitive structure
Journal of Intelligent Material Systems
and Structures
24(3) 310–317
Ó The Author(s) 2012
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DOI: 10.1177/1045389X12449917
jim.sagepub.com
Wei-Hsiang Tu1, Wen-Chang Chu2, Chih-Kung Lee1,2,3,
Pei-Zen Chang2 and Yuh-Chung Hu4
Abstract
Etching the large area of sacrificial layer under the microstructure to be released is a common method used in microelectromechanical systems technology. In order to completely release the microstructures, many etching holes are often
required on the microstructure to enable the etchant to completely etch the sacrificial layer. However, the etching holes
often alter the electromechanical properties of the micro devices, especially capacitive devices, because the fringe fields
induced by the etching holes can significantly alter the electrical properties. This article is aimed at evaluating the fringe
field capacitance caused by etching holes on microstructures. The authors aim to find a general capacitance compensation formula for the fringe capacitance of etching holes by the use of ANSYS simulation. According to the simulation
results, the design of a capacitive structure with small etching holes is recommended to prevent an extreme capacitance
decrease. In conclusion, this article provides a fringing field capacitance estimation method that shows the capacitance
compensation tendency of the design of etching holes; this method is expected to be applicable to the design in capacitive devices of complementary metal oxide semiconductor–microelectromechanical systems technology.
Keywords
Actuator, sensor, autonomic structures
Introduction
To date, there have been numerous high-performance
and low-cost microsensors or microactuators fabricated
by microelectromechanical systems (MEMS) technology applied to the automobiles, biomedicine, and electronics industries. In the fabrication process of micro
devices, it is generally required to etch the sacrificial
layer under the microstructure to form a movable sensing or actuating microstructure: such a method is
called the release process. To completely and rapidly
etch the sacrificial layer, generally a lot of etching holes
are made on the microstructure to be released, which
enables the etchant to uniformly and rapidly permeate
into the sacrificial layer. The arrangement of etching
holes, including the density, size, shape, etc, depends
on the properties of the etchant, namely the etching
rate and selectivity between the materials of the microstructure and the sacrificial layer. However, etching
holes may alter the characteristics of the device, such as
mechanical properties, magnetic field, and electrical
field, which will significantly decrease the fabrication
yield of the micro devices. Some of the literature discusses the effect of etching holes. Rabinovich et al.
(1997) employed the so-called effective medium method
to investigate the effect of etching holes on the mechanical properties of microstructures. They made two identical sized unit modules, one with etching holes and the
1
Department of Engineering Science and Ocean Engineering, National
Taiwan University, Taipei, Taiwan
2
Institute of Applied Mechanics, National Taiwan University, Taipei,
Taiwan
3
President of Institute for Information Industry, Taipei, Taiwan
4
Department of Mechanical and Electromechanical Engineering, National
Ilan University, Ilan, Taiwan
Corresponding author:
Yuh-Chung Hu, Department of Mechanical and Electromechanical
Engineering, National Ilan University, No. 1, Sec. 1, Shen-Lung Road, Ilan
26041, Taiwan.
Email: ychu@niu.edu.tw
Tu et al.
311
other without, and compared the force–displacement
behaviors of the two modules by exerting a series of
normal and shear forces on them. Their results showed
that the mechanical properties of structures are highly
affected by etching holes. Fang et al. (2001) published a
theoretical model that showed that the size and density
of etching holes have a tremendous influence on the
coercivity of a microstructure. Elshurafa and El-Masry
(2006) employed a commercial finite element package
COMSOL to analyze the influence of the size and density of etching holes on the tunable range of MEMS
parallel plate variable capacitors. Their results showed
that the deviation of the tunable range affected by etching holes is around 16%. Elshurafa and El-Masry
(2007) discussed the effects of etching holes within one
plate in a parallel plate varactor or in a two-plate varactor; their results showed the effect of etching holes in
two-plate varactors is not extreme in regard to the
capacitance value. Fang et al. (2010) discussed the
effect of etching holes on variable capacitors and issued
an analytical model to compute the effect of etching
holes on pull-in voltage and capacitance. According to
the aforementioned literature, the influence of etching
holes on the characteristics of the devices needs to be
considered in design and fabrication.
For a long, flat plate whose length dimension is
much greater than its width, we can consider it as a
two-dimensional problem, Figure 1 shows a crosssectional view and geometric parameters of a long parallel plate capacitor. Apart from the uniform electrical
field under the plate, illustrated as the blue field lines in
Figure 1, fringe fields come from its top surface and two
sides, illustrated as red and green field lines in Figure 1.
Chang (1976) derived a fringe capacitance equation via
two times Schwartz–Christoffel conformal mapping
process and asserted that its deviation could be less than
1% to the finite element method as the ratio of thickness
to gap is larger than 1, namely b/g . 1. Vandermeijs
and Fokkema (1984) offered an empirical formula by
curve-fitting Chang’s equation as follows
" 0:25
0:5 #
b
b
h
Cunit length = e
+1:06
+ 0:77+ 1:06
g
g
g
ð1Þ
Figure 1. Schematic diagram and geometric parameters of
two-dimensional fringe fields.
Figure 2. Schematic diagram and geometric parameters of
three-dimensional fringe fields.
where b is the width of the plate, h is the thickness of
the plate, g is the gap between two electrodes, and e is
the permittivity. Compared with Chang’s equation, its
deviation is within 2% as b/g . 1 and 0.1 \ h/g \ 4,
and within 6% as b/g . 0.3 and h/g \ 10.
If the plate’s length and width are not different, then
three-dimensional (3D) fringe fields should be taken
into consideration. As shown in Figure 2, not only the
fringe fields from the top surface and the length sides
but also the ones from the width sides should be considered. Sakurai and Tamaru (1983) utilized the subarea method to develop an empirical formula for 3D
fringe capacitance
C
ðarea of the plateÞ
= 1:15
e
g
0:222
h
+ 1:40
ðcircumference of the plateÞ
g
0:728
h
g
ð2Þ
+ 4:12
g
Its deviation is within 10% under the condition of 0
\ b/L \ 1, 0.5 \ b/g \ 40, and 0.4 \ h/g \ 10.
Vandermeijs and Fokkema (1984) presented a formula
for calculating 3D fringe capacitance; yet it is imprecise. After surveying many literatures, we found that
no literature mentioned how to calculate the fringe
fields caused by etching holes, and only a few literatures mentioned the effects of etching holes on the variable capacitor (Elshurafa and El-Masry, 2006, 2007;
Fang et al., 2010).
Figure 3 shows the schematics of etching holes
through which the field lines of the top surface, as well
as the field lines from its inner-edges, pass. The etching
holes make the electrical fields much more complicated
than the case of a parallel plate capacitor and cause a
nonideal electrical field, which is difficult for capacitance assessment and invalidating of foregoing formulas. Therefore, this article provides a compensative
312
Journal of Intelligent Material Systems and Structures 24(3)
where CT is the total capacitance; Cp is an ideal capacitance of parallel plate, which can be calculated by the
well-known equation Cp = eA=g; and Cf is the fringe
field capacitance caused by the thickness and upper surface of a parallel plate capacitor. Similarly, the capacitance (CTe ) of a parallel plate capacitor with etching
holes can be expressed as
Figure 3. Schematic diagram of the fringe fields of etching
holes.
CTe = Cpe + Cfe
formula of assessment of etching hole capacitance for a
plate capacitor structure. For a capacitive MEMS
device, ANSYS is utilized to simulate the capacitance
under different sizes of etching holes, and an empirical
formula is derived. We expect that this result can provide designers with a rule to precisely estimate the
capacitance of a plate capacitor with etching holes.
Methodology
where Cpe and Cfe are the ideal capacitance and the total
fringe capacitance, respectively, for the parallel plate
with etching hole. Cpe can be represented as
Cpe = Cp Cp removed where Cp removed is the ideal capacitance of the etching hole area. Cfe can be represented as
Cfe = Cf + Cf hole where Cf hole is the fringe capacitance
from the etching hole. A correction term will be carried
out between capacitors with etching holes and those
without etching holes. The formula of capacitance correction can be signified as follows
DC = CTe CT = Cp
There are three parts to this research. First, the authors
comprehend the difference between a parallel plate
capacitor and parallel plate capacitor with etching
holes, and define the quantity of difference as capacitance correction term. Second, the authors employ
ANSYS to compute the capacitance of a parallel plate
capacitor and a parallel plate capacitor with etching
holes with different dimensions, and gain the capacitance correction term that is necessary for compensating the difference. Finally, the authors utilize the
capacitance correction term obtained under different
dimensions to acquire the relation between capacitance
correction and dimension via curve fitting, and provide
an empirical formula.
Analysis of capacitance
The literatures show that the fringe fields of a parallel
plate capacitor cannot be neglected in a micro scale.
The fringe field from the thickness and upper surface
of a parallel plate capacitor needs to be considered.
For this reason, the capacitance of micro parallel plate
capacitor can be expressed as
CT = Cp + Cf
ð3Þ
ð4Þ
removed
+ Cf
hole
ð5Þ
Simulation
The effect of etching holes is nonidentical under different dimensions, sizes, and densities of etching holes.
Hence, this research employs ANSYS to simulate the
influence of etching holes on the capacitance through
designing different sizes of plates and etching holes.
Usually, the alignment is an array, as shown in
Figure 4(a), so a unit module of an etching hole can be
taken out and simulated alone, as shown in Figure
4(b). Furthermore, the structure of an etching hole is
symmetric, so the simulation can function by merely
using a quarter of the structure and field. Table 1
shows the dimensions for simulation. The size of the
etching hole is defined as the ligament efficiencies (m)
meaning line width divided by the pitch of the etching
hole. As shown in Figure 5, the m is expressed as
m=
l
pitch
ð6Þ
The value of m is within 0–1; the bigger the m value,
the smaller the size of the etching hole. Simulation of
the parallel plate structure capacitor without etching
holes (m=1) is conducted under three different
Figure 4. (a) Schematic diagram of the capacitive structure and (b) schematic diagram of unit module.
Tu et al.
313
Table 1. Structure dimensions for simulation.
Length of the square
unit module (mm)
Thickness (mm)
Gap (mm)
Ligament efficiencies
4, 8, and 16
0.5
0.1, 0.2, 0.3, 0.4, 0.5, 0.75,
1.0, 1.5, 2.0, and 4.0
1, 0.7, 0.5, and 0.3
1 mm3). For the setting of c = 8 mm, h = 0.5 mm, m =
0.5 mm, and g = 1 mm, the amount of element is
around 95,000. After simulation, characteristics of the
structure’s electrical field and whole capacitance can be
obtained. The whole plate capacitance, CT, corresponding to various sizes, can be obtained via simulation,
and you can compute the ideal plate capacitance, CP,
to solve fringe field capacitance, Cf, as shown in
Table 3. Equivalently, the plate capacitance with etching holes, CTe , the ideal plate capacitance that subtracted the area of the etching holes from the full plate,
Cpe , and the fringe field capacitance caused by the thickness of the etching hole fringe can be obtained, as
shown in Table 4.
Results and discussion
Figure 5. Schematic of ligament efficiencies.
conditions (c = 4, 8, and 16), and the dimensions of
the plate structure capacitor with etching holes for
simulation are m = 0.7, 0.5, and 0.3. The thickness of
the plate (h) is 0.5 mm. The variable gap between two
plates (g) is within 0.1–4.0 mm. ANSYS element
Solid122 is employed in the electrical field analysis.
Due to the symmetry of the structure, the simulation
can be processed by taking just 1/4 of the model to
build the electrical field. The analyzed electrical field is
a cube with side lengths of 2c. The upper electrode is
involved in the field, and the lower electrode is the bottom of the simulated field, as shown in Figure 6(a).
The setting for the mesh size is shown in Figure 6(b)
and Table 2 (e.g. the element size of X region from 0 to
c/2 + 0.1, Y region from g + h + 0.1 to g + h +
2.1, and Z region from c/2 + 2.1 to 2c is 0.1 3 0.5 3
Based on the results of the simulations, when the gap
increases, the ideal plate capacitance in the whole capacitance decreases, and the fringe field capacitance in the
whole capacitance increases; this indicates that the
effect of the fringe field is more prevalent. Afterward,
just like the procedure for the capacitance correction,
the plate structure capacitance with etching holes, CTe ,
and whole plate structure capacitance, CT, can be
resolved, and the subtraction of these two values is the
capacitance correction term DC. As shown in Figure 7,
under identical ligament efficiencies (m = 0.5), the
larger the unit module, the greater the capacitance correction. Taking into account the relation with the gap
of electrodes, the capacitance correction and gap are
roughly in inverse proportion.
Considering the same area of square plates and cutting out the same area of etching holes with different
sizes and densities, ligament efficiencies of m = 0.5, the
samples include 16 unit modules with 4 mm for each
Figure 6. (a) Scheme of analyzed electrostatic field and (b) scheme of mesh size distribution.
314
Journal of Intelligent Material Systems and Structures 24(3)
Table 2. Mesh size in three distributions.
X region
Y region
0–c/2 + 0.1
c/2 + 0.1–c/2
c/2 + 2.1–2c
0–c/2 + 0.1
c/2 + 0.1–c/2
c/2 + 2.1–2c
0–c/2 + 0.1
c/2 + 0.1–c/2
c/2 + 2.1–2c
0–c/2 + 0.1
c/2 + 0.1–c/2
c/2 + 2.1–2c
0–c/2 + 0.1
c/2 + 0.1–c/2
c/2 + 2.1–2c
0–c/2 + 0.1
c/2 + 0.1–c/2
c/2 + 2.1–2c
0–c/2 + 0.1
c/2 + 0.1–c/2
c/2 + 2.1–2c
0–c/2 + 0.1
c/2 + 0.1–c/2
c/2 + 2.1–2c
0–c/2 + 0.1
c/2 + 0.1–c/2
c/2 + 2.1–2c
0–g + h + 0.1
g + h + 0.1–g + h + 2.1
0–c/2 + 0.1
g + h + 2.1–2c
0–g + h + 0.1
c/2 + 0.1–c/2 + 2.1
g + h + 0.1–g + h + 2.1
g + h + 2.1–2c
0–g + h + 0.1
g + h + 0.1–g + h + 2.1
c/2 + 2.1–2c
Mesh size (mm3)
Z region
g + h + 2.1–2c
Table 3. Simulation results of parallel plate capacitor.
0.1 3 0.1 3 0.1
0.1 3 0.1 3 0.5
0.1 3 0.1 3 1
0.1 3 0.5 3 0.1
0.1 3 0.5 3 0.5
0.1 3 0.5 3 1
0.1 3 1 3 0.1
0.1 3 1 3 0.5
0.1 3 1 3 1
0.5 3 0.1 3 0.1
0.5 3 0.1 3 0.5
0.5 3 0.1 3 1
0.5 3 0.5 3 0.1
0.5 3 0.5 3 0.5
0.5 3 0.5 3 1
0.5 3 1 3 0.1
0.5 3 1 3 0.5
0.5 3 1 3 1
1 3 0.1 3 0.1
1 3 0.1 3 0.5
1 3 0.1 3 1
1 3 0.5 3 0.1
1 3 0.5 3 0.5
1 3 0.5 3 1
1 3 1 3 0.1
1 3 1 3 0.5
13131
+ 2.1
+ 2.1
+ 2.1
+ 2.1
+ 2.1
+ 2.1
+ 2.1
+ 2.1
+ 2.1
Table 4. Simulation results of parallel plate capacitor with
etching hole.
Length of square unit module (mm): 16 mm
Gap (mm)
CP (fF)
CT (fF)
Cf (fF)
0.10
0.20
0.30
0.40
0.50
0.75
1.00
1.50
2.00
4.00
22.666240
11.333120
7.555413
5.666560
4.533248
3.022165
2.266624
1.511083
1.133312
0.566656
24.313873
12.747548
8.848028
6.879083
5.687291
4.078149
3.259652
2.424500
1.996637
1.340618
1.647633
1.414428
1.292615
1.212523
1.154043
1.055984
0.993028
0.913418
0.863325
0.773962
side length, 4 unit modules with 8 mm for each side
length, and 1 unit module with 16 mm for its side
length, as shown in Figure 8. The total capacitance correction has been discussed under different circumstances (high density, small etching holes, and low
density, large etching holes). The result shown in
Figure 9 is that the longer the length of unit etching
holes, the larger the capacitance correction. In contrast,
even though it takes more small etching holes to attain
the same area, the summation of all capacitance corrections is still less. Thus, a result can be inferred that the
influence of small etching holes on the whole capacitance is small. When the gap between the electrodes
Length of square unit module (mm): 16 mm and ligament
efficiencies (m): 0.5
Gap (mm)
CPe (fF)
CTe (fF)
Cfe (fF)
0.10
0.20
0.30
0.40
0.50
0.75
1.00
1.50
2.00
4.00
16.999680
8.499840
5.666560
4.249920
3.399936
2.266624
1.699968
1.133312
0.849984
0.424992
19.215937
10.366146
7.348762
5.810360
4.871035
3.586887
2.922502
2.231021
1.868358
1.293617
2.216257
1.866306
1.682202
1.560440
1.471099
1.320263
1.222534
1.097709
1.018374
0.868625
increases, the summation of capacitance correction in
these three conditions is decreasing.
Curve fitting
In the above-mentioned simulation for the effect of
etching holes, this research employs Mathematica to
curve-fit the results of the simulation. The empirical
formula of capacitance correction term of unit etching
hole plate capacitor is deduced as follows
Tu et al.
315
0
Capacitance difference (fF)
0
∆C (fF)
–1
–2
–3
–4
c = 4 (µm)
c = 8 (µm)
c = 16 (µm)
–5
–1
–2
–3
–4
c = 4 (µm)
c = 8 (µm)
c = 16 (µm)
–5
–6
–6
0
1
2
3
4
0
5
1
2
Gap (µm)
Figure 7. Capacitance correction term DC with m = 0.5; c = 4,
8, and 16; and variable gap.
CEH = C ð1 mÞ
3
4
5
Gap (µm)
Figure 9. Capacitance correction term DC with the same area
of square plates, cutting out the same area of etching holes with
different sizes and densities.
ð7Þ
0.0
!
0:025
h
+ 44:940CEH
41:314CEH
DC = e g
g
2
CEH
The first term indicates the plate capacitance of the
area of etching holes. The second term indicates the
capacitance caused by the fringe field on the thickness
of the etching holes. When the structure is without etching holes (CEH = 0), the capacitance correction is zero.
Because a small plate capacitor has small etching holes,
the capacitance correction is small. The plate capacitance is smaller when the plate gap is larger and the
capacitance correction decreases. According to the literature (Rebeiz, 2003), when the diameter of the etching
hole less than 3–4 times the gap of the electrodes, the
effect of the etching holes can be ignored, owing to the
compensation of the fringe electric field for etching
holes. Synthesizing all the above factors, this research
∆C (fF)
ð8Þ
–0.1
–0.2
–0.3
μ = 0.7, 2.5<h/g<5 Simulation
μ = 0.7, 2.5<h/g<5 Empirical formula
μ = 0.5, 1.25<h/g<5 Simulation
μ = 0.5, 1.25<h/g<5 Empirical formula
μ = 0.3, 1<h/g<5 Simulation
μ = 0.3, 1<h/g<5 Empirical formula
–0.4
–0.5
–0.6
0
1
2
3
4
5
6
h/g
Figure 10. Comparison of analytical solution and ANSYS
simulation with c = 4.
neglects small and trivial values. Figures 10 to 12 show
the comparison of results between the analytical solution of formula and the simulation of ANSYS.
Figure 8. Schematic of square plates, cutting out the same area of etching holes with different sizes and densities.
316
Journal of Intelligent Material Systems and Structures 24(3)
30
0.0
Capacitance (fF)
–0.5
∆C (fF)
Simulation
Ideal parallel plate
(Chuang, 2011)
This work
25
–1.0
–1.5
μ = 0.7, 1.25<h/g<5 Simulation
μ = 0.7, 1.25<h/g<5 Empirical formula
μ = 0.7, 0.67<h/g<5 Simulation
μ = 0.7, 0.67<h/g<5 Empirical formula
μ = 0.7, 0.5<h/g<5 Simulation
μ = 0.7, 0.5<h/g<5 Empirical formula
–2.0
–2.5
20
15
10
5
0
–3.0
0
1
2
3
4
5
6
0
h/g
2
h/g
3
4
5
6
Figure 13. Comparison of capacitance with different gaps
obtained from different models.
Figure 11. Comparison of analytical solution and ANSYS
simulation with c = 8.
holes. The alignment of etching holes is usually an
array; therefore, the quantity of etching holes can easily
be calculated. Assuming there is a sample of unit etching holes (length of 16 mm, thickness of 0.5 mm, and
ligament efficiencies m = 0.5). Now the sample is computed by three methods as follows:
0
–2
∆C (fF)
1
–4
–6
μ = 0.7, 0.67<h/g<5 Simulation
μ = 0.7, 0.67<h/g<5 Empirical formula
μ = 0.5, 0.33<h/g<5 Simulation
μ = 0.5, 0.33<h/g<5 Empirical formula
μ = 0.3, 0.25<h/g<5 Simulation
μ = 0.3, 0.25<h/g<5 Empirical formula
–8
–10
1.
2.
3.
Ideal capacitance formula;
3D structure capacitance formula;
3D structure capacitance with effect of etching
holes.
–12
0
1
2
3
4
5
6
h/g
Figure 12. Comparison of analytical solution and ANSYS
simulation with c = 16.
This empirical formula of capacitance correction can
be combined with 3D plate capacitance computation.
Then, the 3D plate capacitance with etching holes can
be appraised as follows
( " 0:23
0:23 #
b
h
b
CTotal = e
+ 0:73
1:06 + 3:31
g
g
h
" 0:86 #)
0:18
h
h
L + e 4:2
b + 2:74
g
g
g
(
! )
0:025
CEH 2
h
+ e + 44:940CEH
41:314CEH n
g
g
ð9Þ
The first term comes from the literature (Chuang
et al., 2011), empirical formula for computing plate
capacitance. The second term is the capacitance correction in this research. The n is the quantity of etching
Then, we compare these with the results of an
ANSYS simulation, as shown in Figure 13 and Table 5.
According to the results, the best appraisal of etching
hole structure is with the third method (error \ 1%);
the smaller the gap, the better the appraisement compared with other methods.
Conclusion
This research utilized ANSYS to simulate the effect of
etching holes for plate capacitor structures with etching
holes. Under the conditions of cutting the same areas
for etching holes, the small size of an etching hole
means a high etching hole density, which causes minor
capacitance changes. When dimension ranges m = 0.7,
4 \ c \ 16, and 0.25 \ h/g \ 5, the capacitance variation is less than 10%. This research also provides an
empirical formula for the compensation of etching hole
capacitance, combined with a 3D true thickness formula of plate capacitance. The mean error is less than
1%, which shows that this formula can be more accurate than other formulas (mean error . 10%). This
empirical formula is able to provide designers with a
criterion to appraise the effect of etching holes
promptly and precisely.
Tu et al.
317
Table 5. Comparisons of capacitances between simulation and formulae.
h/g
Simulation
Chuang (2011)
fF
fF
24.2291
12.7037
8.8257
6.8706
5.6886
4.0946
3.2843
2.457
2.0319
1.3621
5
19.2159
2.5
10.3661
1.6667
7.3488
1.25
5.8104
1
4.871
0.6667
3.5869
0.5
2.9225
0.3333
2.231
0.25
1.8684
0.125
1.2936
Mean error %
Ideal parallel plate
This study
Error %
fF
Error %
fF
Error %
26.09
22.55
20.1
18.25
16.78
14.15
12.38
10.13
8.75
5.29
15.447
16.9997
8.4998
5.6666
4.2499
3.3999
2.2666
1.7
1.1333
0.85
0.425
211.53
218
222.89
226.86
230.2
236.81
241.83
249.2
254.51
267.15
235.898
18.9501
10.201
7.2346
5.7286
4.8121
3.5638
2.9198
2.2498
1.8969
1.316
21.38
21.59
21.55
21.41
21.21
20.64391
20.091793
0.84291
1.53
1.73
20.377279
Funding
This study was supported by the National Science Council of
Taiwan through grant number NSC 100-2628-E-197-001MY3.
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