UNIVERSITY OF WATERLOO
Department of Electrical and Computer Engineering
E & CE 231
ELECTRONIC DEVICES
LAB. MANUAL
Spring 2007
Introduction - 1
Contents
• General Instructions and Introduction
• LS # 1. The Planar Fabrication Process and Test Measurements
• LS # 2. Introduction to Bipolar Junction Transistors
• LS # 3. Introduction to Field-Effect Devices
• LS # 4. Introduction to CAD using the BIPOLE Program
Introduction - 2
General Instructions
Mani Vaidyanathan,
Paul Hayes
July 27, 2005
1.
Introduction
Welcome to the E&CE 231 laboratory! There are four lab studies to be done in this course:
in lab 1, you will learn how semiconductor devices are fabricated; in lab 2, you will meet
field-effect devices; in lab 3, you will study some fundamental properties of the bipolar
transistor; and in lab 4, you will be introduced to computer-aided design of semiconductor
devices. The purpose of these labs is threefold: to reinforce the theory that you learn in
lectures; to give you some experience with measurement and instrumentation; and to help
you improve your documentation and analysis skills.
Students should perform labs in teams of two. A detailed lab schedule, including available
time slots, report due dates, and the lab test will be given out during the first week of
lectures. Typically, labs 1 and 2 are performed before midterm week, and labs 3 and 4 are
performed after midterm week.
The E&CE 231 labs have recently been totally revised. A lot of background information has
been added with the goal of making the lab exercises more meaningful and easier to perform.
However, in order to get maximum benefit from this information, you should read through
each write-up before going to the lab; moreover, you should keep track of your questions
and then ask a teaching assistant or the lab instructor for clarification during the lab period.
Your feedback on these revised labs is welcome! Please let us know what you think so that
we can make further improvements for future students. Feel free to offer your suggestions to
the course instructor, or send your comments by way of electronic mail to
phayes@ece.uwaterloo.ca.
Introduction - 3
2.
Lab Notebooks
Please use a bound notebook for all lab studies, and adhere to the following guidelines:
1. Make sure your name and student number is clearly written on the front of the book.
Also include the name and student number of your lab partner.
2. Number and date all pages. Do not leave any blank pages, remove any pages, nor add any
pages.
3. Reserve the first few pages for an index showing the lab study number and title, date
performed, page number, mark achieved, and signature of the teaching assistant.
4. Make sure you get a teaching assistant or the lab instructor to initial your work at the end
of each lab session. There may be some lab mark penalty if the lab work is not signed
before you leave your lab session.
5. Follow good engineering practice in making all entries; for example, always indicate
units, title all tables and graphs, and keep your work tidy.
You must use a hardcover notebook. For each lab study, only one lab report is required from
a team of two students; however, both students must assist equally in performing the
experiment, taking readings, and working out the results. All work must be done by hand,
in ink. Remember that your laboratory notebook is meant to be a clear, concise but
unambiguous record of what you did and what you observed in the laboratory - together with
your comments "as appropriate". If we feel that comments were appropriate, but you made no
comments, then your marks will reflect this. Critically analyze all of your observations.
The date of the lab test will be posted.
3.
In the Lab
Please note the following rules when working in the lab:
1. There is no smoking, eating, or drinking allowed.
2. Proper footwear must be worn at all times.
3. Apparatus should never be borrowed from other benches.
4. Apparatus should be left in a tidy condition.
We thank you for your cooperation.
Introduction - 4
Laboratory Study 1:
The Planar Fabrication Process and Test Measurements
Mani Vaidyanathan1
1. Introduction
Welcome to the world of semiconductor devices! In this lab, you'll learn a little about how
diodes and transistors are fabricated. You'll get a chance to probe actual devices, fabricated
here at the University of Waterloo, and perform simple test measurements on them. The
purpose of the lab is not only to give you an idea of how microelectronic devices and circuits
are made, but also to introduce you to many of the terms and concepts important in
semiconductor device engineering.
2. Before the Lab
Your prelab assignment is to read and familiarize yourself with the lab. You'll find that many
of the terms and concepts are completely new to you. Keep track of the things you find
confusing, and then ask a teaching assistant or the lab technologist for clarification during the
lab period. Alternatively, you might want to check the references listed at the end of the lab.
3. Background
Before doing any measurements, you need to understand the basics. We'll review how
semiconductor devices are made, and then consider some of the units and dimensions
commonly used in semiconductor engineering.
3.1 How are semiconductor devices made?
The Planar Fabrication Process
The most common semiconductor material used for electronic devices today is silicon.
Devices are fabricated in silicon by means of a planar process. This process is based on the
diffusion of impurities into the surface of a single-crystal silicon wafer. The impurities make
regions of the silicon either rich in holes or electrons, the two current-carrying particles found
in semiconductors. Regions rich in holes are called p-type, and regions rich in electrons are
called n-type. When a p-type region meets an n-type region, a structure called a pn junction
is formed. This structure is the basic building block of all semiconductor devices.
1
Based on exercises originally developed by Mr. I. R. Grant and Prof. D. J. Roulston.
LS #1 - 1
A diode is formed using just a single pn junction. A simplified cross-section of a planar
diode is given in figure 1. From your study of basic circuit theory, you may already be
familiar with the current-voltage law for such a planar diode:
Id = IS (exp ( Vd / m Vt ) - 1)
Equation 1
where Id is the current through the diode, Vd is the voltage applied across its terminals, Vt is
the thermal voltage, and IS and m are parameters related to the properties of the diode.
However, you probably don't know how the structure in figure 1 leads to this law, or how the
constants IS and m are related to the physical properties of that structure. These are some of
the things that you'll learn in this course!
Figure 1: Sketch of a planar diode, which is actually just a single pn junction.
So how is a planar diode made? The procedure begins with an engineer defining a set of
mask diagrams, such as those shown in figure 2. These diagrams, which are drawn using a
CAD program, define the type of fabrication to be performed on a given area of the silicon.
The mask diagrams are used to create a set of glass processing masks. Using the processing
masks, the fabrication steps, which are illustrated in figures 3 and 4, are as follows:
Figure 2: The masks needed to make the diode of figure 1.
LS #1 - 2
Figure 3: Pictures of the silicon wafer after each processing step. The substeps used in
step 2 are illustrated in figure 4.
LS #1 - 3
Figure 4: Pictures of the silicon wafer after each substep in step 2.
1)
2)
3)
4)
A layer of silicon dioxide SiO2 is thermally grown all over the surface of an n-type
silicon wafer.
The oxide is selectively etched using a process called photolithography. This
involves the following substeps:
a)
The surface of the silicon dioxide is coated with a film of material called
photoresist. The resist is lightly baked to drive off solvents and to dry it.
b)
The p-diffusion processing mask is placed near the coated wafer and exposed
to ultraviolet light. The light degrades exposed photoresist.
c)
The slice is rinsed in a solvent which removes the degraded photoresist.
d)
Exposed silicon dioxide is etched in buffered hydrofluoric acid.
e)
The remaining layer of photoresist is removed.
The slice is cleaned and placed in a deposition furnace. A thin layer of boron, which
is an impurity known to make silicon p-type, is deposited and just diffused into the
surface of the silicon. Note that the boron diffuses into the silicon only where the
oxide has been etched away. This is why processing steps 1 and 2 were needed!
During the deposition, a thin layer of oxide rich in boron, called borosilicate glass, is
formed on the surface of the silicon, but is etched off.
The slice is transferred to a diffusion furnace. The deposited boron surface layer is
driven more deeply into the wafer; in other words, the boron atoms are made to
diffuse more deeply into the silicon, converting it to p-type material rich in holes.
LS #1 - 4
5)
6)
7)
8)
Since the amount of boron available is fixed from step 3, the concentration of boron
at the wafer surface falls while that at regions below the surface increases. During the
diffusion cycle, a new layer of oxide is grown at the surface. The oxide forms a seal
preventing boron atoms from escaping, and it is needed to allow further selective
processing of the silicon.
Contact windows are etched in the oxide. This step is the same as step 2 except that
the contact window processing mask is used, and it is aligned with respect to the
pattern already on the surface of the silicon.
The slice is cleaned and placed in a vacuum deposition system. A layer of aluminum
is deposited all over the surface.
Aluminum is selectively removed, in a manner similar to step 2, using the metal
processing mask, and the slice is baked to bond the aluminum to the silicon surface.
The wafer is then ready for test measurements.
The wafer, or slice, actually contains several copies of the devices to be fabricated.
For the fabrication of a single planar diode, this means several copies of the diode
would actually be made all over the wafer. Therefore, the last step is usually to dice
the wafer into individual chips, every chip having one copy of the devices to be
fabricated. Each chip is then packaged in a hermetically sealed case. Bonding wires
are used to connect the chip to pins, and the pins are brought out of the package for
connection to the outside world.
For this lab, step 8 is omitted, and you'll work with entire wafers that have undergone various
degrees of processing between steps 1 and 7.
What about transistors? How are they made? A planar npn bipolar transistor may be made
by performing extra processing between steps 4 and 5 listed above. The extra processing is
needed to create a region extremely rich in electrons, called n+-type material, and requires the
use of an impurity known to make silicon n-type, such as phosphorus. The n+ region is
created within the p region formed after step 4. Figure 5 shows a simplified cross-section of
a planar npn bipolar transistor. The fabrication required to make a field-effect transistor is
more complicated, and you'll learn about these devices later. In this lab, we'll stick to diodes
and npn bipolar transistors.
LS #1 - 5
Figure 5: A simplified cross-section of a planar npn bipolar transistor. The emitter
contact is E, the base contact is B, and the collector contact is C.
Real Devices
Although the above description is enough for you to get a basic idea of how diodes and
transistors are made, it doesn't quite tell the whole story. To illustrate, let's have a brief look
at the construction of a real npn bipolar transistor. Real transistors (and diodes) can be
divided into those that are discrete, and those that are integrated.
Figure 6: A cross-section of a real discrete npn bipolar transistor. The figure is not
drawn to scale; in reality, the n+ substrate is about 10 to 100 times the thickness of the
epitaxial layer.
A device is discrete if it is the only device fabricated on a chip. Figure 6 shows a crosssection of a real discrete npn bipolar transistor. Compare it to the simple sketch in figure 5.
Note that the n-type material in figure 5 actually refers to what is called an n epitaxial layer.
This material, moderately rich in electrons, is grown on top of a thick n+ substrate. The
LS #1 - 6
substrate provides mechanical support and allows for a good electrical contact --- note the
difference in location of collector contacts between figures 5 and 6.
Figure 7: A cross-section of a real integrated npn bipolar transistor. In reality, the psubstrate is much thicker than shown.
Integrated devices exist with several other devices on the same chip. All the devices on the
chip are combined to form a circuit, called an integrated circuit. Figure 7 shows a crosssection of a real integrated npn bipolar transistor. Compare it to the simple sketch in figure 5.
As in the case of the discrete device, the n-type material in figure 5 corresponds to an n
epitaxial layer. However, unlike the discrete device, the epitaxial layer is grown on top of an
n+ buried layer that is diffused into a p- substrate. The buried layer, it turns out, is needed to
lower the collector resistance of the transistor. The p- substrate, in conjunction with deep p+
walls surrounding the device, provides a method to isolate the transistor from other devices
on the chip. Isolation is achieved by ensuring that all the pn junctions formed between the n
epitaxial layer, n+ buried layer, p+ walls, and p- substrate are always under reverse bias, since
a pn junction under reverse bias conducts virtually no current. Finally, an n+ diffusion,
usually made at the same time as the n+ emitter diffusion, is required at the location of the
collector lead. This diffusion is needed because it turns out that a good electrical contact
cannot be made between metal and the epitaxial layer.
You're probably wondering how the heck the structures in figures 6 and 7 end up working as
bipolar transistors. Stay tuned. Before the end of this course, you'll find out!
LS #1 - 7
3.2 A Note on Dimensions and Units
It is conventional to use a variety of mixed units to describe the various dimensions
encountered in semiconductor engineering. You should be prepared to meet any of them.
The dimensions of a single semiconductor device, such as a diode or transistor, are typically
quoted in microns (µm). One micron is equal to 10-6 m. For example, high-performance
bipolar transistors typically have emitter diffusions that are a few microns wide. Think about
this! Can you see how it is thus possible to have a huge number of these devices on a single
chip of area, say, the size of your fingertip?
Oxide thickness is usually given in angstroms (Å). One angstrom is equal to 10-10 m.
Sometimes, oxide thickness is also quoted in fractions of a micron. For example, an oxide
layer with thickness 2.0 × 10-7 m may be referred to as being 2000 Å or 0.2 µm thick.
Overall chip sizes are often quoted in mils. One mil is 10-3 inches. Therefore, 25.4 µm = 1
mil. The mil, being nonmetric, is an inconvenient unit. You won't encounter the mil too
much in this course.
A unit you will have to get accustomed to using is the centimeter. At first, you may find this
awkward, since when studying basic electricity and magnetism you more commonly used the
meter. In semiconductor engineering, the centimeter is preferred over the meter. For
example, free carrier concentrations, namely the number of electrons or holes available for
current conduction, are quoted as a number per cubic centimeter; thus, one might give the
free hole concentration as p = 1017 cm-3, meaning there are 1017 holes per cubic centimeter
available for conduction. Even quantities that you are familiar with are quoted in terms of the
centimeter rather than the meter. For example, the electric field is quoted in units of V/cm as
opposed to V/m, and resistivity is quoted in units of Ω • cm instead of Ω • m. Be careful!
4. In the Lab
4.1 Devices for this Lab
To keep things simple for this lab, we made neither real discrete nor integrated devices such
as those in figures 6 and 7. Rather, we followed the simplified planar process outlined in the
first part of section 3.1, that is, the process illustrated in figures 3 and 4.
Each chip on the completed wafer contains many more devices than you will actually use in
this lab. Figure 8 shows the patterns you will probe. You'll have to locate these when you
look through the microscope at the probing station.
LS #1 - 8
Figure 8: Patterns you will probe on the test chip. Note: The npn transistor is presently
unavailable.
LS #1 - 9
4.2 Identification of Wafers
There are five wafers to be used in this lab. Wafers 1 to 3 are illustrated in figure 9, and each
corresponds to a different stage of the processing cycle given in section 3.1, as follows:
wafer 1 has the oxide from step 1 all over it;
wafer 2 has the oxide from step 4 all over it;
wafer 3 has the combined oxide from the growth in steps 1 and 4 all over it.
Wafer 4 is just doped silicon. Wafer 5 is the completed wafer with all devices on it.
Figure 9: Illustration of wafers 1 to 3.
4.3 Structure of the Lab Exercises
In each of the exercises below, you will examine a different aspect of semiconductor device
fabrication and characterization. For each exercise, there is a description and questions.
Read the description, which contains all the background information you need, and then
answer the questions.
4.4 Estimation of Oxide Thickness
Description
From the discussion in section 3.1, it is obvious that thermally grown oxide SiO2 plays a
crucial role in the planar fabrication process. A critical parameter of interest is the oxide
thickness. For example, we may want to know if a given oxide layer is thick enough to act as
an effective barrier to diffusing impurity atoms, or we may require the thickness of a layer in
order to estimate how long to apply an etching solution to remove it.
LS #1 - 10
There are two ways to grow oxide. Dry oxide is a term applied to SiO2 grown by the
following reaction:
Si + O2 ⇒ SiO2
Equation 2
Wet oxide is a term applied to SiO2 grown with steam:
Si + 2H2O ⇒ SiO2 + 2H2
Equation 3
Both the above reactions are carried out at high temperatures, typically between 800 and 1200
degrees celsius.
Figures 10 and 11 show graphs of oxide thickness as a function of growth time; note that the
top curve for each temperature applies to the wafers in this lab. If the growth method,
temperature, and time are known, then these graphs can be used to get an estimate of the
resulting oxide thickness. This estimate can be improved by observing the color of the oxide
and consulting the chart in figure 12.
Figure 10: Graph of oxide thickness versus growth time for dry oxide.
LS #1 - 11
Figure 11:
Graph of oxide thickness versus growth time for wet oxide.
LS #1 - 12
Film
Thickness
(Microns)
0.050
0.075
0.100
Colour and Comments
0.125
0.150
0.175
0.200
Royal Blue
Light blue to metallic blue
Metallic to very light yellow-green
Light gold or yellow -- slightly
metallic
Gold with slight yellow orange
Orange to melon
Red-violet
Blue to violet-blue
Blue
Blue to blue-green
Light green
Green to yellow-green
Yellow-green
Green-yellow
Yellow
Light orange
Carnation pink
Violet-red
Red-violet
Violet
Blue-violet
Blue
Blue-green
Green (broad)
Yellow-green
Green-yellow
Yellow to “yellowish (Not yellow
but is in the position where yellow
is to be expected. At times it
appears to be light creamy grey or
metallic)
Light orange or yellow to pink
boarderline
0.225
0.250
0.275
0.300
0.310
0.325
0.345
0.350
0.365
0.375
0.390
0.412
0.426
0.443
0.465
0.476
0.480
0.493
0.502
0.520
0.540
0.560
0.574
0.585
Tan
Brown
Dark violet to red violet
Film
Thickness
(Microns)
0.600
0.630
0.680
Colour and Comments
0.720
0.77
0.80
0.82
Carnation pink
Violet-red
“Bluish” (Not blue but borderline
between biolet and blue-green. It appears
more like a mixture between biolet-red
and blue-green and over-all looks greyish)
Blue-green to green (quite broad)
“Yellowish”
Orange (rather broad for orange)
Salmon
0.85
0.86
0.87
0.89
0.92
0.95
0.97
0.99
1.00
1.02
1.05
1.06
1.07
1.10
1.11
1.12
1.18
1.19
1.21
1.24
1.25
1.28
1.32
Dull, light red-violet
Violet
Blue-violet
Blue
Blue-green
Dull yellow-green
Yellow to “yellowish”
Orange
Carnation pink
Violet-red
Red-violet
Violet
Blue-violet
Green
Yellow-green
Green
Violet
Red-violet
Violet-red
Carnation pink to salmon
Orange
“Yellowish”
Sky blue to green-blue
1.40
Orange
1.45
1.46
1.50
1.54
Violet
Blue-violet
Blue
Dull yellow-green
Figure 12: Colour Chart for the thickness of SiO2 layers. Colour chart for silicon
dioxide films observed perpendicularly under daylight fluorescent lighting.
LS #1 - 13
Questions
Assume the following data for the oxide growth in steps 1 and 4 of the process described in
section 3.1:
wet growth at 1100 degrees celsius and 50 minutes for step 1;
wet growth at 1100 degrees celsius and 36 minutes for step 4.
Recall the description of wafers 1, 2, and 3 given in section 4.2.
The slices used for this lab study have ( 111 ) orientation.
a) Estimate the thickness of the oxide on wafer 1 using the graph in figure 11. Refine your
estimate by observing the oxide color and using the chart in figure 12.
b) Repeat (a) for the oxide on wafer 2.
c) It is evident from the given data that the oxide on wafer 3 is formed from 86 minutes of
wet growth at 1100 degrees celsius. Using this information, repeat (a) for the oxide on
wafer 3. Is your final answer less than, equal to, or greater than the sum of the answers
from parts (a) and (b)? What qualitative statement does this lead you to make about the
rate of oxide growth as a function of time?
d) Suppose that the oxide on wafer 2 was actually formed using only dry growth. Using the
thickness you got in part (b), and the graph in figure 10, determine how long the dry
growth would have had to last to make the oxide, assuming it was also done at 1100
degrees celsius. What qualitative statement can you now make regarding the rate of dry
growth compared to the rate of wet growth?
4.5 Carrier Type by Hot Probe
Description
Silicon which has no impurities diffused into it is called intrinsic, and silicon with impurities
diffused into it is called extrinsic. In intrinsic material, the free electron and hole
concentrations are equal: n = p. In n-type extrinsic silicon n > p, and in p-type extrinsic
silicon p > n. We call the carriers present in higher concentrations the majority carriers, and
the other carriers the minority carriers; for example, in n-type material electrons are the
majority carriers. The majority carriers in extrinsic material come from the impurity atoms:
in n-type material, each impurity atom donates an electron, and thereby becomes a positively
charged ion; in p-type material, each impurity atom donates a hole, and thereby becomes a
negatively charged ion. Although the donated carriers are free to move through the material,
the ionized impurities occupy fixed positions.
The hot probe method is used to determine the majority carrier type of a material. Figure 13
shows a sketch of the hot probe apparatus. The point h is heated whereas the point c is kept
at room temperature. Since h is hot, the majority carriers there are thermally excited.
Therefore, on average, the majority carriers move away from h. Similarly, the minority
carriers will also move away from h; however, their concentration is so small that we can
neglect them. A voltage results between h and c, and the polarity of this voltage indicates the
type of material.
LS #1 - 14
Figure 13: Hot probe apparatus.
Questions
a) With the hot probe apparatus, the voltmeter will read a positive voltage for Vh - Vc if the
material is n-type, and a negative voltage for Vh - Vc if the material is p-type. Why? Hint:
Neglect the minority carriers and consider what is left behind when the majority carriers
move away from the hot probe.
b) Use the hot probe apparatus to determine whether wafer 4 is n-type or p-type.
4.6 Resistivity by Four-Point Probe
Description
A characteristic property of a doped semiconductor is its resistivity. The four-point probe
apparatus, illustrated in figure 14, provides a convenient way to obtain this quantity. Four
equally spaced and colinear probes are lowered onto the surface of the material. A current I
is passed through the outer probes while the inner probes measure a voltage V. If the
impurity concentration is uniform throughout the material, and the thickness d of the sample
is much less than the space s between probes, then it turns out that the resistivity is given by
ρ=
π V
ln 2 I
d ≈ 4.53
V
d
I
Equation 4
For a sample of arbitrary geometry, the resistivity depends on both s and d in a more involved
way.
LS #1 - 15
Figure 14: Four-point probe method to get resistivity.
Questions
a) Use the four-point probe apparatus to determine the resistivity of the material in wafer 4.
Wafer 4 (d = 228 µm) satisfies the conditions under which equation (4) is valid.
b) Using the value of resistivity that you obtain, your knowledge of the wafer type from part
(b) of section 4.5, and the graph in figure 15, determine the concentration of impurity
atoms in wafer 4. Name one element which could have been used as the impurity for
wafer 4.
LS #1 - 16
4
6
8
10
2
Resistivity (ohm * cm)
2
4
6
8
100
P Type
4
6
8
1.0
2
N Type
0.1
14
10
2
4
6
8
15
10
2
4
6
8
16
10
2
4
6
8
17
10
Impurities / cm3
Figure 15: Resistivity versus impurity concentration in silicon.
4.7 Sheet Resistance
Description
Consider the p-type regions in the diode and transistor of figures 1 and 5. For a given chip
with several diodes and transistors, the p region in every device is created at the same time by
the same processing steps. Therefore, the vertical characteristics of each and every p
diffusion on a chip must be the same. On the other hand, the lateral dimensions of the p-type
region in a given diode or transistor are determined by the mask diagram, and an engineer
may specify different lateral dimensions for different devices on a chip depending on their
intended use.
LS #1 - 17
A p-type region of arbitrary lateral geometry is illustrated in figure 16. For this region, we
may write the resistance as
R=
ρl
wt
=
ρ l
Equation 5
t w
However, for the p region in every device on a chip, the resistivity ρ and thickness t are the
same; only the length l and width w vary from device to device. With this in mind, we define
the quantity R[_] ≡ ρ / t , and rewrite equation (5) in the form
R = Rsq
l
w
Equation 6
The quantity Rsq (or R[_] ) is called sheet resistance. Provided the ratio l/w is known, the
resistance of any p region may be calculated using Rsq in equation (6). Rsq is said to have
units of Ω / [_] read “ohms per square”,since it is equal to R for a square: R = R[_] , when
l=w. Correspondingly, the ratio l/w in (6) is called the number of squares, and taken to have
units denoted by the symbol ‘ [_] ’.
Ideally, the ratio l/w is determined by dimensions on the mask diagram; in practice, the actual
l/w ratio in a fabricated device is somewhat smaller. To see this, refer back to the planar
process description in section 3.1. Suppose an engineer specifies a p diffusion mask diagram
with a long, thin region of length l and width w. Ideally, this would correspond to a region
with an area of l/w squares. However, in step 2 of the processing, etching can undercut to
expose an area of width greater than w at the surface of the silicon; moreover, in step 4,
diffusion proceeds laterally as well as downward. The result is that the actual p region which
is formed will have a width greater than w, and the number of squares will be less than the
value l/w obtained from the mask dimensions. Note that the larger the value of w on the
mask diagram, the smaller the effect that undercutting and sideways diffusion will have on
the ratio l/w.
Figure 16: A p-type region of a diode or transistor. The length of the region is l, its
width is w, and its thickness is t.
Of course, the concept of sheet resistance can be applied to any layer of material which has
identical vertical characteristics all over a chip, or even all over a wafer for that matter, and
not just the p regions discussed above. For example, one might speak of the sheet resistance
of the n-type diffusions used to create the emitters of all bipolar transistors on a chip.
LS #1 - 18
Questions
Consider again figure 8. Note the sheet resistance test pattern. This pattern is just a large p
diffusion made in the starting n-type material. Circular metal contacts, or pads, are made to
the diffusion at the surface. The pattern will be used to study the sheet resistance of the p
diffusions made during the creation of the diodes and transistors on your wafer. Locate the
test pattern on a chip on wafer 5 by looking through the microscope at the probing station.
For each of the following exercises, use the probing station to make contact to appropriate
pads. Please take care to position the probes gently so that you do not damage the wafer.
Then, before taking any readings, turn off the microscope light! The light from the
microscope is quite bright, and it can cause many electrons and holes to be generated in the
silicon. These generated carriers could interfere with your measurements. Of course, the
ambient light in the room will also generate a few carriers; however, this light won't cause
enough generation to significantly affect any results.
a) Apply a voltage V between pads 1 and 4, and measure the resulting current I. Calculate
the resistance R1,4=V/I between pads 1 and 4. Hint: For an accurate measurement, use a
voltage V yielding a current I of at least one milliampere. A current of this size will
ensure that any generated carriers from the ambient room light do not significantly affect
your results.
b) In the measurement of part (a), why can you be sure that all of the current I flows only in
the p-type diffusion, that is, why can you be sure that none of the current flows through
the starting n-type material? Hint: Consider equation (1) with Vd = 0.
c) If the lateral area of the p diffusion between pads 1 and 4 is equivalent to 15 [_] (sq) ,
calculate its sheet resistance R[_] using the value of R1,4 you got in part (a).
d) Use pads 1 and 4 as current pads, and pads 2 and 3 as voltage pads; in other words, cause
a current I to flow from pad 1 to pad 4, and measure the voltage V between pads 2 and 3.
Do you see that is the voltage between the points x1 and x2 due to the current I flowing
from pad 1 to 4? Hence, calculate the resistance Rx1,x2 = V/I of the p diffusion between
the points x1 and x2. If the equivalent area between x1 and x2 is 10 [_] (sq) , calculate the
corresponding value of sheet resistance R[_] for the p diffusion. Strictly speaking, the
value you get is more accurate than that in part (c) because, by using different pads for
current and voltage, you eliminate the effects of contact resistance from your
measurement. How does the value you get compare with that in part (c)? Would you say
that contact resistance significantly affected the result you got in part (c)? Hint: For an
accurate measurement, use a current I of at least one milliampere. This will make the
effects of any generated carriers from the ambient room light negligible.
e) Apply a voltage V between pads 1 and 3, and measure the resulting current I.
Calculatethe resistance R1,3=V/I between pads 1 and 3. Hint: As in part (a), for an
accurate measurement, use a voltage V yielding a current I of at least one milliampere.
f) The area between pads 1 and 3 has mask dimensions yielding ( l / w )1,3 = 30 [_] (sq), and
the area between pads 1 and 4 has mask dimensions yielding ( l / w )1,4 = 15 [_](sq).
Based on these mask dimensions, what is the ideal value of the ratio of resistances
LS #1 - 19
R1,3/R1,4? What ratio do you get using the values of R1,4 and R1,3 that you measured in
parts (a) and (f)? How does the measured ratio compare to the ideal ratio? Is this what
you expect? Explain. Hint: Consider the effect of the long and thin section, near pad 3,
on the actual number of squares between 1 and 3.
g) Repeat part (d) using another p diffusion test pattern on your wafer. Ideally, you should
get the same answer, but turbulence of the gas sources in the diffusion furnace can cause
the sheet resistance to vary from one part of the wafer to another.
4.8 Measurement of the Finished Diode and Transistor
Description
Figure 17 shows the current-voltage characteristics for a diode. For forward voltages VD > 0,
the current ideally rises exponentially with voltage, as predicted by equation (1). For reverse
voltages VD < 0, the current is approximately equal to -IS, but slowly increases in magnitude
with increasing reverse voltage. If the reverse voltage is increased far enough, breakdown
will take place. At this point, occurring for a critical voltage called the breakdown voltage VB , the reverse current drastically increases in magnitude. Given the physical properties of a
diode, you'll learn later in this course how to calculate IS and VB.
Figure 17: Current-voltage characteristics for a diode.
LS #1 - 20
Figure 18 shows the IC versus VCE characteristics one might measure for an npn transistor.
The current gain β of the transistor can be obtained by finding the ratio IC / IB; for example,
for the characteristics illustrated in figure 18, β ≈ 100. The current gain is an important
property characterizing a transistor. Later in this course, you'll derive an expression for the β
of an npn transistor in terms of its physical properties.
Questions
Refer back to figure 8. Note the patterns for the diode and transistor. Locate these on a chip
on wafer 5 by looking through the microscope at the probing station. In this exercise, you'll
examine the characteristics of the finished devices using a curve tracer. The curve tracer is a
tricky piece of equipment to use, so please ask a teaching assistant or the lab technologist for
help. Remember to turn off the microscope light prior to making any measurements!
a) Probe pads 23 and 20 of the diode, connecting pad 23 to the collector terminal and pad
20 to the emitter terminal of the curve tracer. Sketch the diode forward characteristics for
ID between 0 and 100 µA. Be sure to label and scale the axes on your sketch.
b) Measure the breakdown voltage VB.
c) Sketch the diode reverse characteristics, for VD between 0 and -4 V, with low- and highintensity incident light. Use the microscope light at low- and high-intensity settings.
Observe that incident light has the effect of essentially shifting the characteristics
vertically by an amount IL. This occurs because of the holes and electrons generated by
the incident light. It turns out that these generated carriers flow in the reverse direction,
creating a light current IL which subtracts from the normal diode current. Show IL on
your sketch. Be sure to label and scale the axes on your sketch!
Figure 18: Ic versus VCE characteristics for a sample bipolar junction transistor.
LS #1 - 21
d) The npn transistor is presently unavailable, so please omit this exercise (d). Probe
the npn transistor and connect emitter, base, and collector to the appropriate terminals on
the curve tracer. Sketch the IC versus VCE characteristics. Estimate the transistor current
gain when IB = 50 µA.
4.9 Switching of a Diode
Description
One of the most important things to know about a semiconductor device is its potential
switching speed. This is because the fastest rate at which a diode or transistor can turn on
and off ultimately determines the speed of the circuits, and hence the systems, in which they
are used. The first step in understanding what limits the speed of a semiconductor device is
to study the switching of a diode. In this exercise, you will look briefly at the turn-off
characteristics of a diode under current drive.
Consider the simple circuit and waveforms in figure 19. A generator is connected to the
series combination of a diode and a resistor R. The generator switches from a positive
voltage Vf to a negative voltage -Vr.
If Vf and Vr are both much larger than the forward diode voltage drop Vd, the diode is said to
be under current drive; that is, the generator is attempting to drive currents of approximately
Vf / R in the forward direction and Vr / R in the reverse direction through the diode.
When Vg = Vf, the diode is forward biased, and as you might expect, a current of
approximately Vf / R flows. Now, when the generator switches to Vg = -Vr, you might think
that the diode is immediately forced into a reverse bias condition, and hence that the current
should immediately become ID = -IS = tiny. But that's not what happens! In reality, when Vg
switches to -Vr, a current ID = -Vr / R flows for a finite time tS, called the storage time, and
only then does it decay rapidly towards -IS!
What gives rise to the diode storage time? You'll learn later that in a pn junction diode, the
current ID through the diode is carried by holes and electrons which are injected from one
region to the other: holes are injected from the p side to the n side, electrons are injected from
the n side to the p side, and the amount of injection increases with the forward current. When
the generator switches from Vf to -Vr, these carriers have to be evacuated before the diode is
reverse biased; that is, the injected holes have to be pulled back to the p side, and the injected
electrons to the n side. Until the carriers are all pulled back, they will carry the forced reverse
current -Vr/R in the diode, and this occurs for the storage time tS.
LS #1 - 22
Figure 19: Simple diode switching circuit and waveforms. For this lab, a 1N4003 diode
and R = 7 kΩ
Ω will be used.
Questions
A teaching assistant or the lab technologist will set up the diode switching circuit and display
the waveforms on an oscilloscope for you. The waveforms will be displayed for four cases:
1. Vf = Vr = 5 V, tf = 50 µs;
2. Vf = 9 V, Vr = 1 V, tf = 50 µs;
3. Vf = 3 V, Vr = 7 V, tf = 50 µs;
4. Vf = Vr = 5 V, tf = 5 µs.
Watch the demonstration and do the following:
a) Write down the measured value of tS from the oscilloscope display for each of the four
cases.
b) Using your observations from cases 1 to 3, explain qualitatively how tS varies with the
ratio Vf / Vr. Explain why this behavior ought to be expected.
LS #1 - 23
c) For the diode used in this demonstration, and assuming that the diode is fully turned
on initially, it works out that tS is given by
tS = τp0 ln (1 + Vf / Vr )
Equation 7
where τp0, called the hole minority carrier lifetime, is the average length of time an
injected hole survives in the n side before recombining with an electron. Using your
observations from cases 1 to 3, calculate τp0, which is an important diode parameter. Are
the values you get from the three cases similar? What would you quote as the
approximate value of τp0?
a) Cases 1 and 4 use the same values of Vf and Vr. Yet, you will find that tS in case 4 is less
than tS in case 1. How can you explain this? Hint: Note that equation (7) is not valid for
case 4.
5. Conclusions: What You Learned!
In this lab, you have been introduced to many important ideas in the study of semiconductor
devices, including: the planar fabrication procedure; conductivity type; pn junctions; real
diodes and transistors; resistivity; sheet resistance; and diode switching. As the term
progresses, you will study each of these topics, and others, in detail.
6. References
1. Donald A. Neamen. Semiconductor Physics and Devices, 3ed edition.
McGraw Hill, Toronto, 2003.
2. Ben G. Streetman and Sanjay Banerjee. Solid State Electronic Devices, 5 th edition.
Prentice Hall, Upper River, New Jersey, 2000. Chapter 5 covers the p-n Junction.
3. David H. Navon. Semiconductor Microdevices and Materials. Holt, Rinehart and
Winston, New York, 1986. Chapter 11 contains an overview of the fabrication procedure
for integrated circuits.
4. R. Runyan and K. E. Bean. Semiconductor Integrated Circuit Processing Technology.
Addison-Wesley Publishing Company, Reading, Massachusetts, 1990. This book
contains far more information than you need for this lab. However, if you're interested,
chapter 1 offers a nice historical perspective on the invention of the transistor and
integrated circuits, and chapter 2 contains a nice overview of the integrated circuit
fabrication process.
LS #1 - 24
5. J. Roulston. Bipolar Semiconductor Devices. McGraw-Hill, New York, 1990. This book
contains more information than you'll need for this course; however, it's a great one to
keep in mind as a general reference when you study diodes and bipolar transistors.
Chapters 1 to 3 present the basics of semiconductor physics, p-n junctions, and diodes;
chapter 4 investigates diode switching; chapter 7 looks at the basic theory of operation of
the bipolar transistor; and, if you're interested, chapter 14 has information on the
fabrication of advanced technology bipolar transistors.
6. Adel S. Sedra and Kenneth C. Smith. Microelectronic Circuits. Holt, Rinehart and
Winston, New York, second edition, 1987. Appendix A has a nice, concise overview of
the fabrication procedure for integrated circuits.
7. Edward S. Yang. Microelectronic Devices. McGraw-Hill Book Company, New York,
1988. Not particularly useful for this lab, but good to keep in mind as a general reference.
8. Adir Bar-Lev. Semiconductors and Electronic Devices. Prentice Hall, Englewood Cliffs,
New Jersey, 2nd edition, 1984. Chapter 16 gives an overview of the fabrication
procedure for integrated circuits. Chapter 5 contains a little information on the hot probe
method, resistivity by the four-point probe, and sheet resistance
LS #1 - 25
Laboratory Study 2
Introduction to Bipolar Junction Transistors
Mani Vaidyanathan1
10 October 1996
1.
Introduction
The first working transistor was a bipolar transistor, invented by John Bardeen, Walter
Brattain, and William Shockley of Bell Laboratories during the late 1940s and early '50s.
There is no doubt that the creation of this device represents one of the most important
technological advancements of this century; in fact, Bardeen, Brattain, and Shockley were
given a Nobel Prize for their work. Today, the bipolar junction transistor (BJT) is widely
used, both in discrete and integrated form, in all sorts of electronic systems. In this lab, you'll
be introduced to some fundamental properties of the BJT; by the end of this course, you'll
know all about this extremely important semiconductor device.
2.
Before the Lab
Ideally, by the time you do this lab, you should have completed lab # 1 and covered the basic
operating principles of the BJT in lectures. However, because of scheduling constraints,
many of you will be doing this lab before doing lab # 1 and also before you've covered the
BJT in class. Don't worry about this, because the essentials of BJT operation you need in
order to do the exercises are included in this write-up, and when you need information from
lab # 1, the appropriate sections to which you should refer will be indicated.
Your prelab assignment is to read this write-up and familiarize yourself with the lab. As with
lab # 1, and depending on when in the term you actually do this lab, you may find that many
of the terms and concepts are new to you. Keep track of the things you find confusing, and
then ask a teaching assistant or the lab technologist for clarification during the lab period.
Alternatively, you might want to check the references listed at the end of this write-up.
3.
Background: Basic Operation of a BJT
In lab # 1, we saw how an npn bipolar transistor is fabricated by way of the planar process. If
you haven't done lab # 1, you can get the essentials by reading section 3 of that lab write-up;
if you have done lab # 1, then you should refresh your memory by reviewing the fabrication
process. Please do this now.
1
Based on exercises originally developed by Prof. D. J. Roulston and Prof. M. I. Elmasry.
LS 2 - 1
Figure 1 Basic structure of a planar npn bipolar transistor under standard
operating conditions. The resulting simplified carrier flows, and conventional
currents due to these flows, are shown. Note that the conventional current due
to electrons is opposite to the direction of their flow. This is because electrons
are negatively charged.
Figure 1 shows the basic structure of a planar npn bipolar transistor under standard
operating conditions. Usually, the first pn junction, formed between the n+ and p
regions, is under forward bias, while the second pn junction, formed between the p
region and n starting material, is under reverse bias. Since the first pn junction is
under forward bias, carrier injection takes place there: holes are made to flow from
the p region into the n+ region, and electrons are made to flow from the n+ region into
the p region. Since the second pn junction is under reverse bias, no carrier injection
takes place there.
Shown in Figure 1 are the paths of the holes and electrons, as well as the conventional
currents due to their flow. The holes enter through the surface contact 10, travel
through the p region, get injected into the n+ region, traverse the n+ region, and then
exit from the surface contact 9. The electrons enter through the surface contact 9,
travel through the n+ region, get injected into the p region, traverse the p region to the
n starting material, and finally travel up to the surface contact 1. We say that the
n+ region emits electrons and that these are
collected by the
n region;
correspondingly, we refer to the n+ region as the emitter and the n starting
LS 2 - 2
material as the collector. The p region is called the base. As well, since electrons are
injected downward, we say that the device is operating in the downward mode.
Figure 2 Simplified bias arrangement for standard downward operation
of an npn bipolar transistor. RB, RC not included. IE = IC + IB
Figure 2 shows the biasing required to achieve standard downward operation. The voltage
VBE is typically around 0.7 V, and VCE is typically a few volts. Shown also in figure 2 are the
terminal currents: IC is the collector current; IB is the base current; and IE is the emitter
current. Can you see which carriers are responsible for each of these currents in the device
by looking at Figure 1 ? The base current is carried by the holes at contact 10, the collector
current by the electrons at contact 1, and the emitter current by the holes and electrons at
contact 9.
The forward bias on the n+p junction, or emitter-base junction, in Figure 1 is created by the
applied voltage VBE. This applied voltage determines the amount of carrier injection that
takes place at the emitter-base junction; therefore, this voltage has control over the number of
electrons crossing the nearby reverse-biased base-collector junction. In other words, the
voltage VBE controls the collector current IC. This phenomenon, namely that the applied
voltage across a forward-biased junction VBE controls the current crossing a nearby reversebiased junction IC, is called transistor action, and in a sense, it's what defines a bipolar
transistor.
LS 2 - 3
4.
In the Lab
Fitgure 3 Substrate is Pin 1 (n type material).
Composite mask diagram of the chip to be used for this lab. The pin
numbers of the pads to which you need access are marked on the diagram.
LS 2 - 4
4.1.
Devices for this Lab
Figure 3 shows a composite mask diagram for the chip you will use in this lab. The chip was
made using an integrated circuit fabrication process. Unlike in lab # 1, you will not probe the
chip directly; rather, you will access the chip through a 16-pin dual-in-line package (DIP).
The pin numbers of the pads to which you need access are indicated in Figure 3.
There are two transistors, and two patterns to be used in this lab:
• transistor 1 is a large npn device, and its composite mask diagram is shown in Figure 7
• transistor 2 is a lateral pnp device, and its composite mask diagram is shown in Figure 18
• pattern 1 is a large p diffusion, and it is shown in figure 13
• pattern 2 provides access to the p diffusion layer under the n+ emitter, and it is shown in
figure 14.
See if you can locate these transistors and patterns in figure 3.
4.2.
Structure of the Lab Exercises
In each of the following exercises, you will examine a different aspect of bipolar transistors.
For each exercise, there is a description and questions. Read the description, which contains
all the background information you need, and then answer the questions.
4.3.
Standard Downward Characteristics
Description
Consider again the npn transistor biased for standard downward operation, as in the
simplified circuit of Error! Reference source not found.. With the emitter terminal as the
common, we often consider the base terminal as the input and the collector terminal as the
output, and say that the transistor is working in a common-emitter configuration. Using this
nomenclature, for a given transistor, we are interested in how the output current IC relates to
both the input voltage VB ≡ VBE and the input current IB; in particular, we want to know
exactly how IC varies with VBE, and we want to know the value of the current gain β ≡ IC / IB.
Consider IC as a function of VBE. When you study the theory of the BJT in lectures, you'll
learn that
I C = I CS [exp(
V BE
) − 1]
Vt
Equation
→1
where ICS is called the collector saturation current and Vt is the thermal voltage. Doesn't
equation 1 look familiar? It's identical in form to the current-voltage law for a diode! Since
the collector current is a result of carrier injection at the forward-biased emitter-base junction,
and this junction itself is just a diode, you shouldn't find this surprising.
LS 2 - 5
Figure 4
Simplified picture of an npn transistor illustrating the dimensions B, L, and WB.
The collector contact is not shown in the sketch.
In lectures, you'll derive an expression for ICS in terms of the physical properties of the
transistor. Assuming that the concentration of impurity atoms in the p-type base is uniform,
you'll find that
2
I CS
qA e n i D n
=
N Ab W b
Equation
→ 2
where the symbols, some of which are illustrated in figure 8, are as follows: q= 1.602 × 1019
C is the electronic charge; Ae = B × L is the lateral emitter area; ni = 1.5 × 1010 cm-3 is the
intrinsic free carrier concentration, namely the concentration of electrons and holes available
for conduction in pure silicon; Dn is the electron diffusion coefficient in the base, and is a
physical constant which describes how electrons move through the p-type base; NAb is the
concentration of impurity atoms in the p-type base; and WB is the neutral base width in the
vertical direction.
Equation 2 is only valid if the concentration of impurity atoms in the p base is uniform. In a
planar npn device, the impurity concentration in the base is actually not uniform; in reality,
the concentration varies vertically through the device, namely along the x axis in figure 8.
We can easily correct equation 2 to take this into account. The simplest correction is to
replace NAb in equation 2 with Nab av , the average impurity concentration in the region
between x = 0 and x = WB. Strictly speaking, however, the product NAbWB in equation 2
should be replaced with a quantity G, called the Gummel number. This number is given by
Wb
G=
∫ N ( x ) dx
0
LS 2 - 6
Equation
→ 3
where N(x) is the impurity concentration at a depth x below the emitter-base junction. As
well, strictly speaking, the constant Dn in equation 2 should be replaced with an average
value Dn av . This is because Dn is a function of the impurity concentration; thus, since the
doping is not constant but varies with x, it follows that Dn is not a constant but depends on x.
2
Figure 5
Gummel plot for a sample bipolar transistor. Ideally, the plot is a straight
line, but it will droop at high IC due to the base and emitter resistances.
Extrapolation of the plot back to the IC axis yields the saturation current
ICS.
It is customary to show the IC versus VBE characteristics of a transistor on a Gummel plot.
Figure shows a sample Gummel plot. Note that the IC axis has a logarithmic scale whereas
the VBE axis has a linear scale. Ideally, from equation 1, this means that the plot should be a
straight line. To see this, note that for values of VBE greater than a few Vt, we can neglect the
-1 in equation 1 to write
I C = I CS exp(
V BE
)
Vt
2
Equation
→ 4
At this point, if you haven't yet covered the basic theory of diodes and BJTs in lectures, you might
have a lot of questions. Don't let this discourage you! For now, take the stated equations on faith,
keeping in mind that you'll eventually examine them closely in lectures. Remember also to keep track
of your questions, so that you can ask for help during the lab period!
LS 2 - 7
and hence
log e
log IC = log ICS +
VBE L L L L Equation → 5
Vt
10
10
10
so that
log 10 I C ∝ V BE
Equation
→ 6
At high values of IC, the Gummel plot droops, deviating from the ideal straight line behavior.
This deviation is due to the base resistance and emitter resistance of the transistor; we'll
investigate this more in section 4.4. Note that the intercept of the Gummel plot with the IC
axis yields the collector saturation current ICS.
β
Figure 6 Sketch of the current gain β as a function of collector current IC for
a sample transistor. The sketch assumes that the transistor is operating in the
standard downward mode, namely with the emitter-base n+p junction under
forward bias and the collector-base np junction under reverse bias, for all
values of IC. Note that logarithmic scales are used for the β and IC axes.
Consider the current gain β = IC/IB. When you studied the bipolar transistor in basic circuit
theory, you would have learned that β is typically quite a high number, around 100.
However, you probably didn't learn that the value of β depends on the amount of collector
current flowing, that is, β is a function of IC. Figure 6 shows a sketch of a typical β versus
IC plot. Note that β is highest at intermediate values of IC, and falls off for low and high
values of IC. In this course, you won't learn too much about why the current gain falls off at
low and high values of IC; however, you should be aware that a transistor biased at very low
or high currents could have a small current gain.
LS 2 - 8
Figure 7 Large npn transistor. The emitter area is 100 × 100 µm2. Base,
emitter, and collector leads for downward operation are indicated on the
diagram.
Procedure & Questions
Consider the circuit in figure 8. You'll use this circuit to study the IC versus VBE and β versus
IC characteristics for transistor 1. Recall that transistor 1 was shown in figure 7.
LS 2 - 9
Figure 8
Circuit you will use to study the operating characteristics of npn bipolar junction
transistors. RB = 10 kΩ
Ω, RC = 270 Ω
Procedure
(a) Connect the circuit using transistor 1. Vary VBE from 500 to 850 mV, in increments of
about 50 mV, by varying VBB; meanwhile, hold VCE at 1.0 V by varying VCC. Use digital
ammeters to measure IB and IC, and use a digital voltmeter to measure VBE and VCE. As
you go, write down VBE, IB, IC, and VCE so that you obtain a table of values for these
quantities. Note: You must keep VCE at approximately 1.0 V for all your measurements!
Hint: For the VBE values specified, you should get a range of IC values from tenths of
microamperes to tens of milliamperes. Stop if Ic exceeds 90 mA.
(b) Using the data you got in part (a), construct a Gummel plot for transistor 1.
Extrapolate the Gummel plot back to VBE = 0 to determine the saturation current ICS.
Hint: You should find3 that ICS is between 10-16 and 10-15 A. From the theory presented
in this section, it is evident that
I CS
qA e n i 2 D nav
=
G
Equation
→ 7
(c) Using Dn av = 20 cm2/s and the value of ICS you got in part (b), calculate G. Recall that
Ae = 100 × 100 µm2 for transistor 1, and use the values q = 1.602 × 10-19 C and ni = 1.5 ×
1010 cm-3 for your calculation.
(d) Using equation 5 and two points from the straight-line portion of your Gummel plot, find
the thermal voltage Vt. Hint: The calculation should not require a value for the
saturation current ICS.
3
The numbers given in the hints are only guidelines to help you ensure that you're performing
measurements correctly. Interpret them as ballpark figures around which your values should lie.
LS 2 - 10
(e) The thermal voltage is given by
Vt =
kT
q
Equation
→ 8
(f) where k = 1.38 × 10-23 J/ K is Boltzmann's constant, q = 1.602 × 10-19 C is the electronic
charge, and T is the temperature. Using the value of Vt you got in part (d), solve for T.
Hint: T is the temperature of the emitter-base junction, not room temperature; thus, you
may find T to be slightly higher than room temperature.
(g) Plot β versus IC for transistor 1 using the data you obtained in part (a). Use logarithmic
scales for the axes. High-current gain falloff occurs at very high currents for transistor 1.
You should see low-current gain falloff. Label both the high and low-current gain falloff
on your plot. Hint: Transistor 1 has a peak gain about 100.
4.4. Base Resistance
Description
In lab # 1, we looked at the idea of sheet resistance. If you haven't done lab # 1, then you can
get the essentials by reading section 4.7 of that write-up; if you have done lab # 1, then you
should refresh your memory by reviewing that section. Please do this now.
Figure 9 Sketch showing the sheet resistances associated with the p
diffusion region, or base, of an npn bipolar transistor. RB \ [_] refers to the
sheet resistance of the entire p diffusion, that is, from the surface of the
silicon to the bottom of the p region. RBE \ [_] refers to the sheet resistance
of the p diffusion layer under the n+ emitter.
Consider the p diffusion needed to create the base region of an npn bipolar transistor. There
are actually two values of sheet resistance associated with this diffusion, as illustrated in
figure 12. We can consider the sheet resistance of the entire p diffusion, that is, from the
surface of the silicon to the bottom of the base region; this is called the base sheet resistance,
and is denoted by the symbol RB [_] . On the other hand, we can consider the sheet resistance
of only that part of the p diffusion under the n+ emitter; this is called the sheet resistance of
the base under the emitter, and is denoted by the symbol RBE [_] . Sometimes, R B [_] is called
the extrinsic base sheet resistance, since it is associated with that part of the base region
LS 2 - 11
extrinsic to where carrier injection takes place; correspondingly, RBE [_] is often called the
intrinsic base sheet resistance. Both RB [_] and RBE [_] are important quantities, because they
determine the base resistance of a bipolar transistor.
Consider again figure 1. Holes making up the base current must travel from the base contact,
through the extrinsic base, and in the intrinsic base before being injected into the emitter.
Since the extrinsic and intrinsic base have a finite sheet resistance, the base current IB sees
finite resistances rbx and rbi associated with these regions. Similarly, the emitter current
IE sees a resistance rE associated with the n+ material through which it must flow. The
effect of these resistances is to make the voltage appearing across the emitter-base junction
different from the applied terminal voltage: although a terminal voltage VBE is applied,
only a portion VBE eff , is actually effective in causing current injection at the emitterbase junction, as illustrated in Figure 10.
Figure 10 Illustration of the base resistance components rbx and rbi, and
the emitter resistance rE. Although a voltage VBE is applied at the device
terminals, only a value VBE eff ends up appearing across the emitter-base
junction; the difference VBE - VBE eff is lost across rbx, rbi, and rE.
LS 2 - 12
Figure 11 Equivalent circuit for modeling the effects of base and emitter
resistance. The resistance rbb ≡ rbx + rbi is the total base resistance, and rE
is the emitter resistance. The transistor in the circuit is ideal, that is, it
operates like a device with zero base and emitter resistances. Note: rC, the
collector resistance is not shown.
We can better understand the effects of base and emitter resistances by considering the
equivalent circuit model in Figure 11. From the figure, you should be able to convince
yourself that
V BEeff = V BE −
IC
β
r bb −
I C ( β + 1)
→ 9
Equation
V BEeff = V BE − I B r bb − I E r e
re
Equation
→ 10
β
where rbb ≡ rbx + rbi is the total base resistance. Since the voltage actually appearing across
the emitter-base junction of the device is VBE eff then the collector current which actually
I C = I CS exp(
V BEeff
)
Vt
Equation
→ 11
flows is
For small values of IC, the last two terms in (10) are negligible, so that VBE eff ≈ VBE and
equation (11) reduces to (4). On the other hand, for larger IC, VBE eff is noticeably smaller than
VBE, and the actual collector current flowing as given by (11) is noticeably smaller than that
predicted by (4); this is why the Gummel plot droops, deviating from the prediction of
LS 2 - 13
equation (4). Figure 12 shows the quantities IC, VBE, and VBE eff for one point on a Gummel
plot.
Figure 12 Illustration of the the applied terminal voltage VBE, the
effective voltage appearing across the emitter-base junction VBE eff , and the
resulting collector current IC for one point on a Gummel plot.
Why do we care about base resistance and emitter resistance? For one thing, the above
discussion should make it clear to you that we need to know these quantities if we are to
correctly predict the collector current IC for a given terminal base-emitter voltage VBE.
However, there is another reason: it turns out that the the base resistance of a bipolar
transistor is one of the things that limits its switching speed. It is important to keep the base
resistance low in order to improve transistor performance. The base resistance is typically in
the range of a few hundreds of ohms. The emitter resistance, being typically only a few ohms
to a few tens of ohms, is far less important than the base resistance in determining device
performance; however, we should be aware of its existence since it plays a role in the
drooping of the Gummel plot.
Some words of caution: in general, many things may contribute to the drooping of the
Gummel plot at high currents, not just base and emitter resistances. In fact, the behavior
of the collector current at high bias is quite complicated. In this course, we won't worry
about all the high current effects that take place in bipolar transistors, but you should note
that it's a lot more involved than just considering the effects of rbb and re.
LS 2 - 14
Figure 13 A large p diffusion pattern with contacts at 13, 14, 15, and 16.
Figure 14 A pattern providing access to the p diffusion layer under the n+
emitter. There are 5 [_]’s between the contacts 11 and 12.
Questions
a)
Pattern 1, which was shown in figure 13, is just a p diffusion with contacts at A, B, C,
and D. It is called a Van der Pauw pattern, and may be used to obtain the base sheet
resistance RB [_] . If a current IBA is made to flow from B to A and the resulting voltage
VCD between the contacts C and D is measured, then Van der Pauw has shown that the
sheet resistance may be calculated as
R B / sq =
π V CD
ln 2 I BA
≈ ( 4 . 54
V CD
Ω)
I BA
sq
Equation
→ 12
Use this information and pattern 1 to determine RB [_] . Hints: Your measurement should
yield RB [_] ∼ 160 → 190 Ω / [_] . Use IBA ∼ 0.1 mA.
b) Pattern 2, which was shown in figure 14, provides access to the p base layer under the n+
emitter. Given that the equivalent lateral area between the contacts X and Y is 5 [_] , use
pattern 2 to determine the sheet resistance RBE [_] of the base under the emitter. Hint:
Your measurement should yield RBE [_] ≈ 5 k Ω / [_] .
LS 2 - 15
c)
Use the Gummel plot you made in part (b) of section 4.3 to determine rbb for transistor 1.
For your calculation, assume that re = 0.5 Ω and choose a point on the Gummel plot
corresponding to a value of IC greater than 10 mA. Hints: Look at figure 12 and use
equation (10). You should find that rbb is around 100 Ω.
d) Repeat part (c) for re = 0.75 Ω. Consider how sensitive your calculations for rbb are to
the value of re.
e)
Even though rE is typically much smaller than rbb, we cannot neglect it when determining
rbb from the Gummel plot. Why not? Hint: Compare the magnitude of the last two
terms in equation (10).
f)
In parts (a) and (b) above, you should have found that RBE [_] is quite a bit larger than
RB[_]. This is typically the case, and it causes the intrinsic base resistance rbi to be much
larger than the extrinsic base resistance rbx. As a result, to a very good approximation,
we can often write rbb ≈ rbi.
Consider again Figure 4. Figure 9 and Figure 10. You might be tempted to conclude that
rbi = RBE [_] ( L/B). However, once the base current IB reaches the base region under the
emitter, it begins to get injected into the emitter; that is, not all of IB traverses the
entire length L of the emitter. This fact means that the intrinsic base resistance is
actually given by
r bi =
R BEsq ( L / B )
Kr
Equation
→ 13
where Kr is called the intrinsic base resistance reduction factor. For the simple structure in
Figure 10, it turns out that Kr = 30. In general, Kr depends on the exact details of the
transistor under consideration. Use equation (13) to determine Kr for transistor 1. Assume
that L/B = 1 and that rbi ≈ rbb , and use the value of rbb you got in part (c). Hint: You should
get a value of Kr around thirty.
4.5. Upward Operation
Description
Consider again figure 1. From the symmetry of the npn structure, you might be wondering if
we can reverse the roles of the n+- and n-type regions; that is, why not use the n region as the
emitter, and the n+ region as the collector? In this case, the first n+p junction must be placed
under reverse bias, while the second pn junction must be placed under forward bias, exactly
opposite to the situation illustrated in figure 1. Since electrons will now be injected upward,
we say that the device is operating in the upward mode. We should still get transistor action,
only terminal 9 will be the collector lead and terminal 1 will be the emitter lead. This is a
good idea, except that the current gain of the device operating in upward mode is small.
The reasons for this will now be explained.
LS 2 - 16
When you cover the theory of the BJT in lectures, you'll derive a simple expression for the
current gain β. Assuming that the transistor is working at intermediate currents, namely
outside the low- and high-current falloff regions, and assuming that the concentration of
impurity atoms in the emitter and base is uniform, you'll find that
β =
W e D n N De
W b D p N Ab
Equation
→ 14
where We is the emitter width, Wb is the base width, Dn is the electron diffusion coefficient
in the base, Dp is the hole diffusion coefficient in the emitter, NDe is the concentration of
impurity atoms in the emitter, and NAb is the concentration of impurity atoms in the base.
Typically, We ∼ Wb and Dn / Dp is in the range of 2 to 3. Thus, the ratio NDe / NAb will
determine the value of gain.
To determine the ratio NDe / NAb, we need to consider how a transistor is fabricated. The
starting material is n-type. Since a p-type diffusion is made into this n-type material, it
follows that the concentration of impurities in the p-type region must exceed that in the
starting n-type material. Do you see why this must be the case?
Similarly, the concentration of the impurity atoms in the n+ region must exceed that in the
(p)type region. As a result, when the n+ region is used as the emitter, as for standard
downward operation, the ratio NDe / NAb will certainly exceed unity, and typically it will be
around 10 to 100; thus, the gain will be high. On the other hand, suppose we use the starting
n-type material as the emitter, as we would for upward operation. In that case, the ratio NDe /
NAb will be less than unity; hence, the gain will be low.
Figure 15 Basic npn structure working in upward mode. The arrows at
the forward-biased pn junction represent electrons injected upward from
the starting n-type material.
There is another reason that the gain is small in upward operation. Consider Figure 15,
which shows the basic npn structure working in upward mode. The arrows at the second
junction represent electrons injected upward from the n-type material. Unlike in downward
mode, the injection area exceeds the collection area in upward mode. As a result, many of
the injected electrons are not collected but are lost, and this degrades the collector current IC.
LS 2 - 17
Moreover, the lost electrons end up recombining with holes. The extra holes needed for this
recombination flow in from the base contact, and this increases the total base current IB.
Thus, in upward mode, β = IC / IB is degraded.
Questions
(a) Using the circuit of Figure 8, measure the upward gain of transistor 1 for values of VBE
between 0.55 V and 0.80 V, in increments of about 50 mV, and VCE = 1 V. Keep track of
the corresponding values of IC, which should all lie between a few microamperes and a
few milliamperes. Remember that you must now use pin 1 as emitter and pin 9 as
collector, opposite to what is indicated in Figue 1. Plot the values of upward gain on the
graph you made in part (g) of section 4.3. In general, how does the upward gain compare
with the downward gain you measured in section 4.3? Does the upward gain exhibit lowand high-current falloff? If so, label these on your plot. Note: You must keep VCE at
approximately 1 V for all your measurements.
(b) In upward operation, as explained above, lost electrons are partly responsible for the low
gain. What is a simple way to minimize the effect of these lost electrons? Hint:
Consider the relative sizes of the injection and collection areas.
4.6. Lateral pnp Devices
Description
The standard fabrication process for integrated circuits is geared towards the construction of
vertical npn transistors. However, in some applications, pnp devices may be needed.
Construction of vertical pnp devices in an integrated circuit would require extra processing,
and normally the extra steps needed would be too costly to justify their implementation.
However, without any extra processing, one can construct a lateral pnp device.
Figure 16 Circuit you will use to measure the gain of lateral pnp
transistors. RB = 10 kΩ
Ω, RC = 270 Ω
LS 2 - 18
Figure 17 Cross-section and layout of a real integrated lateral pnp transistor. The
arrows represent holes injected from the p-type emitter. The n+ diffusion at the location
of the base lead is only needed to ensure a good electrical contact to the n epitaxial
material. In reality, the p- substrate is much thicker than shown.
Figure 17 shows a cross-section of a real lateral pnp transistor that could be made using a
standard integrated circuit fabrication process. The p diffusion step normally used to create
the base of a vertical npn device is used to make the emitter and collector of the lateral pnp
device. The n epitaxial material is used as a base. For standard operation of the lateral
device, the emitter-base junction is forward biased and the collector-base junction is reverse
biased.
Unfortunately, the gain of lateral pnp devices is not very high. The gain is low for two
reasons. First, the base width is now determined by lateral dimensions, as shown in Figue 17.
Typically, lateral dimensions cannot be made as small as vertical dimensions, so that Wb is
larger than it would be for a vertical structure. Since the gain is inversely proportional to Wb ,
it is thus degraded. Second, many of the holes injected from the emitter are lost, as shown in
Figure 17. These lost carriers degrade the gain, just as they did for the npn structure working
in upward mode.
LS 2 - 19
Figure 18 Composite mask diagram for a lateral pnp transistor. Shading is used to indicate
p diffusion regions. Note that two contact cuts are made to the collector p diffusion. Access
to the collector is available through pin 8, and access to the emitter is available through pin 7.
The base contact is available through pin 1.
Questions
Look at the composite mask diagram for transistor 2 in Figure 18. The square p diffusion in
the center is surrounded on all four sides by another p diffusion. Contact cuts are made to the
two p diffusion regions, and the center region is used as the emitter while the outer region is
used as the collector. The base contact is made elsewhere, and is shown in Figure 18 at the
right side .
a) Draw a simple cross-section diagram of transistor 2 from x to x'. Label your sketch
carefully: indicate the p diffusion regions and n starting material; identify which regions
are used for emitter, collector, and base; show hole injection from the emitter using
arrows. You can omit the p+ isolation walls, n+ buried layer, and p- substrate from your
sketch.
b) Repeat part (a) from y to y'.
c)
What is the rationale behind the layout of transistor 2? Hint: Contrast the layout of
transistor 2 with the parallel geometry of the device in Figure 17.
d) Use the circuit of figure 16 measure the gain of transistor 2. Note the polarity of the
voltages Vbb and VCC! Measure the gain for IC = 0.1 mA and VCE = -1V. How does this
gain compare with that of the vertical npn structure operating in standard downward
mode, which you measured in section 4.3? Hint: To get IC = 0.1 mA, you will need VBE
≈ -0.70 V.
e)
For transistor 2, reverse the roles of the two p diffusion regions; that is, use the outer p
diffusion as emitter, and the center p diffusion as collector, opposite to what is indicated
in figure 18. Use the circuit of Figure 16 to measure the gain in this configuration for
LS 2 - 20
IC = 0.1 mA and VCE = -1 V. Is the gain higher or lower than the value you measured in
part (d)? Should this be expected? Why or why not? Hints: Consider your answer to
part (c). The gain you now measure will be less than unity. To get IC = 0.1 mA, you will
need VBE ≈ -0.71 V.
5.
Conclusions: What You Learned!
In this lab, you've been introduced to some fundamental properties of the bipolar junction
transistor (BJT). Here are some of the things that you hopefully got from doing this lab: a
qualitative feel for how an npn transistor works in the downward mode; an idea of how the
collector current IC varies with base-emitter voltage VBE in downward mode and how this
behavior can be seen on a Gummel plot; an idea of how the current gain β varies with
collector current; knowledge of the base resistance of a bipolar transistor, its importance, and
its determination from the Gummel plot; a qualitative feel for upward operation of an npn
transistor, including what factors limit the gain; and a qualitative feel for the lateral pnp
transistor, including how it is constructed and what factors limit its gain. When you cover the
theory of the BJT in lectures, you'll examine many of these ideas in more detail.
6.
References
1. Ben G. Streetman and Sanjay Banerjee. Solid State Electronic Devices, 5 th edition.
Prentice Hall, Upper River, New Jersey, 2000. Chapter 7 covers the BJT.
2. David H. Navon. Semiconductor Microdevices and Materials. Holt, Rinehart and
Winston, New York, 1986. Chapter 8 covers the BJT. For this lab, you may find useful
information in section 8.1. Beware that some of the symbols are not used in the same
way as in the lab write-up!
3. J. Roulston. Bipolar Semiconductor Devices. McGraw-Hill, New York, 1990. This is
the book for information on the bipolar transistors. The material in sections 7.1 through
7.4 is very applicable to this course. Chapter 13 has information on integrated transistors
that you may find useful for this lab.
4. Adel S. Sedra and Kenneth C. Smith. Microelectronic Circuits. Holt, Rinehart and
Winston, New York, third edition, 1991. Chapter 4 contains introductory information on
the basic operation principles of BJTs; in particular, you’ll probably find sections 4.1
through 4.5 useful for this lab.
LS 2 - 21
Laboratory Study 3:
Introduction to Field-Effect Devices
Mani Vaidyanathan 1
21 August, 1995
1
Introduction
Although the bipolar transistor was the first working transistor to be constructed, historically,
the field-effect transistor was the first ever proposed. There are two major types of field-effect
devices: junction field-effect transistors (JFETs); and metal-oxide-semiconductor transistors
(MOSFETs). JFET devices are commonly used in analog circuit applications, such as in the input
stages of operational amplifiers and in microwave amplifiers. MOSFET devices are used in both
analog and digital applications---you may have heard about CMOS, a low-power digital logic
family commonly used in modern digital integrated circuits. In this lab, you will be introduced to
both the JFET and the enhancement MOSFET.2
2
Before the Lab
As with all the other labs, your prelab assignment is to read this write-up and familiarize yourself
with the lab. Since it is likely that we would not have completely covered the JFET and
MOSFET in lectures prior to the time you do this lab, a teaching assistant will give a short
tutorial at the beginning of the lab period. During this tutorial, the qualitative operation of the
JFET and enhancement MOSFET will be reviewed, and the definitions of any terms you need to
know about will be given. Nevertheless, please make sure to review whatever class notes you
have so far on JFETs and MOSFETs. You may also want to check the references listed at the end
of this lab.
3
In the Lab
3.1
Devices for this Lab
In this lab, you will be using a commercial JFET and MOSFET devices made at the University of
Waterloo. The JFET is a type 2N3819, made by Texas Instruments. You may want to refer to the
data sheets for these devices, which are given at the end of this lab write-up.
1
Based on exercises originally developed by Prof. M. I. Elmasry and Mr. P. Hayes.
2
There is also a depletion MOSFET, but we won't analyze that device in this course.
LS #3 - 1
Although all the JFETs and MOSFETs are similar, the devices are not identical. Please make
sure that you use the same JFET and MOSFET throughout the lab.
3.2
Three-Terminal Characteristics of the JFET
With the n-channel JFET device provided, and with the assistance of a teaching
assistant or the lab technologist, use the curve-tracer station to obtain a plot of the
three-terminal characteristics of the JFET, namely a plot of the drain-to-source
current IDS, as a function of the drain-to-source voltage VDS, for different gate-tosource voltages VGS. Sample characteristics are illustrated in figure 1. Make sure
to label and scale both axes on your plot, and to indicate the value of VGS for each
curve, as done in figure 1.
(a) From your plot, what would you estimate as the value of the pinch-off voltage Vp of the
JFET? Note: We shall take the quantity Vp to be negative for an n-channel JFET.
(b) For each curve on your characteristics, plot the point VDS = VGS - Vp . Join the points together
to create the locus delineating the linear or triode region from the saturation region of
the characteristics. Indicate these regions on your plot.
(c) What is the value of the maximum drain-to-source current IDSS?
(d) Ideally, in saturation, the JFET characteristics should be horizontal. However, the JFET has
finite output resistance ro, and thus the lines will have finite slope. From your
characteristics, estimate ro for VGS = 0. Remember that, for a given VGS , the output
resistance ro is just the inverse of the slope of the characteristics in saturation:
 ∂I
rO ≡  DS
 ∂VDS

VGS = constant 

Equation 1
−1
(e) Calculate the device transconductance gm, in saturation, for VGS = 0. Remember that the
transconductance is defined as
gm ≡
∂I DS
∂VGS
Equation 2
VDS = constant
(f) With the aid of a cross-sectional diagram, qualitatively explain the three-terminal
characteristics of a JFET. Be sure to describe what gives rise to both the linear and
saturation regions of the characteristics.
(g) The three-terminal JFET characteristics are similar in appearance to the common-emitter
characteristics of a bipolar junction transistor (BJT). Compare the JFET characteristics to
those of the BJT. What are the similarities? What are the differences? Include a sketch
of the BJT characteristics in your answer, and indicate the saturation and forward active
regions of BJT operation on your sketch. Hint: Be careful---the term saturation
describes a different part of the characteristics for BJTs and JFETs.
LS #3 - 2
Sample three-terminal characteristics for an n-channel JFET. For this device, the
Figure 1:
pinch-off voltage is Vp approx -2.5 V. The maximum drain-to-source current is IDSS ≈ 4.7 mA.
Using the curve for VGS = 0, and between VDS = 4 and 7 V, we get an output resistance value of ro
≈ 3.0 V / 0.29 mA ≈ 10 kΩ. Using the curves for VGS = 0 and -0.5 V, and at VDS = 7 V, we have
gm ≈ 1.4 mA / 0.5 V ≈ 2.8 mS. The dashed line is the locus VDS = VGS - Vp ,and it approximately
delineates the triode and saturation regions of the characteristics.
3.3
Three-Terminal Characteristics of the MOSFET
With the n-channel enhancement MOSFET device provided, and with the assistance of a
teaching assistant or the lab technologist, use the curve-tracer station to obtain a plot of the threeterminal characteristics of the MOSFET, namely a plot of the drain-to-source current IDS, as a
function of the drain-to-source voltage VDS , for different gate-to-source voltages VGS . For these
characteristics, the body or substrate terminal will be shorted to the source, so that the body-tosource voltage VBS is zero. Sample characteristics are illustrated in figure 2. Make sure to label
and scale the axes on your plot and to indicate the value of VGS for each curve, as done in figure
2.
(a) With the aid of a cross-sectional diagram, qualitatively describe the operation of an n-channel
enhancement MOSFET.
LS #3 - 3
(b) From your plot, what would you estimate as the value of the threshold voltage VT of the
MOSFET?
(c) For each curve on your characteristics, plot the point VDS = VGS - VT. Join the points together
to create the locus delineating the linear or triode region from the saturation or active
region of the characteristics. Indicate these regions on the plot.
(d) Calculate the MOSFET output resistance ro, in saturation, for the highest value of VGS on
your plot.
(e) Calculate the MOSFET transconductance gm, in saturation, for the highest value of VGS on
your plot.
(f) Compare the MOSFET three-terminal characteristics with those of the JFET. If you were
given a plot of the characteristics for one of these devices, and the plot had no VGS values
labeled on it, would you be able to tell whether the device was a JFET or a MOSFET?
Explain.
Sample three-terminal characteristics for an n-channel
Figure 2:
enhancement MOSFET. For this device, the threshold voltage is VT ≈2.0 V. For
VGS = 4.5 V, and between VDS = 7 and 2.5 V, we have ro ≈ 4.5 V / 0.30 mA ≈ 15
kΩ. Using the curves for VGS = 4.5 and 4.0 V, and at VDS = 7 V, we have gm ≈ 1.0
mA / 0.5 V ≈ 3.0 mS. The dashed line is the locus VDS = VGS - VT, and it
approximately delineates the triode and saturation regions of the characteristics.
LS #3 - 4
3.4) MOSFET Threshold Voltage
With the MOSFET working in saturation, a simple relationship for the current-voltage
characteristics is given by
I DS = K (VGS − VT )
2
Equation 3
where K is a constant depending on the exact device properties.3 This equation implies that
I DS ∝ VGS . A plot of I DS versus VGS , with VDS chosen large enough so that the device is in
saturation, should hence be a straight line. This is indeed the case, so long as IDS is neither too
small nor too large, and if the straight line portion of the plot is extrapolated back to IDS = 0, then
the intercept yields the threshold voltage VT.
A
D
+
V
G
DS
+
V BS
V
GS
Ammeter
+
V DD
-
S
+
VGG
Figure 3:
+
- -
+
-
1 k
B
V BB
Circuit to study the effect of body bias on MOSFET threshold
voltage.
(a) Connect the circuit shown in figure 3. Please remember that VGS must be positive, VDS
must be positive, and VBS must be negative at all times! Correspondingly, note the
polarity marks on the dc sources VGG, VDD, and VBB. Create a table of values of IDS and
I DS versus VGS for a constant VDS value of 6 V. Vary VGS so that IDS takes on values of
about 1, 2, 3, 4, and 5 mA. For each VGS value, do not forget to adjust VDD so that
VDS = 6 V; it might be a good idea to record VDS at each measurement, just to force
yourself to double check that it is indeed close to 6 V. For now, use VBB = 0 so that the
body-to-source voltage VBS = 0. Use digital voltmeters to monitor VGS and VDS, and use a
digital ammeter to monitor IDS.
3
We'll derive this relationship in lectures. You'll see that K depends on such things as the MOSFET channel
mobility, oxide capacitance, and gate dimensions.
LS #3 - 5
(b) Repeat part (a) for VBS = -2, -4, -6, -8, -10, and -15 V. Notes: This may take some time--please work with your partner to take readings efficiently and patiently. Once you set VBS
to a given value, you don't have to worry about continuously checking it to ensure it hasn't
changed---it should stay constant regardless of VGS and IDS. On the other hand, don't
forget to maintain VDS at 6 V for all your readings!
(c) Using the tables of values you got in parts (a) and (b), and on the same graph, plot
I DS
versus VGS for each VBS. You should end up with six sets of plotted points, one for each
VBS value. Draw the best straight line through each set of points.
(d) Extrapolate each line drawn in part (c) back to IDS = 0 to get the corresponding threshold
voltage VT. Note that the value of VT is not the same for the different VBS values! This is
called body effect. In lectures, we'll assume that VBS = 0 in all our derivations and
analyses, but now you know that a nonzero body bias can affect the device operation! Is
the value of VT for VBS = 0 consistent with your estimate of VT in part (b) of section 3.3?
(e) Using the threshold voltage values from part (d), construct a plot of VT versus VBS. Draw a
smooth curve through the plotted points.
(f) The simple relationship
VT ≈ VTo + γ
(
Equation 4
ϕ − VBS − ϕ )
is sometimes used to model the effects of body bias on threshold voltage, where γ and φ are
model parameters and VT0 is the threshold voltage at VBS = 0. Is the shape of the curve you
constructed in part (e) consistent with such a relationship?
(g) Does a nonzero VBS value have any significant effect on the parameter K in equation 3?
Remember that K is just the slope of the I DS versus VGS plot, and use the lines you
plotted in part (c).
4
Conclusions: What You Learned!
In this lab, you've been introduced to both the JFET and enhancement MOSFET. Here are some
of the things that you hopefully got from doing this lab: a qualitative feel for the operation of
both the JFET and MOSFET; an idea of what the three-terminal characteristics of JFETs and
MOSFETs look like, and some of the device parameters that may be obtained from them; and an
idea of how MOSFET threshold voltage is affected by body bias.
LS #3 - 6
References
1. Donald A. Neamen. Semiconductor Physics and Devices, 3ed edition.
McGraw Hill , Toronto, 2003.
2. Ben G. Streetman and Sanjay Banerjee. Solid State Electronic Devices, 5 th edition.
Prentice Hall, Upper River, New Jersey, 2000. Chapter 6 covers the FET.
3. David H. Navon. Semiconductor Microdevices and Materials. Holt, Rinehardt and Winston,
New York, 1986. Chapter 10 covers field-effect devices. Sections 10.1, 10.2, and 10.4.4
contain good qualitative information that you may find useful for this lab.
4. Adel S. Sedra and Kenneth C. Smith. Microelectronic Circuits. Holt, Rinehart and Winston,
New York, third edition, 1991. Section 5.4 contains and excellent qualitative description of
the physical operation of an n-channel JFET, and section 5.4 contains a good description of
the three-terminal characteristics. Section 5.1 contains an excellent qualitative description of
the operation of an n-channel enhancement MOSFET. Please note that the equation in this
book are given from the point of view of a circuit engineer - we’ll derive somewhat more
rigorous equations in class from the point of view of a device engineer.
LS #3 - 7
Laboratory Study 4
Introduction to CAD for ELECTRONIC DEVICES
The lab involves the use of two CAD programs, BIPOLE and
MicroTec. ( Note: The MicroTec Lab Notes will be handed out in the lab room )
You will use one of these programs for the first half of the lab session and then you will
change to the other CAD program.
1.0 Laboratory Study 4(a)
Introduction to CAD using the BIPOLE Program
M. Vaidyanathan and A. M. Sarangan1
1.1. Introduction
An important aspect of semiconductor engineering is the use of computer-aided design
(CAD) programs. These programs allow an engineer to simulate and model the terminal
characteristics of semiconductor devices using only their physical structure as input, and
hence they play a crucial role in the optimization of device structures for different
applications.
In this lab, you will be introduced to CAD of semiconductor devices by way of the BIPOLE
program. BIPOLE is a device simulator written especially for bipolar devices, namely diodes
and transistors, and it takes into account two-dimensional and major three-dimensional
effects to accurately predict the terminal and internal characteristics of these devices. For
example, you could use BIPOLE to find the gain of a transistor, or you could use it to
determine the highest frequency at which a transistor can still be used as an amplifier;
moreover, you could examine how the structure of the transistor must be changed in order to
improve these quantities.
2.
Before the Lab
By the time you do this lab, you should have learned all about transistors in lectures.
Therefore, no background information is included in this write-up. It would be a good idea
for you to review your class notes on bipolar transistors before starting the lab.
This lab will be held in one of the engineering NEXUS computer rooms. The basics of using
BIPOLE on NEXUS are given in this write-up; you should look over the description before
the lab period in order to get an idea of what you'll be doing in the lab.
1
Based on exercises originally developed by Prof. D. J. Roulston
LS# 4 - 1
Since this is a computer lab, you could redo it on your own time. When you attend one of
the scheduled lab periods, you can take advantage of readily available help; in particular, note
that a teaching assistant or the lab instructor will give a tutorial on the use of BIPOLE, which
you may find useful.
Note:
At your computer, open a DOS window. Type ‘sbip tran1’ after the prompt. This will start
the Bipole simulator in a subdirectory called ‘tempbip’. We will work in this subdirectory.
Sbip stands for Student Bipole. The starting copy of our transistor file is named ‘Tran1.bip’.
3.
Using BIPOLE on NEXUS
3.1. BIPOLE Input Files
Input parameters to BIPOLE are specified using an input file. A BIPOLE input file must
have a name ending with the extension .BIP. The input file specifies the geometry and
material properties of the device we wish to simulate as well as the type of analysis we wish
to perform; for example, an input file might specify a high-performance VLSI transistor and
request analysis to predict its switching performance. Any unspecified input parameters are
automatically assigned preset default values by BIPOLE.
The input file for this lab is called TRAN1.BIP. The file is listed in section 4. You will be
told during the term how to access the file on NEXUS.
3.2. Changing Parameter Values and Running Simulations
You can make changes to BIPOLE input files through a menu system. To enter the menu
system, type SBIP at the DOS prompt. After the first menu appears on your screen, type R
to read an input file. Once the input file has been read, use the menu system to change
appropriate parameter values. After you have made all necessary changes, issue a W
command to save the changed set of input parameters in a new file. You will be asked to
enter a title for the new file. This title is used as a header in the new file and will appear on
created output when a simulation is run on the file. While executing W, a warning message
concerning tabular data may appear on your screen; you can ignore this message. After
saving the new file, type Q to exit the menu system.
To run a BIPOLE simulation on NEXUS, type SBIP infile at the DOS prompt where infile is
the name of a BIPOLE input file without the .BIP extension. The results of the simulation
will be stored in output files.
LS# 4 - 2
3.3. BIPOLE Output Files
Whenever a BIPOLE simulation is executed, a text output file with the extension .LST and
the same name as the input file is created. You can look at this file using any text editor. In
addition, a .BGD file will be created. This file contains graphics information, which can be
viewed using the BIPGRAPH program.
3.4. Using BIPGRAPH
BIPGRAPH can be used to plot BIPOLE simulation results. You can enter BIPGRAPH
simply by typing BIPGRAPH at the DOS prompt. BIPGRAPH is a Windows program; it
is straightforward to use the Windows system to select data from previously created .BGD
files and to plot various quantities.
3.5. Paper Plots
To get paper plots, make sure you invoke BIPGRAPH, then Load (open) Tran1.BGD from
your Bipole subdirectory. When the file has been loaded, use the BIPGRAPH menu to select
the Parameters of interest. Select the Grid and scale ranges. Plot the Parameters. By selecting
the ‘Save Post Script File’ button in BIPGRAPH you can save the plots as ‘Post Script Files’,
if you plan to print them at a later date. With the graph displayed in BIPGRAPH, you can
print to a printer, i.e. ‘Electrical-2’, if you right click the mouse. Post Script files can be view
from GostView, which is found in the Test and Document Tools, on your Start menu.
3.6. In the Lab
You will run a BIPOLE simulation by typing SBIP TRAN1 at the DOS prompt. The output
files TRAN1.LST and TRAN1.BGD should appear on your disk. Enter BIPGRAPH by
typing BIPGRAPH at the DOS prompt. You can remain in BIPGRAPH for all of parts (a) to
(e) below. To get paper plots see section 3.5 Paper Plots.
a) What do the terms net and effective doping mean? Plot the net and effective doping
profiles for TRAN1 up to a depth of 3 µm from the surface. Identify the emitter, base,
and collector regions on this plot. What is the depth of the emitter-base junction? What
about the collector-base junction? You must input both the x and y information when
changing the depth setting in BIPGRAPH.
b) Why is there a capacitance associated with the depletion region of a pn junction? Show
that this capacitance is a function of the total voltage across the junction. Plot the
collector-base junction capacitance of TRAN1 versus total collector-base voltage. If the
collector-base junction of TRAN1 has an area of Ac = 2200 µm2, then what is the
collector-base junction capacitance Cjc for a total collector-base voltage of VJCB = 5.7 V?
LS# 4 - 3
c) For modeling purposes, it is convenient to write the collector-base junction capacitance of
a transistor in the form
C jc =
C jc0
(VJCB / Vbic )
γc
Equation 1
where the symbols are as follows: Cjc0 is the capacitance at zero bias; VJCB = VCB + Vbic is
the total collector-base voltage; VCB is the applied collector-base voltage and will
typically be positive corresponding to a reverse bias at the collector-base junction; Vbic is
the built-in barrier voltage of the collector-base junction ; and
γc is the capacitance-voltage coefficient of the collector-base junction. For a perfectly
abrupt junction γc =1/2, and for a perfectly linearly-graded junction γc = 1/3. However,
the collector-base junction of a real transistor is neither perfectly linearly graded nor
abrupt. In fact, the behavior of the collector-base junction depends on the total junction
voltage VJCB. As a result, the value of γc depends on the total junction voltage VJCB.
γc = ( CB_Gamma )
Plot γc versus VJCB for TRAN1; (C-B Depl. Layer Capacitance Exponent MJC-vs-.
Vjtotal). How does γc change with voltage? For small values of VJCB, does the
collector-base junction behave like a linearly-graded or abrupt junction? What about for
larger VJCB?
(d) Plot the maximum electric field Εmax versus voltage for the collector-base junction of
TRAN1. What does the term avalanche breakdown mean? Assuming avalanche
breakdown at the collector-base junction of TRAN1 occurs for Εmax = 5 × 105 V/cm, is
there any danger of breakdown taking place for VJCB = 5.7 V?
(e) Explain what you understand by the term transition frequency fT. Plot fT versus IC for
TRAN1. How does the maximum fT from the plot compare with the value given by the
simple expression
f T ,max =
DB ,av
πWB2
Equation 2
where DB,av is the average electron diffusion coefficient in the base, and WB is the neutral
base width. In making your comparison, choose appropriate values for DB,av and WB.
Hint: You will need to use the plot you got in part (a).
(f) In this question, you will examine the effect of increasing the emitter area on the dc
current gain β and transition frequency fT.
To begin, exit BIPGRAPH. Reenter the BIPOLE menu system by typing SBIP at the
DOS prompt. Read the file TRAN1 using the R command. Use the menu system to
increase the width of the emitter stripe by a factor of two, and thereby increase the
LS# 4 - 4
emitter area Ae by a factor of two. What is the name of the BIPOLE input parameter you
had to change? Write the changed set of parameters to a new file TRAN2.BIP using the
W command. Exit the menu system by typing Q and run a BIPOLE simulation on
TRAN2 by typing SBIP TRAN2 at the DOS prompt. After the simulation is complete,
reenter BIPGRAPH by typing BIPGRAPH at the DOS prompt.
Plot the dc β versus IC for TRAN1 and TRAN2 on the same graph. Plot fT versus IC for
TRAN1 and TRAN2 on the same graph. For both graphs, explain why the curves are
shifted with respect to each other along the IC axis. On the β versus IC plot, label lowand high-current β falloff. On the fT versus IC plot, label high-current fT falloff.
If you wanted to increase the value of IC at which high-current β or fT falloff takes
place, would you increase or decrease the emitter area of a transistor? Explain.
(g) A processing engineer tells you that he made an error in characterizing recombination for
TRAN1. He says that he incorrectly specified the reference lifetime of carriers in the
E-B depletion layer; the actual value should be lower than the current value in
TRAN1.BIP by a factor of ten. As a result, he is worried that the low current gain might
be significantly lower than originally predicted.
With the file TRAN1.BIP as a starting point, and based on your experience from the
previous exercises, use the BIPOLE menu system and BIPGRAPH to obtain plots of the
(Beta DC) β versus IC for both values of reference lifetime in the E-B depletion layer,
that is, the original value and the new lower value. Is the gain significantly degraded? In
general, why might a lower base lifetime lead to a lower transistor gain?
(h) Explain how you expect the maximum transition frequency fT,max of a transistor to
change when the depth of the collector-base junction is increased. Be sure to include the
idea of transit time in your answer.
Assume that the diffused vertical impurity profile of TRAN1 is unchanged except for the
base-collector junction depth, which is increased from 1.0 µm to 1.2 µm. Use the
BIPOLE menu system and BIPGRAPH to determine how fT,max changes. Plot fT versus
IC for both values of collector-base junction depth on the same graph.
(i) One of the most important applications of bipolar transistors is in emitter-coupled logic
(ECL) gates. In fact, because of its high speed, ECL is the type of electronic logic
circuitry often used in high-end mainframe computers. As a result, given a bipolar
transistor, we often want to know how fast an ECL gate constructed using that transistor
will switch on and off, that is, we are often interested in the ECL propagation delay time
τPD associated with the transistor. You can plot this quantity using BIPGRAPH, as a
function of the collector current IC at which the transistor is biased in the ECL gate.
Plot the ECL propagation delay time, corresponding to a 1.0 V logic swing, for the two
values of collector-base junction depth mentioned in part (h) on the same graph. How do
the curves compare?
LS# 4 - 5
(j) Many device and circuit engineers use fT as an indicator of the potential ECL
performance of bipolar transistors. They feel that the same qualities, which yield a high
transition frequency, should also yield a low ECL propagation delay time. In other
words, these engineers say the following: “Given two transistors, and for a fixed
collector bias current IC, the device with higher transition frequency will yield a faster
ECL logic gate”. Based on the results you got for fT and τPD versus IC in parts (h) and (i),
what can you say about the validity of this statement?
3.7
BIPOLE Input File TRAN1.BIP
&TITLE
TRAN1: Typical low power transistor: default junctions at 0.6
and 1.0 micron
&PARAM
ITYPE=0,
# Make plotting work
ignu=0,
# Vcb bias and VBE minimum bias
VCIN=5.0,VBEMIN=0.6,
# Geometry
ELEM=4.E-04,B=10.E-04,
# collector doping level and depth from surface to N+
substrate
NB1=3.E18,NEPI=3.e15,XEND=5.0e-04,XSUB=0.1E-04,
# E-B scl lifetime
TAUDE=1.E-09,
&end
4. References
1. Donald A. Neamen. Semiconductor Physics and Devices, 3ed edition.
McGraw Hill , Toronto ,2003.
2. Ben G. Streetman and Sanjay Banerjee. Solid State Electronic Devices, 6 th edition
Prentice Hall, Upper River, New Jersey, 2005. Chapter 7 covers the BJT.
3. D.J. Roulston and BIPSIM Inc. 1998. STUDENT BIPOLE with MOSFET Option, User’s
Manual.
LS# 4 - 6
5.0 Laboratory Study 4(b)
Introduction to CAD using the MicroTec Program 2
This is the MicroTec Program (Ver.4.2) information for the Fall (2006) term.
5.1
Introduction
An important aspect of semiconductor engineering is the use of computer-aided design
(CAD) programs. These programs allow an engineer to simulate and model the terminal
characteristics of semiconductor devices using only their physical structure as input. Hence
they play a crucial role in the optimization of device structures for different applications.
In this lab, you will be introduced to CAD for semiconductor devices by way of the
MicroTec program. MicroTec allows 2D silicon process modeling including implantation,
diffusion, and oxidation and 2D steady-state semiconductor device simulation (MOSFET,
DMOS, JFET, BJT, IGBT, Schottky devices etc.). You can examine how changes in the
physical structure of the simulated transistor improves the quality of the MOSFET without
the cost of fabricating the device. Simulated model results are usually compared to lab
measurements made on the real devices. MOSFET models are used in circuit simulators like
PSPICE.
The MicroTec simulations will be run in lab room E2-2356 using the computers connected to
NEXUS as workstations. You will be running it in a ‘DOS Window’ on NEXUS. NEXUS is
running Windows XP. There are a limited number of computers running MicroTec in the lab,
so plan to “time share” with the other students. One half of the class will be using half the
computers to run the Bipole simulations and the other half will be running MicroTec. The run
time for one Output plot for the MOSFET using MicroTec can be 8 minutes. The results
from MicroTec will be used to find the ‘simulated’ Threshold Voltage, Transconductance
and output resistance for the MOSFET. You will be using the doping geometry for the
MOSFET of the real device that we used in the past years during Lab # 2. You are asked to
compare the simulated results with the measured results of the real device used in Lab # 2.
Look at the questions asked about the real device in Lab #2 and answer these same questions
for the simulated device. Compare the answers for the simulated and the real device. Note
any differences in geometries.
5.2
Before the Lab
By the time you do this lab, you may not have learned all about MOSFET transistors in
lectures. Therefore background information will be given at the start of the lab session and it
2
This MicroTec lab was a joint effort of P. Hayes and Michael S Obrecht from “Siborg Systems
Inc” first run in Jan.2000. M. Shah has made improvements to this latest version.
LS# 4 - 7
is a good idea to read the text. It would also be a good idea for you to review Laboratory
Study # 2: Introduction to Field-Effect Devices, in the lab manual, before starting the lab.
This MicroTec lab will be held in the Lab room E2-2356. The basics of using MicroTec on
NEXUS is given in this write-up. You should look over the description before the lab period
in order to get an idea of what you'll be doing in the lab.
Since this is a computer lab with a limit of Ten stations; you need to be on time. You need to
attend one of the scheduled lab periods. You can take advantage of readily available help; in
particular, note that a teaching assistant or one of the lab instructors will give a tutorial on the
use of MicroTec, which you may find useful.
Note:
If you turn off the MicroTec computer it may delete all the files that you have just created.
These files are stored in File N:\ tempMT. The graphic plots can be printed while in the lab
on printer ‘Electrical-2’ in the next room or stored on your disk as Post Script files. You will
need money on your printing account to print during the lab session.
6 Using MicroTec on NEXUS
6.1
MicroTec Input Files
The “Select_Project” folder contains our starting sample-input files. Input parameters to
MicroTec are specified using an input file. The MicroTec input file must have a name ending
with the extension .inp. The input file specifies the geometry and material properties of the
device we wish to simulate as well as the type of analysis we wish to perform; for example,
an input file might specify a high-performance VLSI transistor and request analysis to predict
its gain. Any unspecified input parameters are automatically assigned preset default values
by MicroTec .
The starting input file for this lab has the name ‘0.5um NMOSFET’ and can be found in the
‘Select_Project’ folder’. The Semiconductor Simulator ‘SemSim’ is our simulator. The
simulator we are using is displayed in the “Method’ box as “SemSim”. This starting file will
be modified. A sample of the modified listing can be seen in section 6.7, 6.8 of this lab. The
device fabrication information is in section 7. We will be generating two graphs with four
plots on each graph. We will then be analyzing these plots. The simulation run time for just
the output plot is 8 minutes.
6.2
Changing Parameter Values and Running Simulations
Start the MicroTec program by typing ‘MT’ at the DOS prompt in a DOS window. You can
make changes to MicroTec input files through a menu system. From the ‘Select_Project’
folder click on ‘0.5um NMOSFET’ to chose our sample mosfet input file. The input file will
be using the simulation method called ‘SemSim’ displayed in the “Method’ box as
LS# 4 - 8
“SemSim”. Next make a copy of the file by clicking on the copy button. Rename the file
(MOSFETthreshold) and hit the ‘update’ button. Go to the file folder “Project_Settings”
and make sure that all six directives (folders) have subdirectives (a + sign). Hit the ‘save
setting’ button. This is the sample-input file that we will modify to fit the specifications of
our device. Once we modify this input file we will press the ‘Run’ button to run a simulation
on our input device file. After a successful simulation the 2D and 3D button will be enabled.
Using the 2D and 3D buttons, we will generate output graphs.
6.3
MicroTec Output Files
Whenever a MicroTec simulation is executed, a text output file with the extension .inp is
created. You can look at this file using any text editor. In addition, .3D, .2D, .MDX, .DBF
files will be created. These files contain graphics and data base information.
6.4
Using the 2D and 3D Buttons
The Buttons marked 2D and 3D can be used to plot MicroTec simulation results. You can hit
the 2D button and from the curve menu select ‘add’. The ‘Family’ of curves that will be
selected are numbered 1, 3, 5, and 7. For the threshold voltage plot, the X-axis will be
selected as ‘Vg’ and Y-axis will be selected as ‘Id’. Press the ‘add’ button to add another
plot to the graph. It is straightforward to use the system to select data from previously created
files and to plot various quantities. Select the grid and legend options from the View menu.
6.5
Paper Plots
To get paper plots select from the file menu print and hit the print button. The printout will be
on Electrical-2 but you will to have need money on your printing account. Alternately you
could save the plots as Post Script files in your working directory (n:\tempMT) buy pressing
the print.ps button. The print button opens a box that asks for input.
6.6
In the Lab
Start the MicroTec program by typing ‘MT’ at the DOS prompt in a DOS window. This will
create a temporary folder “tempMT” in the directory you are working. Later on whenever you
are done with everything you should delete this “tempMT” folder. You can make changes to
MicroTec input files through a menu system. From the ‘Select_Project’ folder click ‘0.5um
NMOSFET’ to chose the sample mosfet input file. The input file will be using the
simulation method called ‘SemSim’ displayed in the “Method’ box as “SemSim”. Next
make a copy of the file by clicking on the copy button. Rename the file
(MOSFETthreshold) and hit the ‘update’ button. Go to the file folder “Project_Settings”
and make sure that all six directives have subdirectives. Make 3 more IV-data subdirectives.
This is done by right clicking on the last IV-data subdirective and left clicking and then
choosing the copy instruction. Hit the ‘save setting’ button. This is the sample-input file that
we will modify to fit our device.
LS# 4 - 9
Within a SemSim project we will create a NMOSFET device domain size of 300x72x5
(microns).
It is accepted in manufacturing to take the Y-axis to be positive in the downward direction.
In the Project_Setting folder expand all the folders. Clicking on the folder expands the
folders.
Parameter values may be changed by double clicking on the desired parameters.
Change the settings to those of the device that we will use in the lab.
The NMOSFET (w/l = 300/12) device domain size of 300x72x5 (microns) has the following
characteristics: (see section 6.7).
6.7
Project_Settings Input File for Id vs Vg
To display the Id vs Vg curves, run the input folder project settings that follow, section 6.7.1.
For the following settings, display the (2D) Id vs Vg curves by using the 'add' option from
the 2D menu. The curves are from the family data 1, 3, 5, and 7. The X-axis is Vg and the Yaxis is Id. From the graphs find the Threshold Voltages (the x intercepts) for the four
substrate bias conditions. How does the Threshold Voltage change with substrate bias
and why? In lab # 2 compare these results with the results measured in the lab.
Parameters are added by first left clicking then right clicking on a folder (subdirective name),
then choosing ‘Add Parameter’ from the menu. Similarly you can add other parameters if
you need to add them. Use the copy button to make 3 more IV-data subdirectives.
Now change the values of the following parameters in your project tree. Add the parameters
if they are not in your project tree.
6.7.1
The Project_Settings Input File for Id vs Vg (modify the MOSFETthreshold file to
read as follows):
BASIC
Mesh
Number of x-nodes to
number of y nodes to
Domain x size to
Domain y size to
Domain z size to
First y mesh step size
Remesh
61
30
72
5
300
0.003
3
LS# 4 - 10
Numerical Solution Parameters
comment line
subthreshold
batch mode
1
ELECTRODES
Ohmic Electrode
electrode name
electrode number
electrode location
electrode left edge
electrode right edge
Bulk
1
2
0
72
Ohmic Electrode
electrode name
electrode number
electrode location
electrode left edge
electrode right edge
source
2
1
0
30
Gate Electrode
electrode name
Gate
electrode number
3
electrode location
1
electrode left edge
30
electrode right edge
42
gate oxide thickness
0.13
location of interface charge
1e-2
width of interface charge
1e-2
interface charge density
4.6E+10
peak interface charge density
0
electron recombination velocity 1e-15
hole recombination velocity
1e -15
metal work function
4.1
Ohmic Electrode
electrode name
electrode number
electrode location
electrode left edge
electrode right edge
IV-Data
IV-curve label
ramped contact number
number of IV-points to compute
voltage step size
initial voltage for contact #4
initial voltage for contact #1
initial voltage for contact #3
initial voltage for contact #2
IV-curve label
ramped contact number
number of IV-points to compute
drain
4
1
42
72
IV-curve
3
22
0.3
0.1
0
0
0
IV-curve
3
22
LS# 4 - 11
voltage step size
initial voltage for contact #4
initial voltage for contact #1
initial voltage for contact #3
initial voltage for contact #2
0.3
0.1
-2
0
0
IV-curve label
ramped contact number
number of IV-points to compute
voltage step size
initial voltage for contact #4
initial voltage for contact #1
initial voltage for contact #3
initial voltage for contact #2
IV-curve
3
22
0.3
0.1
-4
0
0
IV-curve label
ramped contact number
number of IV-points to compute
voltage step size
initial voltage for contact #4
initial voltage for contact #1
initial voltage for contact #3
initial voltage for contact #2
IV-curve
3
22
0.3
0.1
-6
0
0
Analytical Doping data
comment
left edge of well
right edge of well
top edge of well
bottom edge of well
doping concentration
x characteristic length
y characteristic length
substrate
0
72
0
5
-5e+15
.05
.07
Analytical doping data
comment
left edge of well
right edge of well
top edge of well
bottom edge of well
doping concentration
x characteristic length
y characteristic length
source
0
30
0
0
2.5e+20
0.45
0.65
LS# 4 - 12
Analytical doping data
comment
left edge of the well
right edge of the well
top edge of the well
bottom edge of the well
doping concentration
x characteristic length
y characteristic length
1)
drain
42
72
0
0
2.5e+20
0.45
0.65
Press the save-setting button, 2) then press the run simulation button, 3) then plot (2D)
the four Vt graphs on one plot.
6.8
Project_Settings Input File for Id vs Vd for 4 different gate voltages
Make a second copy of the modified MOSFETthreshold file and rename it
MOSFEToutput. To display the Id vs Vd curves, run the input folder project settings
documented in section 6.8.1. For the following settings display the (2D) Id vs Vd for 4
different gate voltages. The curves are displayed by using the ‘add’ option from the 2D
menu. The curves are from family data 1, 3, 5, and 7. The X-axis is Vd and the Y-axis is Id.
Find the transconductance for the four gate bias conditions at Vd = 4 volts. How does
the current change with Vg and Vd and why? In lab # 2 compare these simulated
results with the results measured in the lab.
6.8.1
Project_Settings Input File for Id vs Vd for 4 different gate voltages (modify the
MOSFEToutput file to read as follows) :
BASIC
Mesh
Number of x-nodes to
number of y nodes to
Domain x size to
Domain y size to
Domain z size to
First y mesh step size
Remesh
41
20
72
5
300
0.003
3
Numerical Solution Parameters
comment line
subthreshold
batch mode
1
ELECTRODES
Ohmic Electrode
electrode name
electrode number
electrode location
electrode left edge
electrode right edge
Bulk
1
2
0
72
LS# 4 - 13
Ohmic Electrode
electrode name
electrode number
electrode location
electrode left edge
electrode right edge
source
2
1
0
30
Gate Electrode
electrode name
Gate
electrode number
3
electrode location
1
electrode left edge
30
electrode right edge
42
gate oxide thickness
0.13
location of interface charge
1e-2
width of interface charge
1e-2
interface charge density
4.6E+10
peak interface charge density
0
electron recombination velocity 1e-15
hole recombination velocity
1e -15
metal work function
4.1
Ohmic Electrode
electrode name
electrode number
electrode location
electrode left edge
electrode right edge
drain
4
1
42
72
IV-Data
IV-curve label
ramped contact number
number of IV-points to compute
voltage step size
initial voltage for contact #4
initial voltage for contact #1
initial voltage for contact #3
initial voltage for contact #2
IV-curve
4
10
0.5
0
0
2
0
IV-curve label
ramped contact number
number of IV-points to compute
voltage step size
initial voltage for contact #4
initial voltage for contact #1
initial voltage for contact #3
initial voltage for contact #2
IV-curve
4
10
0.5
0
0
3
0
IV-curve label
ramped contact number
number of IV-points to compute
voltage step size
initial voltage for contact #4
initial voltage for contact #1
IV-curve
4
10
0.5
0
0
LS# 4 - 14
initial voltage for contact #3
initial voltage for contact #2
4
0
IV-curve label
ramped contact number
number of IV-points to compute
voltage step size
initial voltage for contact #4
initial voltage for contact #1
initial voltage for contact #3
initial voltage for contact #2
IV-curve
4
10
0.5
0
0
5
0
Analytical Doping data
comment
left edge of well
right edge of well
top edge of well
bottom edge of well
doping concentration
x characteristic length
y characteristic length
substrate
0
72
0
5
-5e+15
.05
.07
Analytical doping data
comment
left edge of well
right edge of well
top edge of well
bottom edge of well
doping concentration
x characteristic length
y characteristic length
source
0
30
0
0
2.5e+20
0.45
0.65
Analytical doping data
comment
left edge of the well
right edge of the well
top edge of the well
bottom edge of the well
doping concentration
x characteristic length
y characteristic length
drain
42
72
0
0
2.5e+20
0.45
0.65
1) Press the save-setting button, 2) then press the run simulation button, 3) then plot (2D)
the four Vg graphs on one plot.
LS# 4 - 15
7 The SIDIC Lab Process Data , background infromation
ECE231 UW102 MOS Process Results
Follows are the results of the analysis of the process data for the MOS chips:
PARAMETER
UNITS
VALUE
Substrate:
Dopant atom
Orientation
Resistivity
Dopant Concentration
ohm-cm
at./cm3
Boron
<100>
1
1E+16
Source/Drain
Diffusion:
Dopant
Sheet Resistance
Junction Depth
Surface Concentration
ohms/sq
microns
at./cm3
Phos.
4.85
1.95
2.5E+20
Polysilicon Gate:
Thickness
Sheet Resistance
microns
ohms/sq
0.3
20
Gate Oxide Thickness
microns
0.13
cm2
pF
0.01
250
/cm2
4.6E+10
volts
1.32
microns
ohms/sq
1.15
0.027
Capacitor:
Area
Value
Surface State Charge,
Qss
Threshold Voltage
Aluminum Metal:
Thickness
Sheet Resistance
These parameters pretty well all were reconciled with each other in all the
calculations that linked Cs, NB, Vt, process data, and measured results.
1) Our large NMOSFET (w/l=300/12 microns), contact # 6,7,8 substrate is contact # 7
The Channel --Length is 12 microns -- Width is 300 microns
The Source/ Drain diffusion --Length is 30 microns --Width is 300 microns
LS# 4 - 16
8 Conclusions : What You have Learned---The questions that are asked in lab # 2 about the data for the real devices
can be used to compare the data from the simulations. Draw a cross
section of the Large NMOS transistors used in the lab and label the x, y,
and z directions used by this simulator.
9 References
4. Ben G. Streetman and Sanjay Banerjee. Solid State Electronic Devices, 6 th edition.
Prentice Hall, Upper River, New Jersey, 2006. Chapter 7 covers the BJT.
5. D.J. Roulston and BIPSIM Inc. 1998. STUDENT BIPOLE with MOSFET Option, User’s
Manual.
P.H. April 5 , 2007
LS# 4 - 17