International Electrical Engineering Journal (IEEJ)
Vol. 4 (2013) No. 1, pp. 918-925
ISSN 2078-2365
A SINUSOIDAL PWM SCHEME FOR NEUTRAL POINT
CLAMPED FIVE LEVEL INVERTER
SRIHARIRAO NAMBALLA
Power Electronics, Department of Electrical & Electrical Engineering,
Visakha institute of Engg& Tech, Visakhapatnam,(A.P), India.
E-mail: srihari63@gmail.com
Abstract: A power electronics device which converts DC power to AC power at required output
voltage and frequency level is known as an inverter. Two categories into which inverters can be
broadly classified are two level inverters and multilevel inverters. Some advantages that multilevel
inverters have compared to two level inverters are minimum harmonic distortion, reduced EMI/RFI
generation, and operation on several voltage levels. A multilevel inverter can be utilized for
multipurpose applications, such as an active power filter, a static VAR compensator and a machine
drive for sinusoidal and trapezoidal current applications. Some drawbacks to the multilevel inverters
are the need for isolated power supplies for each one of the stages, the fact that they are a lot harder to
build, they are more expensive, and they are more difficult to control in software. This focus of the
simulation is on study of three phase, three-level, and five-level inverters. Full analysis for three-level
and five-level inverter is included .Software packages MATLAB/SIMULINK is used to study and
simulate inverter waveforms. Firstly, three phase inverters are modeled with resistive load and
inductive load and their waveforms are observed. Secondly, a three-level inverter is modeled by
different ways and suitable switching control strategies (PWM technique) to carry out harmonic
elimination. Thirdly, a five-level inverter is modeled by different ways and suitable switching control
strategies (PWM technique) to carry out harmonic elimination. Finally, all inverters models are
modeled and run in by using MATLAB/SIMULINK. Three level and five level inverters both threephase are modeled, run and compared.
Index Terms—Multilevel inverter, neutral point clamped (NPC), sine pulse width modulation
(SPWM), switching state, five-level inverter
1.Introduction:
The power electronics device which converts
level inverter of desirable voltage and
DC power to AC power at required output
frequency has been achieved; however,
voltage and frequency level is known as an
harmonics distortion should be investigated
inverter. Two categories into which inverters
during operation. The pulse width modulation
can be broadly classified are two level
(PWM) strategies are the most effective to
inverters and multilevel inverters. One
control multilevel inverters. Even though sine
advantage that multilevel inverters have
pulse width modulation (SPWM) is
compared to two level inverters is minimum
complicated, it is the preferred method to
harmonic distortion. A multilevel inverter can
reduce power losses by decreasing the power
be utilized for multipurpose applications, such
electronics devices switching frequency,
as an active power filter, a static VAR
which can be limited by pulse width
compensator and machine drive for sinusoidal
modulation. Different aspects of the threeand trapezoidal current applications. Some
level NPC inverter will be discussed including
drawbacks to the multilevel inverters are the
the inverter topology. The operation theory
need for isolated power supplies for each one
will be discussed with the aspect of sine pulse
of the stages, they are more expensive, and
width modulation.
they are more difficult to control in software.
2. Five –level NPC inverter:
This paper focuses on the analysis of a three-
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A SINUSOIDAL PWM SCHEME FOR NEUTRAL POINT CLAMPED FIVE LEVEL INVERTER
International Electrical Engineering Journal (IEEJ)
Vol. 4 (2013) No. 1, pp. 918-925
ISSN 2078-2365
Multilevel
topologies
and
modulation
techniques have been developed and applied in
high power system. With the requirement of
quality and efficiency in high power systems
with the limitation of high power device
switching speed, low total harmonic distortion
(THD) and low switching frequency are
desirable.
MULTILEVEL
conversion
structures represent a solution to improve the
performances given by the classical structures
with two voltage levels. Multilevel structures
offer a reduction of the voltage stress that
compensates the increased number of devices.
Also these structures offer the advantage of
reducing the size of the output filter by
reducing the total harmonic content.
An important structure is the Active Neutral
Point Clamped Converter (ANPC) developed
in 2001. It presents the advantage of an
increased number of degrees of freedom. Also
it allows the combination with other concepts
in order to create structures with higher
number of voltage levels and output
parameters. Another class of multilevel
converters introduces the coupled inductor
concept. This type of converters offers an
increased number of voltage levels, lower
current stress in the semiconductor devices and
better output voltage properties.
The most commonly used topologies are
neutral-point-clamped (NPC). In neutral-pointclamped inverter the dc-link is split into
number of smaller voltage levels using a bank
of series connected bulk capacitors. The
inverter structure allows the connections of the
inverter poles to any of these voltage levels,
thus generating a multi-level voltage
waveform at the output.
A three-phase five-level diode-clamped
inverter is shown in Figure 1. Each of the three
phases of the inverter shares a common dc bus,
which has been subdivided by four capacitors
into six levels. The voltage across each
capacitor is Vdc, and the voltage stress across
each switching device is limited to Vdc through
the clamping diodes. Table1 lists the output
voltage levels possible for one phase of the
inverter with the negative dc rail voltage V0 as
a reference. State condition 1 means the switch
is on, and 0 means the switch is off. Each
phase has five complementary switch pairs
such that turning on one of the switches of the
pair require that the other complementary
switch be turned off. The complementary
switch pairs for phase leg a are (S a1, Sa‘1), (Sa2,
Sa‘2), (S a3, Sa‘3) and (S a4, Sa‘4). Table also
shows that in a diode-clamped inverter, the
switches that are on for a particular phase leg
is always adjacent and in series.
Fig.1.Three-phase five-level structure of a
neutral point clamped inverter.
Voltage Vao
Switching state
Sa4
Sa3
Sa2
Sa1
Sa‘4
Sa‘3
Sa‘2
Sa‘1
V4 = 4Vdc
1
1
1
1
0
0
0
0
V3 = 3Vdc
0
1
1
1
0
0
0
V2 = 2Vdc
0
0
1
1
1
0
0
1
1
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A SINUSOIDAL PWM SCHEME FOR NEUTRAL POINT CLAMPED FIVE LEVEL INVERTER
International Electrical Engineering Journal (IEEJ)
Vol. 4 (2013) No. 1, pp. 918-925
ISSN 2078-2365
V1 = 1Vdc
V0 = 0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
1
Table1: output voltage levels with switching states
The advantages of NPC inverter are:
(i) All of the phases share a common dc bus,
which minimizes the capacitance requirements
of the inverter. For this reason, a back-to-back
topology is not only possible but also practical
for uses such as a high-voltage back-to-back
inter-connection or an adjustable speed drive.
(ii)The capacitors can be precharged as a
group. (iii)Efficiency is high for fundamental
frequency switching.
3.Sinusoidal pulse width modulation
(SPWM): In sinusoidal PWM instead of
maintaining the width of all pulses the same as
in the case of multiple PWM, the width of
each is varied in proportion to the amplitude of
a sine wave evaluated at the same pulse. The
distortion is reduced significantly compared to
multiple PWM (Figure2).
Fig2. Spwm generating gate pulses
A high frequency triangular wave, called the
carrier wave, is compared to a sinusoidal
signal representing the desired output, called
the reference wave. Usually, ordinary signal
generators produce these signals. Whenever
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A SINUSOIDAL PWM SCHEME FOR NEUTRAL POINT CLAMPED FIVE LEVEL INVERTER
International Electrical Engineering Journal (IEEJ)
Vol. 4 (2013) No. 1, pp. 918-925
ISSN 2078-2365
the carrier wave is less than the reference, a
comparator produces a high output signal,
which turns the upper transistor in one leg of
the inverter on the lower switch off. In the
other case the comparator sets the firing signal
low, which turns the lower switch ON and
upper switch OFF.
The number of pulses per half cycle depends
on the carrier frequency. Within the constraint
that two transistors of the same arm cannot
conduct at same time, the instantaneous output
voltage is shown in Figure 2 the same gating
signals can be generated by using
unidirectional triangular carrier wave as in
Figure-5 this method is preferable and easier
to implement. The output voltage can be
varied by varying the modulation index ‗m‘.
The area of each pulse corresponds
approximately to the area under the sine wave
between the adjacent mid points of off-periods
on the gating signals. The SPWM, which is
most commonly used, suffers from certain
drawbacks like low fundamental output
voltage.
Advantages of SPWM:
The output voltage control is easier with
PWM than other schemes and can be
achieved without any additional components.
The lower order harmonics are either
minimized or eliminated altogether.
The filtering requirements are minimized as
lower order harmonics are eliminated and
higher order harmonics are filtered easily.
It has very low power consumption.
The entire control circuit can be digitized
which reduces the susceptibility of the circuit
to interference.
Sinusoidal Pulse Width Modulation (SPWM)
technique is used to generate the gate pulses.
SPWM technique is widely used in industries.
Neutral point clamped Three Level Inverter is
the modified version of Three Level Inverter
also discussed in this paper. FFT is used for
harmonic analysis of output of Three Level
Inverter. Simple Block Diagram of whole
system is given in Fig.3
Fig.3 Block Diagram
4.Simulation results: Simulation of various inverters using sinusoidal pulse width modulation was
carried out with the help of ―MATLAB 6.5‖. Simulation was carried out to observe the improvement
in the line voltage THD and Line Current THD as the inverter level increases from 3-level and 5level. The fig.4 and fig.5 shows final simulation diagram and corresponding simulation results of line
voltages and THD results are shown in fig.6, fig.7 and also fig. 8 shows THD analysis of 3-level
inverter
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A SINUSOIDAL PWM SCHEME FOR NEUTRAL POINT CLAMPED FIVE LEVEL INVERTER
International Electrical Engineering Journal (IEEJ)
Vol. 4 (2013) No. 1, pp. 918-925
ISSN 2078-2365
gate pulses
gate pulses
gate pulses1
3 ph wave
gate pulses 1
mod Voltage
gate pulses2
Subsystem
gate pulses3
gate pulses 2
Pulse Circuit
Scope
gate pulses 3
Discrete,
Ts = 5e-005 s.
npc inverter
powergui
Fig.4 five level simulation diagram with spwm
1
g
m
g
m
12
1
14
g
In18
2
11
m
1
In15
1
In16
g
9
2
In13
m
2
g
2
10
m
In14
2
6
1
In10
2
3
1
2
g
m
1
2
g
m
1
m
1
1
g
g
In3
8
In12
2
g
5
In9
2
2
1
2
In2
m
m
g
7
m
In11
2
4
In8
m
g
1
1
In1
g
1
2
1
m
+ v
-
g
g
1
m
1
g
24
2
In28
m
21
3
Vca
1
In25
2
Vbc
2
18
2
1
2
1
2
g
m
g
m
In22
m
23
1
In27
g
2
1
2
20
2
m
g
m
In24
In26
17
In21
m
2
1
m
1
19
g
In23
16
g
+ v
In20
1
Vab
15
2
g
In19
m
1
2
m
13
g
+
- v
In17
22
Fig.5 five level NPC inverter
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A SINUSOIDAL PWM SCHEME FOR NEUTRAL POINT CLAMPED FIVE LEVEL INVERTER
Selected signal: 5 cycles. FFT window (in red): 1 cycles
200
0
International Electrical Engineering Journal (IEEJ)
Vol. 4 (2013) No. 1, pp. 918-925
ISSN 2078-2365
-200
0
0.02
0.04
0.06
Time (s)
0.08
0.1
250
200
150
Fundamental (50Hz) = 184.7 , THD= 42.50%
100
15
vab
50
0
Mag (% of Fundamental)
-50
-100
-150
-200
-250
0
0.05
0.1
0.15
0.2
0.25
t
250
200
150
100
vbc
50
0
10
5
-50
-100
0
-150
-200
-250
0
0.05
0.1
0.15
0.2
0.25
t
0
50
100
150 200 250
Harmonic order
300
350
250
Selected signal: 50 cycles. FFT window (in red): 1 cycles
200
Fig8 THD results for 3level inverter
150
100
200
vca
50
0
-50
-100
0
-150
-200
-250
0
0.05
0.1
0.15
0.2
0.25
t
Fig6-200Line to line voltages of five level
0
0.2
0.4
0.6
0.8
inverter
1
Time (s)
Fundamental (50Hz) = 189.2 , THD= 27.95%
Mag (% of Fundamental)
8
6
4
2
0
0
50
100
150 200 250
Harmonic order
300
350
400
Fig7 THD results for 5level inverter
5. Performance Comparison Of Three &
five Level Inverters:
As we know that the output obtained from
a three-level inverter is not a pure sinusoidal
waveform. It is due to the presence of
harmonics in the inverter output voltage which
may cause heavy losses and may lead to low
efficiency or any other applications which may
take the supply from the inverter. So, there is a
need for us to reduce these harmonics. The
harmonics in a three level inverter is reduced
by increasing the switching frequency. But the
switching frequency is restricted by the
switching losses in high power applications. In
such applications multilevel inverters have
been widely used in recent years for the
advantage of low harmonic output at low
switching frequency. At the same time low
blocking in the switching devices can be
achieved. The more the number of levels of
the output voltage the lesser will be the
harmonic content. Multi level inverters have
advantages of good power quality, good
electromagnetic compatibility, low switching
losses, high voltage capability. These multi
level inverters are used in the active rectifiers
and the FACTS applications. The multi level
inverters synthesize several voltage levels
from the various levels of the DC input. A near
sinusoidal voltage waveform can be generated
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A SINUSOIDAL PWM SCHEME FOR NEUTRAL POINT CLAMPED FIVE LEVEL INVERTER
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International Electrical Engineering Journal (IEEJ)
Vol. 4 (2013) No. 1, pp. 918-925
ISSN 2078-2365
from the various levels of the DC input. They
have become attractive in the high power and
high voltage applications. By using the
multilevel inverters the stress on each device is
reduced proportional to the number of the
output levels present. With several levels in
the output waveform the switching dv/dt
stresses are reduced, and hence the lifetime of
motor and cables are increased. By using a
multilevel inverter the power rating of the
equipment can enhanced without any
dangerous consequences.
From the simulation results, I can say
that the total harmonic distortion reduces by
increasing the number of levels in the output
voltage and by the sinusoidal pulse width
modulation technique the total harmonic
distortion reduces. From the waveforms
obtained I can say that the output peak voltage
also increases with SPWM technique. The
switching losses also reduce with the SPWM
technique.
The THD for the three-level SPWM is
obtained as 42.50% and five-level SPWM are
obtained as 27.95% shown in fig8&7
respectively. It can be observed that the
control strategy has operated at a satisfactory
level.
6.Conclusions:
The following conclusions have been
made on five level NPC inverter. A number of
issues were investigated, including the inverter
configuration, operating principle, sinusoidal
modulation (SM) techniques, and neutral point
voltage control. The performance of the threephase five-level twenty four switch inverter
has been explained and observed that
performance of the inverter is improved by
employing SPWM control scheme. Sinusoidal
pulse width modulation algorithm has been
described and applied to three-level, five-level
inverter. Compared with conventional
methods, this method has the advantage of
ease implementing, especially for the inverters
with more levels. From simulation results it is
observed that the generated voltage spectrum
is very much improved with increase the level
of inverter. The use of five-level inverters
reduces the harmonic components of the
output voltage compared with the three-level
inverter at the same switching frequency. The
total harmonic distortion (THD) is highly
reduced as the level of the inverter is
increases. So no need additional reactors or
transformers to reduce the harmonic
components. Then, it is suitable for high
voltage and high power applications.
7.References:
[1] A.Nabae, I. Takahashi, H.Akagi ―A new
Neutral-Point Clamped PWM Inverter‖ IEEE
Trans. On Ind. App. Vol. IA- 17, No.5,
September/October 1981, pp 518-523.
[2] A. Kocalmis, ―Modelling and Simulation
of A Multilevel Inverter Using SVPWM‖,
MSc Thesis, Institute of Science, Firat
University, 2005.
[3] S.K., Mondal, B.K., Bose, V., Oleschuk,
J.O.P., Pinto, ―Space vector pulse width
modulation of three-level inverter extending
operation into over modulation region‖, IEEE
Transactions on Power Electronics, Vol.18,
pp.604 – 611, March 2003.
[4] A. Kocalmis, and S. Sunter, ―Modeling and
simulation of a multilevel inverter using space
vector modulation technique‖,
3rd Int. Conf. on Technical and Physical
Problems in Power Engineering (TPE-2006)
Ankara-Turkey, pp.940-943, 29-31 May,
2006.
[5] A. Kocalmis, ―Modelling and simulation of
a multilevel inverter using SVPWM‖, MSc
Thesis, Institute of Science, Firat University,
2005.
[6]B. Hariram and N. S. Marimuthu. 2005.
Space vector switching patterns for different
applicationsA
comparative analysis.
Proceedings of IEEE conference. pp. 14441449.
[7] B.K. Bose. 1986. Power electronics and ac
drives. Prentice hall Inc., Englewood Cliffs,
New Jersey.
[8] Jun Hu and Jie Chang, Rockwell Science
Center, 1049 Camino Dos Rios Thousand
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A SINUSOIDAL PWM SCHEME FOR NEUTRAL POINT CLAMPED FIVE LEVEL INVERTER
International Electrical Engineering Journal (IEEJ)
Vol. 4 (2013) No. 1, pp. 918-925
ISSN 2078-2365
Oaks, CA 91360, and Fang Z. Peng Oak Ridge
National Laboratory Oak Ridge, TN 3783 18058, Modular Design of Soft-Switching
Circuit for Two-Level and Three-Level
Inverters.
[9] Hind Djeghloud, Hocine Benalla, Space
Vector Pulse Width Modulation Applied to the
Three-Level Voltage Inverter, Electrotechnic's
Laboratory of
Constantine,
MentouriConstantine University, Constantine 25000,
Algeria.
[10] Ayşe Kocalmış and Sedat Sünter,
Simulation of a Space Vector PWM Controller
for a Three-Level Voltage-Fed Inverter Motor
Drive, Department of Electrical and Electronic
Engineering, Firat University, 23119, Elazig.
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A SINUSOIDAL PWM SCHEME FOR NEUTRAL POINT CLAMPED FIVE LEVEL INVERTER