Chinese Journal of Electronics
Vol.25, No.5, Sept. 2016
Novel Cascaded Z-Source Neutral Point Clamped
Inverter∗
HE Yuyao, LIU Hailong, FENG Wei and LI Jie
(School of Marine Science and Technology, Northwestern Polytechnical University, Xi’an 710072, China)
Abstract — Z-source Neutral point clamped (NPC) inverter inherits the advantages of Z-source inverter, which
can buck-boost energy and allow the shoot-through states.
At the same time, Z-source NPC inverter has high running efficiency and less harmonic content. Hence, it can
be widely used in motor drives and fuel cell applications.
When increasing the modulation index, one can only get
smaller shoot through value in Z-source NPC inverter,
therefore the output voltage of the inverter can not be
boosted very high. In this paper, a novel cascaded Z-source
neutral point clamped inverter is proposed by cascading
two Z-source networks in series. An Alternative phase opposition disposition (APOD) carrier-based modulator is
applied to control the proposed Z-source inverter. To confirm the operating principle of the new Z-source NPC inverter, a generic APOD carrier-based modulator for the
cascaded Z-source NPC Inverter under Matlab/Sinmulink
is built. The simulation results show that the boost factor
has been increased from 1/(1 − 2D) for the traditional Z
source NPC inverter to 1/(1 − 4D) for the proposed cascaded Z-source NPC inverter. A prototype of the cascaded
Z-source NPC inverter has been set up. The experimental results verify that the new topology can increase the
boost factor and expand the voltage regulation range of
the inverter.
Key words — Cascaded network, Z-source inverter,
Three-level, Boost factor, APOD.
I. Introduction
The Z-source Neutral-point-clamped (NPC) inverter
advantageously utilizes the shoot-through states
of the inverter bridge to boost DC link voltage. Theoretically, Z-source NPC inverter can produce infinite voltage
gain like many other DC-DC boost topologies[3,4]. However, this cannot be achieved due to the effects of parasitic
components and the dependence between shoot-through
interval and modulation index. In order to enable Z-source
NPC inverter to produce high voltage gain, smaller modulation factor should be adopted. However, smaller modulation factor could increase power losses and instability.
[1,2]
Also the voltage and current stresses on the switches of
the inverter would be high[5] . Therefore, a new Z-source
inverter topology should be developed. Then, a large modulation index can be used, and at the same time the boost
factor which can produce higher output voltage can be increased.
In recent years, many Z-source inverter topologies
have been proposed to increase voltage gain. Gajanayake
et al. proposed a extended boost ZSI topology which used
multi Z-source stages to increase the boost factor for twolevel inverter[6]. However, the extended boost ZSI topology can not avoid DC voltage unbalance when it is used
for three-level NPC inverter. The trans-Z-source inverter
in Ref.[7] and the T-Z-source inverter in Ref.[8] are those
kinds of inverters which employ transformer winding in
the impedance network. Trans-Z-source inverter can not
be applied to three-level NPC inverter, either. Unique
switched inductor and/or switched-capacitor are used to
replace the single inductor in the Z-source to design a
new kind of inverter which is called switched inductor
Z-source inverter[9] or switched-capacitor and switchedinductor Z-source inverter topologies[10] . They have the
ability to increase the boost factor from 1/(1 − 2D) to
(1 + D)/(1 − 3D) and (1 − D)/(1 − 3D), respectively.
Those boost voltage ability is not enough when they are
used in the practical applications where the input voltage
varies in a wide range, such as the fuel cell and photovoltaic power conditioning systems[11] . Theoretically, the
topology in Ref.[12] can increase boost factor through increasing the number of inductor, but the boost factor of
the primitive topology is too low compared with that of
the classical ZSI. So the voltage inversion ability of this
topology is fairly bad. What’s more, the DC link voltage
waveform is saw-tooth wave but not trapezoidal wave.
To overcome the aforementioned drawbacks in Z-
∗ Manuscript Received Nov. 15, 2014; Accepted July 9, 2015. This work is supported by the National Natural Science Foundation of
China (No.61271143).
c 2016 Chinese Institute of Electronics. DOI:10.1049/cje.2016.08.045
Chinese Journal of Electronics
966
source NPC inverter, this paper presents a new Z-source
NPC inverter topology with two Z-source networks in series, which is called cascaded Z-source NPC inverter. The
new topology can not only reduce Z-source network capacitor voltage and inductor current stresses, but also suppress the resonance by adopting a proper soft-start strategy. The boost factor of the proposed topology can be
increased from 1/(1 − 2D) to 1/(1 − 4D) . The operating
principle and comparison with the traditional topologies
reveal the merits of the proposed topology. Finally, theory, simulation, and experimental results are presented
in the paper to confirm the advantages of the proposed
topology and modulation concepts.
II. Traditional Z-Source NPC Inverters
The topologies of the traditional (classical) Z-source
NPC inverters are shown in Fig.1. Fig.1(a) shows the
topology of Z-source NPC inverter with upper and lower
Z-source impedance networks connected to its dc link and
supplied by two isolated dc sources[3]. For the upper Zsource network, voltage boosting can be affected by turning on, e.g., switches SU1 , SU2 and SU3 with diode D4
forward-biased, whereas for the lower Z-source network,
similar effect can be achieved by turning on SU2 , SU3 and
SU4 with diode D3 forward-biased. They should preferably be boosted for equal time intervals to avoid dc voltage unbalance[13] .
TU = TG = T0
(1)
Fig. 1. Topologies of the traditional Z-source NPC inverters.
(a) Topology of Z-source NPC inverter with two LC
impedance networks; (b) Topology of Z-source NPC
inverter using a single LC impedance network
where TU , TG are the time intervals of upper Z-source
2016
shoot-through state and lower Z-source shoot-through
state. T0 is effective shoot-through time.
As described in Ref.[2], the boost factor can be expressed as
B = 1/(1 − 2T0 /T )
(2)
B = 1/(1 − 2D)
where B is the boost factor determined by D and D is
the shoot-through duty ratio of each cycle and is equal to
T0 /T . The peak output phase voltage can be expressed as
V̂X = M V̂0 /2
(3)
where M is the modulation index, X ∈ U, V, W .
Fig.1(b) shows the topology of Z-source NPC inverter
with a single Z-source impedance network[14]. Compared
to the conventional NPC inverter topology, the Z-source
NPC inverter with a single Z-source impedance network
must function with an additional shoot-through state inserted when voltage-boost operation is commanded.
Given that the Z-source NPC inverter bridge is in the
shoot-through zero state for an interval of T0 , during a
switching cycle T , and from the equivalent circuit, as described in Ref.[14], the peak DC link voltage across the
inverter bridge can be expressed as
V̂0 =
1
VDC
1 − 2D
(4)
The peak output phase voltage can be expressed as
V̂X =
1
1
M V̂O
1
=
VDC = M BVDC
2
2 1 − 2D
2
(5)
where B = 1/(1−2D) is the boost factor, which should be
set to unity (D = T0 /T = 0) for voltage-buck operation
and B > 1 for voltage-boost operation.
The boost factors of Z-source NPC inverters with a
single or two Z-source impedance networks are 1/(1−2D).
In the classical Synchronized pulse width modulation
(SPWM) control strategy and a simple boost control
method, the obtainable modulation index M decreases
with the increase of the shoot-through duty ratio[15] . In
order to get an output voltage that requires a high voltage gain, G = M B, the modulation index M of the main
circuit should be decreased to a very low level. However,
small modulation indices result in greater voltage stress
on the switching devices[16] . But there is no voltage boost
and no voltage gain at M = 1. The theoretical relationship of modulation index M versus shoot-through duty
ratio D can be expressed by √
D ≤ 1 − M in simple boost
control method or D ≤ 1 − 3M in maximum constant
boost control method. The constraint of low M and high
D cause a new conflict of the output power quality and
system boost inversion ability[17] .
III. Cascaded Z-Source Neutral Point
Clamped Inverter
Novel Cascaded Z-Source Neutral Point Clamped Inverter
In order to obtain high boost factor for Z-source NPC
inverter at high modulation index, we propose a cascaded
Z-source NPC inverter with two Z-source impedance networks in series to couple the inverter main circuit to
the power source. The topology of the cascaded Z-source
NPC inverter is shown in Fig.2. Compared with Z-source
NPC inverter topologies in Fig.1, the boost factor of the
new cascaded Z-source NPC inverter can be increased to
1/(1 − 4D) from 1/(1 − 2D) for the traditional Z source
NPC inverters, that is, one can get a higher boost factor with smaller shoot-through duty ratio. Then a high
voltage gain of the new inverter can be obtained at high
modulation index M . The ripples of capacitor voltages
and inductor currents and the components size of Z-source
impedance networks can be reduced at smaller shootthrough duty ratio. Furthermore, Z-source network capacitor voltage and inductor current stresses are decreased.
At the same voltage gain G = V0 M , the new topology
can use larger modulation index and apply lower voltage
stresses on switching devices compared to traditional Zsource NPC inverter. Thus, the presented Z-source NPC
inverter would be expected to have good performances.
967
respectively, the Z-source network becomes symmetrical.
From the symmetry and the equivalent circuits, we have
Fig. 3. Simplified representations of the cascaded Z-source
NPC inverter when in (a) shoot-through and (b) nonshoot-through states
⎧
VL1 = VL2 = VLA
⎪
⎪
⎪
⎪
⎪
⎪
⎨ VC1 = VC2 = VCA
VL3 = VL4 = VLB
⎪
⎪
⎪
⎪
VC3 = VC4 = VCB
⎪
⎪
⎩
VC5 = VC6 = VCC
(6)
Fig. 2. Topology of the cascaded Z-source NPC inverter
1. Operational principles of the cascaded ZSource NPC inverter
Compared with the Z-source NPC inverter topology in
Fig.1(b), another Z-source impedance network is cascaded
in the new topology as shown in Fig.3.
One of the advantages of the proposed topology is that
the boost factor is much higher than that of the traditional Z-source NPC inverter. At the same time, the new
topology can make sure voltage balance of capacitors in Zsource impedance networks, which is applicable to threelevel neutral point clamped inverter. The equivalent circuits of the proposed cascaded Z-source NPC inverter are
shown in Fig.3. Assuming that the inductors and capacitors of each Z-source network have the same inductance
and capacitance, that is,
L1 = L2 = LA , L3 = L4 = LB
C1 = C2 = CA , C3 = C4 = CB , C5 = C6
Given that the inverter bridge is in the shoot-through zero
state for an interval of T0 during a switching cycle T , and
from the equivalent circuit in Fig.3(a), we have[17]
VLA = 2VCC + VCA
VLB = VCB
(7)
Now consider that the inverter bridge is in one of the eight
non-shoot-through states for an interval of T1 during the
switching cycle T . From the equivalent circuit in Fig.3(b),
we have
⎧
VLA = Vd1 − VCA
⎪
⎪
⎪
⎪
⎪
⎪
⎨ VLB = Vd2 − VCB
VCC = (Vo − Vd2 )/2
(8)
⎪
⎪
⎪
⎪
Vd2 = VCA − VLA
⎪
⎪
⎩
Vo = VCB − VLB
The average voltage of the inductors over one switching
period should be zero in steady state. From Eqs.(7) and
Chinese Journal of Electronics
968
2016
(8), thus, we have
V̄LA = (T0 (2VCC + VCA ) + T1 (Vd1 − VCA )/T = 0
V̄LB = (T0 VCB + T1 (Vd2 − VCB ))/T = 0
(9)
From T0 (2VCC + VCA ) + T1 (Vd1 − VCA ) = 0, we can get
VCA =
D
1−D
(2VCC −
Vd1 )
1 − 2D
D
(10)
where D = T0 /T is the shoot through duty ratio. From
T0 VCB + T1 (Vd2 − VCB ) = 0, we can get
VCB =
1−D
Vd2
1 − 2D
(11)
From Vo = VCB − VLB = 2VCB − Vd2 , we have
Vo =
Hence
VCC =
1
Vd2
1 − 2D
D
Vo − Vd2
=
Vd2
2
1 − 2D
Vd2 = VCA − VLA = 2VCA − Vd1
1 − 2D
Vd1
1 − 4D
(13)
1
1
Vd2 =
Vd1
1 − 2D
1 − 4D
G=
(15)
(16)
where Vd1 = 2Vdc , B = 1/(1 − 4D) > 1/(1 − 2D) is the
boost factor.
From Eq.(16), one can see that the boost factor (B)
for new topology is prompted to 1/(1 − 4D) compared to
1/(1 − 2D) for the topologies shown in Fig.1.
2. Performance analysis and comparison with
traditional Z-Source NPC inverters
In this subsection, we will give the performance analysis of the proposed cascaded Z-source NPC inverter and
the comparisons on boost factor, voltage gain, voltage
stresses on switching devices, modulation index versus
voltage gain with that of the traditional Z-source NPC
inverters.
As described above, the new topology can produce a
better voltage boosting at a small shoot through duty ratio. Fig.4 shows the relationships of the boost factor versus
the shoot through duty ratio for the proposed topology
and traditional topology in Fig.1, respectively. As can be
seen, the boost ability of the proposed topology is significantly increased compared with that of the traditional
Z-source NPC topology. The cascaded Z-Source NPC inverter topology produces an infinite boost factor when
shoot through duty ratio approaches D to 0.25.
v̂a
= MB
vin /2
(17)
where v̂a is the output peak phase voltage, and vin is the
input DC voltage. The voltage gain G for the proposed
topology under maximum boost control condition can be
expressed as
(14)
Substituting Eq.(15) into Eq.(12), then we have
Vo =
As defined in Ref.[15], the voltage gain G of the Zsource inverter can be expressed as
(12)
Substituting Eqs.(10) and (13) into Eq.(14), then we have
Vd2 =
Fig. 4. Boost ability comparison of two kinds of Z-source NPC
topologies
G=
2 1−D
v̂a
= MB = √
vin /2
3 1 − 4D
(18)
Fig.5 shows the maximum obtainable voltage gain G
versus the shoot through duty ratio D under this boost
control condition for the proposed topology and traditional topologies. It is shown that new topology exhibits
its advantage of stronger voltage boost inversion ability
at the low shoot through duty ratio, that is, the new
topology can provide higher output voltage at small shoot
through duty ratio, and then a large modulation index M
can be used. As expected, the cascaded Z-source NPC inverter topology can get an infinite voltage gain when the
shoot through duty ratio D approaches to 0.25.
Fig. 5. Voltage gain comparison of two kinds of Z-source NPC
topologies
As analyzed in Ref.[16], the voltage stress Vs across
the inverter switches is BVin . The voltage stress for the
proposed topology under this control method can be calculated as
√
2 3G − 1
Vs = BVin =
Vin
(19)
3
Novel Cascaded Z-Source Neutral Point Clamped Inverter
The voltage stress across switches versus the voltage gain
is plotted in Fig.6 for the proposed topology and traditional Z-source NPC topology. As shown in Fig.6, the voltage stresses on switching devices of the new Z-source NPC
inverter is lower than that of the traditional Z-source NPC
inverter.
969
current in turn appears as a ripple in the current through
the diode and source. Due to the smaller ripples allowed,
the changes in the capacitor voltage and inductor current
can be assumed as linear, instead of sinusoidal, for simple analysis and designing of Z-source inverter[17]. Fig.8
shows the waveforms of the capacitor voltage and inductor current under linear condition. The average values of
VCX are denoted by V̄CX (X ∈ {A, B, C}).
Fig. 6. Voltage stress on switching devices(2VDC = 300V )
For any desired voltage gain G under the maximum
boost control condition, the maximum modulation index
for the proposed Z-source NPC inverter can be expressed
as
3G
(20)
M=√
3−1
Fig.7 shows the obtainable modulation index versus
the voltage gain under this boost control method, where
curve 1 and curve 2 correspond to the proposed Z-source
NPC inverter and the traditional Z-source NPC inverter,
respectively. It is shown that for a given voltage gain
(G > 1), a higher modulation index can be used in the
proposed inverter to improve the inverter output performance.
Fig. 8. Linearized waveforms of (a) capacitor voltage and (b)
inductor current for small ripples
The average values of ILA and ILB are denoted by
I¯LA and I¯LB respectively, and the peak value of their ripples are given as ΔVCX (X ∈ {A, B, C}) and ΔILX (X ∈
{A, B}). During shoot-through time, the Z-source inductor current discharges the capacitors, therefore,
⎧
⎪
⎨ ICA = −ILA
ICB = −ILB
(21)
⎪
⎩
ICC = 2ICA
Consider the non-shoot-through states, then
ICA = ILA − ILB − ICB + ICC
ICB = ILB − Io − ICC
Fig. 7. Relationships of modulation index (M ) versus voltage
gain (G)
3. Parameters design of cascaded Z-source network
As we know, a ripple in the capacitor in turn appears
as a ripple in the DC link voltage applied to the voltage
source inverter. A large ripple in the DC link voltage degrades the waveform of the ac voltage by giving rise to
unexpected harmonics in addition to increasing the voltage rating of the VSI. Similarly, the ripple of the inductor
(22)
The average current of the capacitors over one switching
period is zero in steady state, we have
T0 (−ILA ) + T1 (ILA + Io − 2ILB + ICC ) = 0
(23)
T0 (−ILB ) + T1 (ILB − Io − ICC ) = 0
Form Eq.(23), we get
⎧ I
1−D
LA
⎪
=
⎨
Io
1 − 4D
1−D
⎪ ILB
⎩
=
Io
1 − 4D
(24)
970
Chinese Journal of Electronics
And the average current of the capacitor across shootthrough time is
ICC
2(1 − D)
(25)
=
Io
1 − 4D
The average currents of the capacitor CA , CB and CC
in shoot-through state are equal to the inductor currents,
the voltage ripples across the capacitors and the current
ripples across the inductors can be expressed as, 2ΔVCA =
I¯LA Δt/CA , 2ΔVCB = I¯LB Δt/CB , 2ΔVCC = I¯CC Δt/CB ,
2ΔILA = (V̄CA + 2V̄CC )DT /LA , 2ΔILB = V̄CB DT /LB .
From Eq.(10), Eq.(11), Eq.(13) and Eq.(15), we have
⎧
1 − 3D
⎪
VCA =
(2VDC )
⎪
⎪
1 − 4D
⎪
⎪
⎨
1−D
(26)
(2VDC )
VCB =
⎪
1
− 4D
⎪
⎪
⎪
⎪
D
⎩V
(2VDC )
CC =
1 − 4D
Assuming that cascaded Z-Source capacitor voltage ripple as ΔVCA = k1 V̄CA , ΔVCB = k2 V̄CB , ΔVCC = k3 V̄CC ,
the values of capacitors in each Z-source network can be
obtained as
⎧
(1 − D)DIo T
⎪
C1 = C2 =
⎪
⎪
⎪
2k1 (1 − 3D)(2VDC )
⎪
⎪
⎨
DIo T
C3 = C4 =
(27)
2k
⎪
2 (2VDC )
⎪
⎪
⎪
⎪
⎪
⎩ C5 = C6 = (1 − D)Io T
k3 (2VDC )
where k1 , k2 , k3 1. Assuming that cascaded Z-Source
inductor current ripples as ΔILA = m1 I¯LA , ΔILB =
m2 I¯LB , the values of inductors in each Z-source network
can be expressed as
⎧
VDC DT
⎪
⎨ LA =
4m1 Io
(28)
V
⎪
⎩ L = DC DT
B
4m2 Io
where m1 , m2 1.
For the traditional Z-source NPC topology, however,
during the shoot-through state, the value of capacitor and
inductor can be expressed as[17]
⎧
Io DT
⎪
⎨C=
2kEs
(29)
E
⎪
⎩ L = s DT
2mIo
where Es is equal to 2VDC and k 1, m 1.
For the same voltage gain, the cascaded Z-source NPC
topology only needs smaller shoot through ratio. Comparing Eqs.(27) and (28) with Eq.(29), one can see that
the values of capacitors and inductors in the cascaded Zsource NPC inverter can be smaller than that in the traditional Z-source NPC inverter with the same ripples when
2016
in the situation of same voltage gain, capacitor voltage
and inductor current of inverters.
If the source voltage, load current, switching period
and duty ratio of shoot-through state are known, C and
L for any control strategy can be calculated from Eqs.(27)
and (28). To demonstrate the design process based on approximate method, an illustrative example of calculating
parameters for the cascaded Z-source networks is given as
follows.
Suppose that input voltage of two DC sources are
150V, D is 0.1, and M is 0.85. Working frequency of the
inverter is 10kHz. Load resistance and load inductance
are 4Ω and 1mH, respectively. The ripples of the capacitor voltages are ΔVCA ≤ 0.1%VCA , ΔVCB ≤ 0.1%VCB ,
ΔVCC ≤ 4%VCC . The ripples of the inductor currents
are ΔILA ≤ 20%ILA , ΔILB ≤ 20%ILB , the capacitances
and inductances of the cascaded Z-source networks can
be calculated by Eqs.(27) and (28) as C1 = C2 = 279µF,
C3 = C4 = 211µF and C5 = C6 = 1640µF, LA = 144µH,
LB = 112µH. If we choose CA = 300µF, CB = 300µF,
C5 = C6 = 1500µF and LA = 200µH, LB = 200µH, the
ripples required will be satisfied for the topology.
IV. Modulation Scheme
While inserting shoot-through states into the inverter
state sequence, it is important to ensure that the correct
normalized volt-sec average is produced at all instances,
regardless of the angular position of the reference phase.
With this criterion in mind, the proposed inverter can be
controlled using a generic Alternative phase opposition
disposition (APOD) carrier-based modulator with an appropriate tripled offset and time advance/delay added[19]
as shown in Fig.9, where the corresponding state sequence
for controlling a conventional three-level inverter is also
shown for comparison.
Fig.9 shows that the inserted shoot-through states are
not affected by turning ON all switches from the same
phase leg. Instead, the shoot-through states are inserted
by synchronizing the turning ON of switches from two systematically selected phase legs. Using this approach, the
number of device commutations needed for a switching cycle is the same as that needed by a conventional three-level
inverter (minimum of six per half-carrier cycle), which is
four less than that needed by the approach of turning
ON all switches from a phase simultaneously. Where it is
noted that turning ON of SU1 and SW 4 at t1 ∼ 0.5T0 to
initiate the first shoot-through state is affected by using
two additional references Vu(SU1) and Vw(SW 2) , as illustrated in Fig.9 for a cascaded Z-source NPC inverter. The
termination of the shoot-through state is affected by using the original references Vu(SU2) and Vw(SW 1) to turn
off SU3 and SW 2 .
Comparing the two sets of references and translating
Novel Cascaded Z-Source Neutral Point Clamped Inverter
the horizontal time interval of 0.5T0 to a normalized vertical offset of T0 /T , the additional references Vu(SU1) and
Vw(SW 2) are observed to derive from the original references by adding T0 /T to Vu(SU2) and subtracting the same
offset from Vw(SW 2) .
971
To verify the cascaded Z-source NPC inverter designed
and modulation concepts presented, extensive simulation
studies are performed on the open loop configuration of
the proposed topology in Matlab/Simulink. The simulation parameters are: two DC input voltage VDC = 150V,
Z-source network: C1 = C2 = C3 = C4 = 300µF,
C5 = C6 = 1500µF, L1 = L2 = L3 = L4 = 200µH. Load:
resistance R = 4Ω, inductance L=1mH per phase. Switching frequency: f = 10kHz; Modulation ratio M = 0.85;
Shoot-through duty ratio D = 0.1. Fig.10 and Fig.11 show
the simulation results of the traditional and cascaded Zsource NPC topologies, respectively. The waveforms from
top to bottom are DC link voltage Vo , output line voltage Vab , output phase voltage Va , and load current iL ,
respectively.
Fig. 10. Simulated waveforms of the traditional Z-source NPC
inverter M =0.85, D=0.1
Fig. 9. APOD modulation of conventional and cascaded Zsource NPC inverter
In addition to the vertical offset, to synchronize the
gating of phases U and W , a triple offset expressed as
Eq.(30) must be added to the original set of three-phase
sinusoidal references to center the resulting modified references vertically within the disposed carrier bands. Proceeding to add all offsets to the original sinusoids, the
resulting set of references needed for controlling the proposed the cascaded Z-source NPC Inverter is expressed
as
Voffset = −0.5[max(νa , νb , νc ) + min(νa , νb , νc )]
⎧
Vmax(X1) = Vmax + Voffset + To /T
⎪
⎪
⎪
⎪
Vmax(X2) = Vmax + Voffset
⎪
⎪
⎪
⎪
⎨V
mid(X1) = Vmax + Voffset
⎪
Vmid(X2) = Vmax + Voffset
⎪
⎪
⎪
⎪
⎪
⎪ Vmin(X1) = Vmax + Voffset
⎪
⎩
Vmin(X2) = Vmax + Voffset − To /T
(30)
Fig. 11. Simulated waveforms of the cascaded Z-source NPC
inverter M =0.85, D=0.1
(31)
where X ∈ A, B, C.
V. Simulation and Experimental Results
The peak DC link voltage across the traditional Zsource NPC inverter bridge can be calculated as 375V
based on Eq.(4) and the peak DC link voltage across the
cascaded Z-Source NPC inverter bridge can be obtained
as 500V based on Eq.(16).
In Fig.11, we can see that a higher boost voltage is
produced with same shoot through time intervals in the
cascaded Z-Source topology. The simulation results coin-
972
Chinese Journal of Electronics
2016
cide well with the calculation results.
When the voltage gain G = BM of two inverters is
3.33 and the same output currents (iL = 100A) are required, simulation results are given in Fig.12 and Fig.13
as other parameters are the same as used in Fig.10 and
Fig.11. One can see that the cascaded Z-source NPC inverter needs smaller D and gets a larger M than that in
the traditional Z-source NPC inverter, and the voltage
stress on switch devices in the cascaded Z-source NPC inverter is also lower than that in traditional Z-source NPC
inverter.
Fig. 14. Experimental waveforms of the traditional Z-source
NPC inverter
Fig. 12. Simulated waveforms of the traditional Z-source NPC
inverter M =0.6983, D=0.3952
Fig. 15. Experimental waveforms of the cascaded Z-source
NPC inverter
VI. Conclusion
Fig. 13. Simulated waveforms of the cascaded Z-source NPC
inverter M =0.9481, D=0.1789
Prototype of the cascaded Z-source NPC inverter is
built in the laboratory to validate the proposed Z-source
NPC topology. The parameters used in the experiment
are the same as in simulation. Reference signals are generated using TMS320F2812 based hardware environment
and modulation signals are derived based on the APOD
modulation method. Fig.14 and Fig.15 shows the experimental results of traditional and cascaded Z-source NPC
inverters, respectively. Channel 1 shows DC link voltage
across the inverter bridge. Channel 2 shows load current.
The experimental waveforms show that cascaded Zsource NPC inverter can produce higher output voltage.
This paper has presented a cascaded Z-source neutral
point clamped inverter topology with cascading two Zsource networks in series. The operational principle and
an APOD carrier-based modulator of the proposed Zsource NPC inverter are given. Comparison with the traditional Z-source NPC topologies reveals the merits of
the proposed topology. The boost factor of the proposed
topology can be increased to 1/(1−4D) from 1/(1−2D) of
the traditional Z-source NPC inverter. The new topology
can also reduce Z-source network capacitor voltage and inductor current stresses. The voltage stresses on switching
devices of the new Z-source NPC inverter can be smaller
than that of the traditional Z-source NPC inverter in the
case of the same voltage and current ripples. A generic
APOD carrier-based modulator for the cascaded Z-source
NPC Inverter under Matlab/Sinmulink is built. Finally,
theory, simulation, and experimental results presented
confirm the proposed topology and modulation concepts.
The proposed cascaded Z-source NPC inverter is suitable
in applications where the input voltage varies in a wide
range, such as the fuel cell and photovoltaic power conditioning systems.
Novel Cascaded Z-Source Neutral Point Clamped Inverter
References
[1] Oleksandr Husev, Carlos Roncero Clemente, Enrique Romero
Cadaval, et al., “Single phase three-level neutral-point-clamped
quasi-Z-source inverter”, IET Power Electronics, Vol.8, No.1,
pp.1–10, 2015.
[2] P.C. Loh, F. Gao, Frede Blaabjerg, et al., “Pulse width modulated Z-source neutral point clamped inverters”, IEEE Transactions on Industry Applications, Vol.43, No.5, pp.1295–1308,
2007.
[3] P.C. Loh, D.M. Vilathgamuwa, Y.S. Lai, et al., “Pulsewidth modulation of Z-source inverters”, IEEE Transactions
on Power Electronics, Vol.20, No.6, pp.1346–1355, 2005.
[4] D. Li, P.C. Loh, M. Zhu, et al., “Enhanced boost Z-source
inverters with alternate cascaded switched and tapped inductor cells”, IEEE Transactions on Industrial Electronics, Vol.60,
No.9, pp.3567–3578, 2013.
[5] Shuai Dong, Qianfan Zhang and Shukang Cheng, “Analysis of
critical inductance and capacitor voltage ripple for a bidirectional Z-source inverter”, IEEE Transactions on Power Electronics, Vol.30, No.7, pp.4009–4015, 2015.
[6] C.J. Gajanayake, F.L. Luo, H.B. Gooi, et al., “Extended boost
Z-source inverters”, IEEE Transactions on Power Electronics,
Vol.25, No.10, pp.2642–2652, 2010.
[7] W. Qian, F.Z. Peng and H.Y. Zha, “Trans-Z-source inverter”,
Power Electronics Conference (IPEC), East Lansing, USA,
Michigan State University, pp.3453–3463, 2010.
[8] M.K. Nguyen, Y.C. Lim and Y.G. Kim, “T Z-source inverters”,
IEEE Transactions on Industrial Electronics, Vol.60, No.9,
pp.5686–5695, 2013
[9] M. Wei, P.C. Loh and F. Blaabjerg, “Asymmetrical transformer-based embedded z-source inverters”, IET Power Electronics, Vol.6, No.2, pp.261–269, 2013.
[10] A.V. Ho, T.W. Chun and H.G. Kim, “Development of multi-cell
active switched-capacitor and switched-inductor Z-source inverter topologies”, Journal of Power Electronics, Vol.14, No.5,
pp.834–841, 2014.
[11] S.T. Yang, X.P. Ding, F. Zhang, et al., “Study on Z-source inverter for photovoltaic generation system”, Proceedings of the
CSEE, Vol.28, No.17, pp.112–118, 2008.
[12] Lei Pan, “L-Z-Source Inverter”, IEEE Transactions on Power
Electronics, Vol.29, No.12, pp.6534–6543, 2014.
[13] J. Zhang and B. Qi, “Neutral-point potential balancing method
for Z-source three-level NPC inverters”, Proceedings of the
CSEE, Vol.30, No.12, pp.7–13, 2010.
[14] P.C. Loh, S.W. Lim, F. Gao, et al., “Three-level Z-source inverters using a single LC impedance network”, IEEE Transactions
on Power Electronics, Vol.22, No.2, pp.706–712, 2007.
[15] F.Z. Peng, “Z-source inverter”, IEEE Transactions on Industry
Applications, Vol.39, No.2, pp.504–510, 2003.
973
[16] F.Z. Peng, M. Shen and Z.M. Qian, “Maximum boost control
of Z-source inverter”, Proceedings of 2004 35th Annual IEEE
Power Electronics Specialists Conference, pp.255–260, 2004.
[17] M. Shen, J. Wang, A. Joseph, et al., “Constant boost control
of the Z-source inverter to minimize current ripple and voltage
stress”, IEEE Transactions on Industry Applications, Vol.42,
No.3, pp.770–778, 2006.
[18] Y.P. Hsieh, J.F. Chen, L.S. Yang, et al., “High ratio bidirectional dc-dc converter with coupled inductor”, IEEE Transactions on Industry Applications, Vol.61, No.1, pp.210–222, 2014.
[19] P.C. Loh, D.G. Holmes, Y. Fukuta, et al., “Reduced common mode modulation strategies for cascaded multilevel inverters”, IEEE Transactions on Industry Applications, Vol.39,
No.5, pp.1386–1395, 2003.
[20] Weiguo Liu and Hucheng He, “State plane analysis and soft
switching condition of novel resonant DC link inverter”, Acta
Electronica Sinica, Vol.37, No.9, pp.2052–2057, 2009.
[21] Jizhong Wang and Jiangyu Li, “Harmonic analysis of power
supply net side with large synchronous frequency speed drive
system”, Acta Electronica Sinica, Vol.42, No.5, pp.1035–1040,
2014.
HE Yuyao
was born in Shaanxi
Province, in Nov. 1956. He received the
B.S. degree in aircraft control system from
BeiHang University in 1982; the M.E. degree in systems engineering from Xi’an
Jiaotong University in 1984; the Ph.D. degree in weapon science and technology from
Northwestern Polytechnical University in
1999. He was a visiting professor in Clemson University in USA (1986.08–1987.09);
in Deakin University in Australia (1998.03–1998.12); in Cleveland State University in USA (2002.01–2003.01), respectively. He
is currently a professor in the Northwestern Polytechnical University. His research interests include power electronics, motor control technology, intelligent control and nonlinear control. (Email:
heyyao@nwpu.edu.cn)
LIU Hailong
was born in Henan
Province, in Nov. 1980. He received the
B.S. degree in electrical engineering and
automation and the M.E. degree in traffic information engineering from Chang’an
University, China in 2004 and 2007, respectively. Now he is a Ph.D. candidate of
weapon science and technology in Northwestern Polytechnical University. His research interests include power electronics,
power converters, and motor control technology. (Email: liuhlonglong@126.com )