A NOVEL DITHERING ALGORITHM TO REDUCE ELECTRO MAGNETIC
INTERFERENCE IN VOLTAGE SOURCE INVERTERS
A Thesis
Presented to
The Graduate Faculty of The University of Akron
In Partial Fulfillment
of the Requirements for the Degree
Master of Science
Krishna Mohan Pavan Kumar Namburi
August, 2012
A NOVEL DITHERING ALGORITHM TO REDUCE ELECTRO MAGNETIC
INTERFERENCE IN VOLTAGE SOURCE INVERTERS
Krishna Mohan Pavan Kumar Namburi
Thesis
Approved
Accepted
Advisor
Dr. Yilmaz Sozer
Department Chair
Dr. Alex De Abreu-Garcia
Committee Member
Dr. Malik Elbuluk
Dean of the College
Dr. George K. Haritos
Committee Member
Dr. Tom T. Hartley
Dean of the Graduate School
Dr. George R. Newkome
Date
ii
ABSTRACT
The use of power electronic converters is increasing rapidly in clean energy
power generation systems such as solar/wind power generation and electric vehicles
applications. Electro Magnetic Interference (EMI) is a major concern in power electronic
based energy conversion systems. The EMI issues in the PWM inverter system arises
from the high
and
rates, which are due to the fast switching of the power
semiconductor devices.
Dithering the switching frequency of an inverter over a particular range can
reduce the
stresses of the power semiconductor devices, and consequently the EMI
noise. In this research, a dithering algorithm to reduce the
of the switches is proposed
and the relationship between the parameters used in the dithering of the switching
frequency is developed.
A relationship is developed among the various parameters involved in the
dithering concept. Two important parameters involved in dithering concept are the
dithering frequency range (
to
), and the sweeping frequency (
) for a
given fundamental frequency. An analysis is done for different dithering ranges by
sweeping frequencies for minimization of the EMI. A relationship between the important
parameters is developed by doing the FFT analysis of the switch voltage of the two level
and three level inverter system for various combinations of dithering ranges and
iii
sweeping frequencies. Peak values of the FFT spectrum of the switch voltage have been
observed for various dithering ranges and sweeping frequencies. The relationship has
been developed through simulation studies and results are verified with an experimental
system.
The PWM inverter system analyzed is a three phase two level voltage source
inverter. The inverter has been controlled using both the space vector pulse width
modulation and sinusoidal pulse width modulation techniques. The dithering algorithm
has been applied in the generation of PWMs and the results have been analyzed for EMI
reduction capability.
Keywords: Electromagnetic Interference, Dithering, Power Electronic Converters, and
FFT Analysis.
iv
DEDICATION
Dedicated to my family and teachers
v
ACKNOWLEDGEMENTS
I would like to thank the committee members Dr. Yilmaz Sozer , Dr. Iqbal Husain
Dr. Malik Elbuluk and Dr. Tom Hartley for their guidance and support throughout my
Master’s program. I would like to specially thank Dr. Yilmaz Sozer and Dr. Iqbal Husain
for helping me throughout this thesis work and shaping my thoughts and research work
into a good manuscript. I am thankful to Dr. Malik Elbuluk for being in my committee
and for the experience I gained working as a teaching assistant with him. I am thankful to
Dr. Tom Hartley for being in my committee and for the advice and suggestions given to
me regarding this thesis.
I truly appreciate Mrs. Gay Boden for her help right from the day I stepped into
the graduate school. Thanks to Erik Rinaldo and Greg Lewis for helping me with all
necessary infrastructure to complete my research work. I am thankful to the Department
of Electrical and Computer Engineering for supporting me through teaching
assistantships.
I would like to thank my friends Sreeshailam, Sriram, Yu Zou and Arafat who
were always there when I needed them. Finally, I am thankful to my mother for her love
and support. I owe all my success to my parents and my family.
vi
TABLE OF CONTENTS
Page
LIST OF FIGURES……………………………………………………………………….x
LIST OF TABLES…………………………………………………………………….....xii
CHAPTER
I.
II.
INTRODUCTION…………………………………………………………...........1
1.1
Power Electronic Inverters………………………………………………...1
1.2
Research Motivation……………………………………………………....2
1.3
Research Objectives……………………………………………………….4
1.4
Thesis Organization……………………………………………………….4
ELECTRO MAGNETIC INTERFERENCE……………………………………...6
2.1
Introduction………………………………………………………………..6
2.2
Sources of EMI……………………………………………………………6
2.3
EMI Issues in Power Electronic Drives…………………………………...7
2.4
EMI Classification………………………………………………………...7
2.5
Analytical EMI Identification Method….………………………………..10
2.6
Mitigation of EMI Noise in Power Converters using Passive Filters……12
2.7
Mitigation of EMI Noise in Power Converters with Various PWM
Patterns…………………………………………………………………………...13
2.8
Summary………………………………………………………………....14
vii
III.
DITHERING ALGORITHM FOR MITIGATION OF EMI…………………….15
3.1
Introduction………………………………………………………………15
3.2
Effect of Switching Frequency Dithering on EMI……………………….15
3.3
Dithering Strategy………………………………………………………..17
3.4
Implementation of Dithering Algorithm on Power Electronic Inverters...19
3.5
3.6
IV.
V.
3.4.1
Two Level Inverter………………………………………………19
3.4.2
Multilevel Inverter……………………………………………….21
PWM Switching Strategies of Inverters…………………………………23
3.5.1
Sinusoidal Pulse Width Modulation……………………………..23
3.5.2
Space Vector Pulse Width Modulation…………………………..24
Summary…………………………………………………………………31
DEVELOPMENT OF SWEEPING STRATEGY FOR THE DITHERING
TECHNIQUE BASED ON SIMULATIONS……………………………………32
4.1
Introduction………………………………………………………………32
4.2
Control of 3-phase Two Level Inverter using SVPWM Dithering………32
4.3
Control of 3-phase Two Level Inverter using Sine PWM Dithering…….37
4.4
Control of 3-Phase Cascaded H-bridge Three Level Inverter using
SVPWM Dithering……………………………………………..………...42
4.5
Control of 3-Phase Cascaded H-bridge Three Level Inverter using Sine
PWM Dithering…………………………………………………………..47
4.6
Comparison of PWM Techniques with respect to EMI………………….52
4.7
Summary…………………………………………………………………52
HARDWARE IMPLEMENTATION AND EXPERIMENTAL RESULTS…...54
5.1
Introduction………………………………………………………………54
5.2
Hardware Implementation......…………………………………………...54
viii
Inverter Module Circuit………………………………………….55
5.2.2
DSP to Inverter Module Interface………………………………..56
5.2.3
Fault Output Interface ………..……………………………….…56
5.2.4
Voltage Sensor Circuitry…………………………………………56
5.2.5
House Keeping Power Supplies………………………………….57
5.3
Embedded Control Program……………………………………………..57
5.4
Test Setup………..………………………………………………………61
5.5
Experimental Results…………………………………………………….62
5.6
VI.
5.2.1
5.5.1
Control of 3-phase 2 Level Inverter using SVPWM Dithering….62
5.5.2
Control of 3-phase 2 Level Inverter using Sine PWM Dithering..68
Summary…………………………………………………………………74
CONCLUSION AND FUTURE WORK………………………………………..76
REFERENCES…………………………………………………………………………..78
APPENDICES..................................................................................................................80
APPENDIX A .
SIMULINK DIAGRAMS……………………………………….81
APPENDIX B .
MATLAB CODES………………………………………………85
APPENDIX C .
SCHEMATICS…………………………………………………..93
APPENDIX D .
PCB LAYOUTS………………………………………………..100
ix
LIST OF FIGURES
Figure
Page
1.1
General Inverter operation………………………………………………………...1
2.1
Common mode and differential mode current paths in a PWM drive…………...10
3.1
Representation of switch voltage………………………………………………...17
3.2
Frequency spectrum of switch voltage………...………………………………...17
3.3
Proposed dithering method………………………………………………………18
3.4
Three-phase VSI topology……………………………………………………….20
3.5
Cascaded H-bridge multilevel inverter using two DC sources…………………..22
3.6
Voltage output of cascaded H-bridge multilevel inverter………………………..23
3.7
Principle of sine PWM…………………………………………………………...24
3.8
Three-phase inverter……………………………………………………………..25
3.9
Switching vectors of inverter using SVM………………………………………..26
3.10
Determination of switching times………………………………………………..27
3.11
Switching state vectors of a three level inverter in hexagonal coordinate system29
3.12
Flowchart of SVM three level inverter…………………………………………..31
4.1
Spectrum of switch voltage for dithering range of 16-20 kHz with a sweep
frequency of 960 Hz………………………………………………………...……34
4.2
Variation of sweep frequency with change in dithering range…………………..36
4.3
Spectrum of switch voltage for dithering range of 19-21 kHz with a sweep
frequency of 120 Hz……………………………………………………………...38
x
4.4
Variation of sweep frequency with change in dithering range…………………..42
4.5
Spectrum of switch voltage for dithering range of 16-20 kHz with a sweep
frequency of 960 Hz……………………………………………………………...44
4.6
Variation of sweep frequency with change in dithering range…………………..47
4.7
Spectrum of switch voltage for dithering range of 19-21 kHz with a sweep
frequency of 240 Hz……………………………………………………………...49
4.8
Variation of sweep frequency with change in dithering range…………………..51
5.1
Block diagram of schematics…………………………………………………….55
5.2
Inverter module PS22A76………………………………………………………..55
5.3
Voltage sensor circuit……………………………………………………………57
5.4
PWM generation for the inverter switches using the three PWM generator
modules in the DSP………………………………………………………………59
5.5
Software flow diagram…………………………………………………………...60
5.6
Experimental setup……………………………………………………………….62
5.7
Spectrum of switch voltage for dithering range of 16-24 kHz with a sweep
frequency of 960 Hz……………………………………………………………...65
5.8
Variation of sweep frequency with change in dithering range…………………..66
5.9
Three phase PWM output waveforms with 6 kHz noise filter………………...…67
5.10
Three phase output voltage waveforms with 6 kHz noise filter...……………….68
5.11
Spectrum of switch voltage for dithering range of 16-20 kHz with a sweep
frequency of 960 Hz……………………………………………………………...70
5.12
Variation of sweep frequency with change in dithering range…………………..72
5.13
Phase to phase inverter output voltage operating at 50 V DC bus voltage without
scope filtering…………………………………………………………………….73
5.14
Phase to phase inverter output voltage operating at 100 V DC bus voltage with
6 kHz scope filtering……………………………………………………………..74
xi
LIST OF TABLES
Table
Page
3.1
Switching states of two level inverter……………………………………………25
4.1
Peak values of FFT spectrum in two level inverter with a dithering range of 19-21
kHz using SVPWM dithering…………………………………………………...33
4.2
Peak values of FFT spectrum in two level inverter with a dithering range of 16-20
kHz using SVPWM dithering……………………………………………...........33
4.3
Peak values of FFT spectrum in two level inverter with a dithering range of 16-24
kHz using SVPWM dithering…………………………………………………...35
4.4
Change of sweeping frequency with dithering range in two level inverter using
SVPWM dithering…………………………….…………………………………35
4.5
Peak values of FFT spectrum in two level inverter with a dithering range of 19-21
kHz using sine PWM dithering……………………………………………….....37
4.6
Peak values of FFT spectrum in two level inverter with a dithering range of 18-22
kHz using sine PWM dithering……………………………………….................39
4.7
Peak values of FFT spectrum in two level inverter with a dithering range of 16-24
kHz using sine PWM dithering……………………………………………….....39
4.8
Peak values of FFT spectrum in two level inverter with a dithering range of 15-25
kHz using sine PWM dithering……………………………………………….....40
4.9
Change of sweeping frequency with dithering range in two level inverter using
sine PWM dithering……………………………………………………………...41
4.10
Peak values of FFT spectrum in three level inverter with a dithering range of 1921 kHz using SVPWM dithering…………………………………………..........43
4.11
Peak values of FFT spectrum in three level inverter with a dithering range of 1620 kHz using SVPWM ditherin………………………………………………....44
xii
4.12
Peak values of FFT spectrum in three level inverter with a dithering range of 1624 kHz using SVPWM dithering……………………………………………......45
4.13
Peak values of FFT spectrum in three level inverter with a dithering range of 1626 kHz using SVPWM dithering………………………………………..............45
4.14
Change of sweeping frequency with dithering range in three level inverter using
SVPWM dithering…………………………….…………………………………46
4.15
Peak values of FFT spectrum in three level inverter with a dithering range of 1921 kHz using sine PWM dithering………………………………………............48
4.16
Peak values of FFT spectrum in three level inverter with a dithering range of 1822 kHz using sine PWM dithering……………………………………………....49
4.17
Peak values of FFT spectrum in three level inverter with a dithering range of 1624 kHz using sine PWM dithering……………………………………………....50
4.18
Change of sweeping frequency with dithering range in three level inverter using
sine PWM dithering…………………………...…………………………………50
5.1
DSP specifications……………………………………………………………….58
5.2
Peak values of FFT spectrum in two level inverter with a dithering range of 19-21
kHz using SVPWM dithering…………………………………………………...63
5.3
Peak values of FFT spectrum in two level inverter with a dithering range of 16-20
kHz using SVPWM dithering…………………………………………………...64
5.4
Peak values of FFT spectrum in two level inverter with a dithering range of 16-24
kHz using SVPWM dithering…………………………………………………...64
5.5
Change of sweeping frequency with dithering range in two level inverter using
SVPWM dithering……………………………….………………………………66
5.6
Peak values of FFT spectrum in two level inverter with a dithering range of 19-21
kHz using sine PWM dithering………………………………………….............69
5.7
Peak values of FFT spectrum in two level inverter with a dithering range of 16-20
kHz using sine PWM dithering…………………………………………….........70
5.8
Peak values of FFT spectrum in two level inverter with a dithering range of 16-24
kHz using sine PWM dithering…………………………………………….........71
5.9
Change of sweeping frequency with dithering range in two level inverter using
sine PWM dithering……………………………..…………………………….…72
xiii
CHAPTER I
INTRODUCTION
1.1
Power Electronic Inverters
DC/AC inverters are used to invert a DC form of voltage or current into AC forms
with the desired magnitude and frequency. The output voltage could be fixed or variable
at a fixed or variable frequency. A variable output voltage can be obtained by varying
the input DC voltage and maintaining the inverter gain constant. On the other hand, if the
DC input voltage is fixed and it is not controllable, a variable output voltage can be
obtained by varying the gain of inverter, which is normally accomplished by pulse width
modulation (PWM) control within the inverter. Figure 1.1 shows the typical function of
an inverter.
Figure 1.1: General inverter operation.
The output voltage waveforms of an ideal inverter should be sinusoidal. However,
the waveforms of practical inverters are non sinusoidal and contain certain harmonics.
1
For low power applications a two level inverter can be used to obtain nearly
sinusoidal ac voltage; but for medium and high power applications, a two level inverter
uses a series and parallel connection of devices. It leads to voltage and current sharing the
problems of the switching devices and also stress on the device will be high.
In recent years high power and medium voltage drive applications have also been
installed. To overcome the limited semiconductor voltage and current ratings, some kind
of series and/or parallel connection are necessary. Due to their ability to synthesize
waveforms with a better harmonic spectrum and attain higher voltages multilevel
inverters are receiving increasing attention in the past few years. The multilevel inverter
was introduced as a way to increase the converter operating voltage above the voltage
limits of classical semiconductors [6].
1.2
Research Motivation
The power electronic inverter based drive systems should meet certain
electromagnetic interference (EMI) limits. The main source of EMI in ac drives is the
high frequency switching of the power devices. Passive filtering and EMI shielding
solutions add significant cost and weight to the equipment [2]. It has been shown that
dithering the switching frequency reduces the EMI noise [3], and also the requirements
for the EMI filter [3]. A similar approach to reduce these emissions is to randomize the
switching frequency, which has been mentioned in the literature [7]. Dithering the
switching frequency of the power devices of an inverter results in EMI noise
improvement of more than 10dB [2]. There are also several other methods that have been
previously presented to reduce EMI generation using some active control concepts. For
example, researchers proposed a two stage gate voltage turn on process to control the
2
device switching speed in order to reduce EMI generation. Although there is a reduction
in resulting EMI amplitude, switching losses increased [2]. Another research group
developed a gate drive that injects additional current only during the voltage transition,
increasing the voltage rate of change value
change
without affecting the rate of current
[8]. Another researcher developed a technique for reducing the EMI
generated in hard switched voltage source inverters while minimizing switching losses by
using a circuit that can control the
of power switches [7].
However all of these approaches are general and did not discuss any relationship
between the parameters involved in the dithering concept. The difference between past
investigations and our proposed work is the ability of the dithering technique to relate the
various parameters involved in the switching frequency dithering concept. We apply the
dithering technique to three phase two level voltage source inverter and cascaded Hbridge multilevel inverter with both sinusoidal pulse width modulation and space vector
modulation algorithms. In this research, we discuss the dithering technique and develop a
relationship between the parameters involved in the dithering concept. The main
parameters involved in the switching frequency dithering are the dithering frequency
range (
frequency (
to
), the sweeping frequency, (
) and the fundamental operating
). In this research, we looked at the voltage spectrum of the inverter
switches and compared the FFT of the switch voltages for different combinations of
dithering ranges and sweeping frequencies. Simulations and experiments have been
carried out for both voltage source inverters of two levels and three levels, for various
combinations of dithering frequency range (
3
) and sweep frequencies (
) and
the results have been analyzed for their EMI reduction capability.
1.3
Research Objectives
In this thesis, a dithering algorithm is proposed to reduce the EMI of power
electronic inverters. A relationship among the various parameters involved in the
dithering of switching frequency has been developed. The peak value of the FFT
spectrum of the switch voltage of the inverter is measured. The relationship has been
verified by conducting several simulations and experiments for different dithering ranges
and sweeping frequencies. The sweep frequency function has been derived through curve
fitting and is approximated to be a cubic equation. The PWM inverter system has been
controlled using space vector PWM and sinusoidal PWM.
1.4
Thesis Organization
A brief overview of the subsequent chapters is given in this section. In Chapter 2,
basic EMI issues in power electronic drives, sources of EMI, EMI classification and EMI
mitigation methods are discussed. In Chapter 3, the concept of dithering, proposed
dithering algorithm based on simulation results, and control strategies of two level and
multilevel inverter are discussed. Chapter 4 deals with the simulation results obtained for
various dithering ranges and sweeping frequencies of voltage source inverter and
cascaded H-bridge multilevel inverter. Chapter 5 deals with the experimental setup,
hardware and software implementations. Experimental results have been tabulated for
various dithering ranges and sweeping frequencies. Matlab plots showing the variation of
sweeping frequency with dithering range has been provided. Finally conclusions and
future work are presented in Chapter 6.
4
The MATLAB/SIMULINK software, schematics, PCB layouts of the prototype
and digital signal processor (DSP) programming code are provided in the Appendix.
5
CHAPTER II
ELECTROMAGNETIC INTERFERENCE
2.1
Introduction
Basics concept of electromagnetic interference (EMI), analytical method of EMI
identification, classification of EMI noise is explained in this chapter. Sources of EMI
and the issues in power electronic drives are discussed. EMI mitigation methods using
passive filters and with various PWM patterns are discussed.
2.2
Sources of EMI
Power electronic converters are widely used in many applications including
renewable energy generation, industrial equipment/motor drives, electric vehicle/train, air
craft, household appliances, electronic ballasts, computer power supplies, power supplies
for telecommunication equipment, etc. These power converters use the fast switching
power semiconductor switches, such as MOSFET (Metal oxide semiconductor field
effect transistor), IGBT (Insulated Gate Bipolar Transistor) as the preferred switching
devices as they have many properties, such as higher efficiency, smaller size, and lower
overall cost, low losses associated with switching device [24]. However, fast switching
speed of new inverter technologies has the potential to cause EMI and high
[24].
The main problem that limits the power electronics drive’s evolution is the
conducted EMI generated by the inverter fed drive systems with the pulse width
6
modulation. The pulse width modulated inverters applied in adjustable speed drives has
become very important due to its use in various applications. These inverters show great
phenomena in high frequency applications. There will arise various problems in the
power electronic inverter system, as there is an increase in the carrier frequency of the
pulse width modulation and the faster switching rates of the power electronic switches
[11]. Generation of high frequency currents flowing in all parts of drive systems will
increase with the increase in the switching frequency and faster switching rates of power
electronic devices.
2.3
Electromagnetic Interference Issues in Power Electronic Drives
High frequency power electronic inverters have been widely used in high power
energy conversion systems. This results in better performance in dynamic response and
reduction in size, weight and acoustic noise of the system [8]. On the other hand, high
frequency switching of the high voltages and currents introduces EMI issues into the
system. EMI becomes a major concern for inverter driven motor drive system,
particularly when this motor drives are used in electric vehicles. The conducted and
radiated EMI may cause malfunctioning in the electronic equipment of the vehicle [8].
The sources of EMI are generally identified as high switching
to most of the research works, the switching
higher switching
2.4
and
and
and
rates. According
are the main sources of EMI. The
, the higher EMI emission.
EMI Classification
EMI is categorized into many types for the purpose of analysis and
regulation. Mainly, EMI can be split into radiated EMI and conducted EMI [1]. Radiated
emissions represent electromagnetic energy, which is propagated through space.
7
Conducted emissions represent electromagnetic energy, which is propagated through a
conductor. Here the conductor can be a power line, ground connection or control cables.
Conducted emissions are further classified into common mode (CM) noise and
differential mode (DM) noise [1]. There is no clear distinction between the common
mode and differential mode according to present EMI standards. But the distinction is
useful in the analysis and development of EMI reduction techniques. Conducted CM EMI
is caused by high frequency currents flowing through the input power lines. In switching
power converters, common mode EMI is caused by high
switching transitions [1]. The
main path for conducted CM EMI currents is the parasitic capacitance that exists between
the power module and the grounded heat sink. The
at the midpoints of the three legs of
the inverter are normally identified as CM noise source. The
caused by the switch turn
on/turn off, coupled through the parasitic capacitance between the IGBT collector and the
module base plate that is normally grounded through the heat sink, generate CM noise
current. The CM noise current flows into the ground and through the stray capacitance
inside the motor to the motor frame and back to the source via the power mains. The CM
noise current also flows into the ground and through the stray capacitance inside the
power supply and back to the noise source [1]. High frequency currents around the path
of power flow causes conducted DM EMI. These DM currents are mainly caused by
high
switching transitions in power switches. Any high frequency current that is not
shunted by dc bus capacitor appears as differential mode EMI [8]. The
in the dc bus is
can also be identified as differential mode noise source. This change of current is also
caused by the switching operation of the inverter [8]. The DM noise current flows into
8
power supply and back to the inverter. The DM current also flows through the motor
phase windings, and through the stray capacitance inside the motor, and then back to the
power mains via the dc bus and the rectifier. The common mode and differential mode
current paths in a PWM drive are shown in Figure 2.1 [8]. The
at the midpoints of the
three legs of the inverter are normally identified as CM noise source. The
caused by
the switch turn on or turn off, coupled through the parasitic capacitance between the
IGBT collector and the module base plate that is normally grounded through the heat sink,
generate CM noise current. The CM noise current flows into the ground and through the
stray capacitance inside the motor to the motor frame and back to the source via the
power mains. The CM noise current also flows into the ground and through the stray
capacitance inside the power supply and back to the noise source. The
in the dc bus is
normally identified as DM noise source. This change of current is also caused by the
switching operation of the inverter. The DM noise current flows into power supply and
back to the inverter. The DM current also flows through the motor phase windings, and
through the stray capacitance inside the motor, and then back to the power mains via the
dc bus and the rectifier [8].
9
Figure 2.1: Common mode and differential mode current paths in a PWM drive [8]
In this research we will see the EMI as conducted CM noise, which is measured by
rating of the power switches. We looked at the voltage spectrum of the inverter
switches by applying switching frequency dithering algorithm and compared the FFT of
the switch voltages for different
2.5
,
and
.
Analytical EMI Identification Method
The high speed switching action in a power converter emits both CM and DM of
EMI noise. The purpose of analysis of EMI noise is to investigate the fundamental
mechanism of the conducted EMI noise generation from power device switching. The
mechanism of EMI noise has been analyzed in [24] through simplified time domain
models to predict the switching noise. The switching transient in a power converter has
traditionally been analyzed by modeling as a single slope
and
transients. Neither
the diode reverse recovery current’s effect nor the internal interconnect parasitic has been
addressed. In reality, the switching transient of an IGBT has multiple slopes and shows
complex switching behavior. The frequency domain model is also used to quickly predict
10
the EMI spectrum [24]. The IGBT turn-on switching introduces a major change in device
current
,
, which can be expressed as [24]:
(2.1)
where,
is the trans-conductance of the IGBT,
the IGBT threshold voltage. The
of the stray inductance
rise during time
. The change in
is the IGBT gate voltage, and
causes
is
to fall down because
can be given as [24]:
(2.2)
The change in device voltage,
during
can be written as
(2.3)
Where
is the time required by the collector current ( ) to change from peak value to
steady state value.
The
during the current rise has a direct impact on the reverse-recovery current (
the freewheeling diode. The relation between
and
) of
is given by [24]:
(2.4)
where,
is the minority carrier lifetime of diode. It has been revealed that large
reverse-recovery current increases the EMI level. A larger turn on
. High
and
leads to a higher
during switching of power devices is related to switching frequency
and conducted EMI level [24].
11
2.6
Mitigation of EMI Noise in Power Converters using Passive Filters
The switching mode power electronics systems generate significant conducted
electromagnetic interference (EMI) in a broad spectrum. This EMI noise is harmful to the
normal operation of other electronics systems. The EMI must be suppressed to an
acceptable level before it can propagate to other systems.
There are some active and passive EMI filters which suppresses the EMI noise.
Passive EMI filters are widely used in power electronics systems to suppress EMI noise.
Because of the switch mode operations of the power electronics circuits, the EMI is
usually very high. As a result, the size of an EMI filter is usually up to one-fourth of the
whole system [23]. In order to improve the power density, EMI filter size is of concern.
In order to reduce the EMI filter size, active injections is investigated to reduce CM noise
of the power electronics systems. There are two ways to reduce CM noise using active
filters which are CM noise voltage cancellation or current cancellation [23].
CM noise voltage cancellation is achieved by generating equal and opposite CM
voltage in series with the original CM noise voltage. The CM current cancellation can be
implemented by parallel current injections through forward or feedback methods. The net
effects are the cancellation of the CM noise. Feed forward current injection was utilized
since the current amplifier has unity gain whereas the feedback amplifier has a large loop
gain to guarantee sufficient CM current cancellation. This allowed for increased
bandwidth of cancellation. Active filtering is verified using a motor drive system using a
custom built hybrid EMI filter. The hybrid filter is composed of a passive and an active
EMI filter [23].
12
Soft switching is another way to reduce EMI noise. It can reduce noise emission
by reducing
and
during the circuit operation. However, the practical EMI reduction
is affected by many factors. For hard switching inverter, diode reverse recovery problems
at turn on and high turn off
are the major EMI noise source. For resonant snubber
inverter, a better implementation is more important for EMI reduction [8]. The softswitching technique provides the potential to reduce EMI emission, but the ringing
caused by diode reverse recovery in the resonant branch and the hard turn-on of auxiliary
switch decreases the benefits achieved from the soft-switching of main switches. Snubber
capacitor is used to limit the IGBT turn-off
smaller the turn-off
. The larger the snubber capacitor, the
[8]. The other way to reduce the EMI noise is to dither the
switching frequency. Dithering the switching frequency operates the power converter
over a varying band of frequencies. Hence EMI emissions spread over a wide range of
frequencies resulting in the reduction of peak value of EMI emissions [3].
2.7
Mitigation of EMI Noise in Power Converters with Various PWM Patterns
The conducted EMI is one of the parameters to compare the modulation strategies,
which represent EMI emission trends of PWM inverters. The modulation strategies
analyzed are sinusoidal PWM and space vector PWM.
Sinusoidal PWM is the sine wave modulated with the triangle wave. It is a
simplified technique for implementation. The function for the sine wave modulation is
described as follows:
(2.5)
where,
is the amplitude modulation index.
13
Space vector,
is a vector having a magnitude of 1.5Vm and rotates in space at
rad/sec
represented as
(2.6)
With special space vector techniques it is possible to reduce the switching frequency.
Space vector techniques also reduce the minimum required DC bus voltage level. Since
the switching frequency and the level of the DC bus voltage directly effects the EMI,
space vector PWM techniques provide better EMI performance.
2.8
Summary
EMI issues in power electronic drives have been discussed. Classification of
EMI has been presented. Characteristics of EMI noise with various PWM patterns have
been discussed. The
rating of the power switches has been considered as the measure
of EMI.
14
CHAPTER III
DITHERING ALGORITHM FOR MITIGATION OF EMI
3.1
Introduction
Dithering the switching frequency results in the power converter being operated
over a varying band of frequencies. As a result, the EMI emissions spread over a range of
frequencies instead of a narrow band resulting in the reduction of peak value of EMI
emissions.
This chapter covers the basic concept of dithering, effect of switching frequency
dithering in power electronic converters. The proposed dithering algorithm has been
discussed. Concepts of two level inverters and multilevel inverters and their control
strategies such as space vector PWM and sinusoidal PWM have been discussed.
3.2
Effect of Switching Frequency Dithering on EMI
It has been a challenge to design a power converter that meets electromagnetic
compatibility (EMC) requirements. Normally a power converter’s high frequency
switching can produce both conducted and radiated EMI at levels that exceed acceptable
limits. Designers will minimize the effects of EMI during power converter circuit design
and board layout by applying best engineering practices [3]. A good layout, design and
filtering practices can reduce the power converter’s EMI to acceptable levels and permit
the power converter to final product to achieve EMC approvals. Since not every power
converter is designed under ideal conditions, the emissions of the power converter are not
15
measured until late of the development process [3]. At that time there is a limited space to
add extra filtering components and there will be no time to redesign. Then comes the
situation to pass EMC requirements late in the design cycle where it becomes expensive
and time-consuming. Hence dithering concept arises. The way to reduce a converter’s
peak emissions and possibly pass the EMC requirements is to dither the converter’s
switching frequency. Hence we can say that frequency dithering is a smart way to
maintain schedule by minimizing design changes [3].
The necessity of dithering can also be explained as follows: It is a challenge to
control EMI emissions produced during normal operation of the power converters. If
these EMI emissions are large enough, they conduct through power lines and flow
through other components within the system affecting the overall system performance.
The emission peaks typically occur at the fundamental switching frequency and
magnitude reduces as the frequency increases. Hence dithering the power converter’s
operating frequency can reduce the peak emissions by spreading EMI over a band of
frequencies.
Generally in a fixed frequency power converter narrow band emissions occur at
the fundamental of switching frequency with successive harmonics having less and less
energy. Dithering the switching frequency results in the power converter being operated
not as a single fixed frequency but over a varying band of frequencies. As a result the
EMI emissions spread over a range of frequencies instead of a narrow band resulting in
the reduction of peak value of EMI emissions.
Dithering the switching frequency will also reduce the peak value at the harmonic
frequencies. The frequencies, which are multiples of switching frequency, are harmonic
16
frequencies. The extent to which emissions are reduced by dithering depends on the
choice of dithering parameters such as rate of dithering, sweeping frequency. By proper
selection of these parameters it is possible to lower the EMI emissions by approximately
10dB [2].
3.3
Dithering Strategy
A Single phase PWM voltage waveform for a sinusoidal AC drive is shown in
Figure 3.1 [2].
Time (Sec)
Figure 3.1: Representation of switch voltage.
The voltage waveform equation can be expressed in Eqn 3.1 [2]:
(3.1)
Magnitude
The spectrum of the above equation can be seen in Figure 3.2 [2].
Radians
Figure 3.2: Frequency Spectrum of Switch Voltage.
17
From Figure 3.2 it can be seen that the PWM harmonics are concentrated at
specific frequencies, hence appears as narrowband noise. On the other hand, dithering the
switching frequency results in a lower signal to noise ratio with a spectrum that is
continuous and lower in peak amplitude representing a broadband noise.
There are various parameters involved in the PWM switching frequency dithering
such as switching frequency range, sweeping frequency. The switching frequency range
is bounded by two factors. The switching frequency cannot be very high because it will
increase the switching losses. It cannot be very low due to audible noise and stability
conditions reasons. Sweeping frequency is defined as the rate of updating the switching
frequency from one value to another. It is also called as hopping frequency.
The concept of dithering used for the reduction of EMI is shown in Figure 3.3.
The PWM frequency of the inverter switches is changed from
to
at a rate of
.
Time (Sec)
Figure 3.3: Proposed Dithering Method.
In order to relate the parameters in dithering method we have done extensive simulations,
which will be presented in the Chapter IV.
The various switching frequency dithering ranges implemented are 19-21 kHz,
18-22 kHz, 16-24 kHz, 15-25 kHz with different sweeping frequencies like 120 Hz, 240
18
Hz, 480 Hz, 960 Hz, 1200 Hz at a fundamental operating frequency of 60 Hz. The peak
values of the FFT spectrum of switch voltage of the inverter are obtained for various
combinations of dithering ranges with different sweeping frequencies at a fundamental
operating frequency of 60 Hz. Based on the simulation results, we come up with a
relationship between the parameters involved such as dithering frequency range and
sweeping frequency in the dithering concept by observing peak values of FFT spectrum
of switch voltage of the inverter. The relationship is approximated to a cubic equation
which explains the trend in the switching frequency range and sweep frequencies.
The relationship between the various parameters in switching frequency dithering
is verified for 3-phase voltage source inverter and cascaded H-bridge multilevel inverter
of 3 levels, both by simulations and experiments.
3.4
Implementation of Dithering Technique on Power Electronic Inverters
Dithering technique has been implemented on three phase two level inverter and
cascaded h-bridge three level inverter. The principle of operations of the inverters are
explained.
3.4.1
Two Level Inverter
Single phase VSI cover low range power applications and three phase VSI cover
the medium to high power applications. The main purpose of these topologies is to
provide a three phase voltage source, where the amplitude, phase, and frequency of the
voltages should always be controllable.
A three phase output can be obtained from a configuration of six transistors and
six diodes as shown in Figure 3.4. Two types of control signals can be applied to the
19
transistors: 180o conduction or 120o conduction. The 180o conduction has better
utilization of the switches and is preferred method.
Figure 3.4: Three-phase VSI topology.
Each transistor conducts for 1800. Three transistors remain on at any instant of
time. When transistor S1 is switched on, terminal a is connected to the positive terminal
of the dc input. When transistor S4 is switched on, terminal a is brought to the negative
terminal of the dc source. There are six modes of operation in a cycle and the duration of
each mode is 600. The transistors are numbered in the sequence of gating the transistors
(e.g., 123, 234, 345, 456, 561, and 612).
The load may be connected in Y or delta. The switches of any leg of the inverter
(S1 and S4, S3 and S6, or S5 and S2) cannot be switched on simultaneously, this would
result in a short circuit across the dc link voltage supply. Similarly, to avoid undefined
states and thus undefined ac output line voltages, the switches of any leg of the inverter
cannot be switched off simultaneously, this can result in voltages that depend on the
respective line current polarity.
20
3.4.2
Multilevel Inverter
For low power applications two level inverter can be used to obtain nearly
sinusoidal ac voltage, but for medium and high power applications, a two level inverter
uses series and parallel connection of devices. It leads to voltage and current sharing
problems of the switching devices and also stress on the device will be high. Thus, in
medium and high power applications, multilevel inverters are used.
A multilevel inverter uses cascaded H-bridges with separate DC sources. Each
DC source is associated with a single phase H-bridge converter. The AC terminal
voltages of different level converters are connected in series. Through different
combinations of the four switches, S1 to S4, each converter level can generate three
different voltage outputs, +Vdc, -Vdc and zero. By closing the appropriate switches, each
H-bridge inverter can produce three different voltages: +Vdc, 0, and -Vdc. When switches
S1 and S4 of one particular H-bridge inverter in Figure 3.5 are closed, the output voltage is
+Vdc. When switches S2 and S3 are closed, the output voltage is -Vdc. When either the
switches S1 and S2 or the switches S3 and S4 are closed, the output voltage is 0. The AC
outputs of different full-bridge converters in the same phase are connected in series such
that the synthesized voltage waveform is the sum of the individual converter outputs. In
this topology, the number of output-phase voltage levels is defined by m = 2N+1, where
N is the number of DC sources. Minimum harmonic distortion can be obtained by
controlling the conducting angles at different converter levels [19].
21
Figure 3.5: Cascaded H-bridges multilevel inverter using two dc sources.
Figure 3.6 shows the synthesized line voltage waveform of a three-level cascaded
inverter with two separate DC sources. The output voltage is synthesized by the sum of
each H-bridge inverter outputs, Van = Va1 + Va2. Each inverter level can generate three
different voltage outputs, +Vdc, 0, and –Vdc, by connecting the dc source to the ac output
side by different combinations of the four switches, S1, S2, S3, S4. Using the top level as
example, turning on S1 and S4 yields Va1 = +Vdc. Turning on S2 and S3 yields Va1 = –Vdc.
Turning off all the switches yields Va1 = 0. Similarly, the ac output voltage at each level
can be obtained in the same manner. Controlling the conducting angles at different
inverter levels can minimize the harmonic distortion of the output voltage [19]. For a
three phase system, the output voltage of the three cascaded converters can be connected
in either wye or delta configurations.
22
Figure 3.6: Voltage output of cascaded H-bridge multilevel inverter.
3.5
PWM Switching Strategies of Inverters
The relationship among the various dithering parameters is also verified by using
different control algorithms of the inverter like sinusoidal pulse width modulation and
space vector control algorithms on both two level and three level inverters.
3.5.1
Sinusoidal Pulse Width Modulation
Sinusoidal PWM is the sine wave modulated with the triangle wave. It is a
simplified technique for implementation. The function for the sine-wave modulation is
described as follows:
(3.2)
where, ma is the magnitude of modulation index.
23
Magnitude
Figure 3.7: principle of sine PWM [12].
3.5.2
Space Vector Pulse Width Modulation
The Space vector control algorithm for 2 level voltage source inverter and
cascaded H-bridge three level inverter is described.
Space vector modulation is an algorithm for the control of pulse width
modulation. It is used for the creation of AC waveforms used to drive 3-phase AC
systems. One active area of development is in the reduction of total harmonic
distortion (THD) created by the rapid switching inherent to these algorithms. The main
area of development in space vector modulation is the reduction of THD created by rapid
switching which is inherent to these algorithms; improve the quality of output voltage
spectra and the reduction of electromagnetic interference.
3.5.2.1
Space Vector Modulation of 3-Phase 2 Level Voltage Source Inverter
A three phase inverter shown in Figure 3.7 must be controlled so that at no time
the both switches in the same leg turned on otherwise the DC supply would be shorted.
This requirement may be met by the complementary operation of the switches within a
24
leg. i.e. if A+ is on then A− is off and vice versa. This leads to eight possible switching
vectors for the inverter, V0 -V7with six active switching vectors and two zero vectors.
Figure 3.8: Three-phase inverter.
Table 3.1: Switching states of two level inverter.
Vector
A+
B+
C+
A-
B-
C-
Type
V0=(000)
OFF
OFF
OFF
ON
ON
ON
Zero
V1=(100)
ON
OFF
OFF
OFF
ON
ON
Active
V2=(110)
ON
ON
OFF
OFF
OFF
ON
Active
V3=(010)
OFF
ON
OFF
ON
OFF
ON
Active
V4=(011)
OFF
ON
ON
ON
OFF
OFF
Active
V5=(001)
OFF
OFF
ON
ON
ON
OFF
Active
V6=(101)
ON
OFF
ON
OFF
ON
OFF
Active
V7=(111)
ON
ON
ON
OFF
OFF
OFF
Zero
To implement space vector modulation, a reference voltage vector is synthesized using a
combination of two adjacent active vectors and one or more zero vectors. In order to
obtain optimum harmonic performance and minimum switching frequency, the state
sequence is arranged such that the transition from one state to next state should be
performed by switching only one inverter leg.
25
Step 1: Coordinate Transformation
The first step is to convert the three phase coordinate system into the two phase
(,) coordinates using the following transformation matrix.
(3.3)
There are eight possible switching vectors for a three phase two level voltage source
inverter. The vectors V1 through V6 are six non-zero vectors called active vectors and
vectors 0 and 7 are called zero vectors. The region between the adjacent vectors
constitutes the sector.
Figure 3.9: Switching vectors of inverter using SVM.
Step 2: Determination of Sector
The reference vector obtained is
, the phase angle can be calculated as follows
(3.4)
If
, the reference voltage vector is in Sector 1.
26
If
, the reference voltage vector is in Sector 2.
If
, the reference voltage vector is in Sector 3.
If
, the reference voltage vector is in Sector 4.
If
, the reference voltage vector is in Sector 5.
If
, the reference voltage vector is in Sector 6.
Step 3: Determination of Duty Cycles
The reference voltage vector is assumed constant during one switching cycle. The
reference vector is synthesized by the application of two non-zero vectors and one zero
vector that bound the sector for the sampling period. The components of the reference
vector in Sector 1 are shown in Figure 3.10.
Figure 3.10: Determination of switching times.
27
The duty ratios for the vectors are computed as follows
(3.5)
(3.6)
(3.7)
where,
(3.8)
Step 4: Determination of Phase Duty Ratios
Depending upon the sector, duty cycles of switching vectors are selected such that the
transition from one state to the next state will involve only switching of the one inverter
leg.
3.5.2.2
Space Vector Control of Cascaded H-bridge Three Level Inverter
To implement space vector modulation, a voltage reference vector is to be
synthesized with the help of switching vectors and can be represented in vector form as
follows [15]:
(3.9)
By the definition of vector norm, the length of reference vector can be represented as
(3.10)
The steps involved in space vector control of three level inverter are explained as follows
28
Step 1: Coordinate Transformation
The reference vector
is to be transformed into a two dimensional coordinate system.
The transformation from three-dimensional system to two-dimensional system is given in
Eqn 3.11.
(3.11)
where,
(3.12)
The switching state vectors of a three level inverter is shown in Figure 3.11
Figure 3.11: Switching state vectors of a three level inverter in hexagonal coordinate
system.
29
Step 2: Detection of Nearest Three Vectors
The next step in the algorithm is find the nearest four vectors by computing the upper and
lower rounded values of the reference vector coordinates in (g,h) coordinate system. The
nearest four vectors can be known from Eqn 3.13 and Eqn 3.14.
(3.13)
(3.14)
Step 3: Computation of Duty Cycles
Once the nearest three vectors are identified, the duty cycles are obtained by the
following equations [15]
where
(3.15)
(3.16)
(3.17)
The overview of the space vector modulation algorithm for an n-level inverter is shown
in Figure 3.12 [15].
30
Figure 3.12: Flow chart of SVM three level inverter.
3.6
Summary
A proposed dithering algorithm and the effect of switching frequency dithering on
EMI has been discussed. The principles of operation of various power electronic inverters
have been discussed. Switching strategies of various PWM techniques such as sinusoidal
pulse width modulation and space vector pulse width modulation of both two level and
three level inverters has been discussed.
31
CHAPTER IV
DEVELOPMENT OF SWEEPING STRATEGY FOR PWM DITHERING
TECHNIQUE BASED ON SIMULATIONS
4.1
Introduction
This chapter discusses the simulations and the results obtained based on dithering
algorithm applied on three phase two level voltage source inverter and three phase
cascaded H-bridge three level inverter. The relationship between the dithering range and
sweeping frequency is discussed through the simulation results obtained.
4.2
Control of 3-Phase Two Level Inverter using SVPWM Dithering
The three phase two level voltage source inverter was simulated in
Matlab/Simulink at different dithering frequency ranges with different sweep frequencies
to find the best sweep frequency, which would give the minimum peak value of the FFT
spectrum of the switch voltage. Space vector PWM is used to simulate the two level
voltage source inverter. The different dithering frequency ranges for which the inverter is
simulated are 19-21 kHz, 16-20 kHz and 16-24 kHz. The different sweep frequencies
considered for each dithering range are 120 Hz, 240 Hz, 480 Hz and 960 Hz. The peak
values of the FFT spectrum for various sweep frequencies for different dithering ranges
are tabulated [3].
32
Peak values of FFT spectrum of switch voltage for a dithering range of 19-21 kHz with
various sweep frequencies is shown in Table 4.1.
Table 4.1: Peak values of FFT spectrum in two level inverter with a dithering range of
19-21 kHz using SVPWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
121.4 dB
240 Hz
122.9 dB
480 Hz
122.0 dB
960 Hz
121.6 dB
From the Table 4.1 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 120 Hz.
Peak values of FFT spectrum of switch voltage for a dithering range of 16-20 kHz with
various sweep frequencies is shown in Table 4.2.
Table 4.2: Peak values of FFT spectrum in two level inverter with a dithering range of
16-20 kHz using SVPWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
125.2 dB
240 Hz
115.0 dB
480 Hz
121.0 dB
960 Hz
117.3 dB
33
From the Table 4.2 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 240 Hz.
FFT spectrum of switch voltage with dithering of switching frequency in the range of 1620 kHz is shown in Figure 4.1.
Figure 4.1: Spectrum of switch voltage for the dithering range of 16-20 kHz with a sweep
frequency of 960 Hz.
Peak values of FFT spectrum of switch voltage for a dithering range of 16-24 kHz with
various sweep frequencies is shown in Table 4.3.
34
Table 4.3: Peak values of FFT spectrum in two level inverter with a dithering range of
16-24 kHz using SVPWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
126.8 dB
240 Hz
123.8 dB
480 Hz
116.6 dB
960 Hz
114.2 dB
From the Table 4.3 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 960 Hz.
As given in above Tables there is a best sweep frequency range that minimizes the peak
value of the FFT spectrum of the switch voltage. The optimum sweeping frequency for
different dithering range is summarized in Table 4.4.
Table 4.4: Change of sweeping frequency with dithering range in two level inverter using
SVPWM dithering.
Dithering Range Sweeping Frequency, fsweep Peak value of FFT
19-21 kHz
120 Hz
121.4 dB
16-20 kHz
240 Hz
115.0 dB
16-24 kHz
960 Hz
114.2 dB
35
From the above Table 4.4, it can be observed that as the dithering frequency range
increases, the sweep frequency that produces lower peak value of FFT spectrum of switch
voltage also need to be increased. Figure 4.2 shows how the sweep frequency changes as
the dithering range increases for a fundamental operating frequency of 60 Hz.
Dithering of SVPWM 2 Level Inverter
1000
900
y = 20*x
2
data 1
quadratic
- 60*x + 1.6e+002
800
f_sweep
(Hz)
fsweep(Hz)
700
600
500
400
300
200
100
2
3
4
5
frange(KHz)
6
7
8
f_range (kHz)
Figure 4.2: The variation of sweeping frequency with change in dithering range.
The sweep frequency function is derived through curve fitting and is approximated to be
a quadratic equation as follows:
(4.1)
The function obtained through curve fitting is predicting the required
very well.
36
for a given
4.3
Control of 3-Phase Two Level Inverter using Sine PWM Dithering
The three phase two level voltage source inverter was simulated in
Matlab/Simulink at different dithering frequency ranges with different sweep frequencies
to find the best sweep frequency, which would give the minimum peak value of the FFT
spectrum of the switch voltage. Here sinusoidal PWM is used to simulate the two level
voltage source inverter. The different dithering frequency ranges for which the inverter is
simulated are 19-21 kHz, 18-22 kHz, 16-24 kHz and 15-25 kHz. The different sweep
frequencies considered for each dithering range are 120 Hz, 240 Hz, 480 Hz and 960 Hz.
The peak values of the FFT spectrum for various sweep frequencies for different
dithering ranges are tabulated below.
Peak values of FFT spectrum of switch voltage for a dithering range of 19-21 kHz with
various sweep frequencies is shown in Table 4.5.
Table 4.5: Peak values of FFT spectrum in two level inverter with a dithering range of
19-21 kHz using sine PWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
117.0 dB
240 Hz
125.2 dB
480 Hz
120.6 dB
960 Hz
118.5 dB
37
From the Table 4.5 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 120 Hz.
FFT spectrum of switch voltage with dithering of switching frequency in the range of 1921 kHz is shown in Figure 4.3.
Figure 4.3: Spectrum of switch voltage for the dithering range of 19-21 kHz with a sweep
frequency of 120 Hz.
Peak values of FFT spectrum of switch voltage for a dithering range of 18-22 kHz with
various sweep frequencies is shown in Table 4.6.
38
Table 4.6: Peak values of FFT spectrum in two level inverter with a dithering range of
18-22 kHz using sine PWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
117.9 dB
240 Hz
125.2 dB
480 Hz
115.2 dB
960 Hz
117.0 dB
From the Table 4.6 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 480 Hz.
Peak values of FFT spectrum of switch voltage for a dithering range of 16-24 kHz with
various sweep frequencies is shown in Table 4.7.
Table 4.7: Peak values of FFT spectrum in two level inverter with a dithering range of
16-24 kHz using sine PWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
120.3 dB
240 Hz
119.6 dB
480 Hz
117.5 dB
960 Hz
115.0 dB
39
From the Table 4.7 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 960 Hz.
Peak values of FFT spectrum of switch voltage for a dithering range of 15-25 kHz with
various sweep frequencies is shown in Table 4.8.
Table 4.8: Peak values of FFT spectrum in two level inverter with a dithering range of
15-25 kHz using sine PWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
240 Hz
116.6 dB
480 Hz
115.2 dB
960 Hz
114.6 dB
1020 Hz
113.8 dB
From the Table 4.8 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 1020 Hz. As given in the above Tables there
is a best sweep frequency range that minimizes the peak value of the FFT spectrum of the
switch voltage. The optimum sweeping frequency for different dithering range is
summarized in Table 4.9.
40
Table 4.9: Change of sweeping frequency with dithering range in two level
inverter using sine PWM dithering.
Dithering Range Sweeping Frequency, fsweep Peak value of FFT
19-21 kHz
120 Hz
117.9 dB
18-22 kHz
240 Hz
115.2 dB
16-24 kHz
960 Hz
115.0 dB
15-25 kHz
1020 Hz
113.8 dB
From the Table 4.9, it can be observed that as the dithering frequency range increases, the
sweep frequency that produces lower peak value of FFT spectrum of switch voltage also
need to be increased. Figure 4.4 shows how the sweep frequency changes as the dithering
range increases for a fundamental operating frequency of 60 Hz.
41
Dithering of Sine PWM 2 Level Inverter
1100
1000
3
data 1
cubic
2
y = - 5.6*x + 99*x - 3.8e+002*x + 5.2e+002
900
f_sweep
(Hz)
fsweep(Hz)
800
700
600
500
400
300
200
100
2
3
4
5
6
f_range (kHz)
frange(KHz)
7
8
9
10
Figure 4.4: The variation of sweeping frequency with change in dithering range.
The sweep frequency function is derived through curve fitting and is approximated to be
a cubic equation as follows:
(4.2)
The function obtained through curve fitting is predicting the required
for a given
very well.
4.4
Control of 3-Phase Cascaded H-bridge Three Level Inverter using SVPWM
Dithering
The three phase three level cascaded H-bridge multilevel inverter was simulated
in Matlab/Simulink at different dithering frequency ranges with different sweep
frequencies to find the best sweep frequency, which would give the minimum peak value
of the FFT spectrum of the switch voltage. Space vector pulse width modulation is used
to simulate the multilevel inverter of three levels. The different dithering frequency
42
ranges for which the inverter is simulated are 19-21 kHz, 16-20 kHz, 16-24 kHz and 1626 kHz. The different sweep frequencies considered for each dithering range are 120 Hz,
240 Hz, 480 Hz and 960 Hz. The peak values of the FFT spectrum for various sweep
frequencies for different dithering ranges are tabulated below.
Peak Values of FFT spectrum of switch voltage for a dithering range of 19-21 kHz with
various sweep frequencies is shown in Table 4.10.
Table 4.10: Peak values of FFT spectrum in three level inverter with a dithering range of
19-21 kHz using SVPWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
119.1 dB
240 Hz
121.4 dB
480 Hz
120.0 dB
960 Hz
119.6 dB
From the Table 4.10 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 120 Hz.
Peak values of FFT spectrum of switch voltage for a dithering range of 16-20 kHz with
various sweep frequencies is shown in Table 4.11.
43
Table 4.11: Peak values of FFT spectrum in three level inverter with a dithering range of
16-20 kHz using SVPWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
121.8 dB
240 Hz
124.6 dB
480 Hz
116.5 dB
960 Hz
123.2 dB
From the Table 4.11 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 480 Hz.
FFT spectrum of switch voltage with dithering of switching frequency in the range of 1620 kHz is shown in Figure 4.5.
Figure 4.5: Spectrum of switch voltage for the dithering range of 16-20 kHz with a sweep
frequency of 960 Hz.
Peak values of FFT spectrum of switch voltage for a dithering range of 16-24 kHz with
various sweep frequencies is shown in Table 4.12.
44
Table 4.12: Peak values of FFT spectrum in three level inverter with a dithering range of
16-24 kHz using SVPWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
126.8 dB
240 Hz
123.8 dB
480 Hz
116.6 dB
960 Hz
114.2 dB
From the Table 4.12 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 960 Hz.
Peak values of FFT spectrum of switch voltage for a dithering range of 16-26 kHz with
various sweep frequencies is shown in Table 4.13.
Table 4.13: Peak values of FFT spectrum in three level inverter with a dithering range of
16-26 kHz using SVPWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
123.8 dB
480 Hz
120.4 dB
960 Hz
119.0 dB
1200 Hz
114.3 dB
45
From the Table 4.13 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 1200 Hz.
As given in above Tables there is a best sweep frequency range that minimizes the peak
value of the FFT spectrum of the switch voltage. The optimum sweeping frequency for
different dithering range is summarized in Table 4.14.
Table 4.14: Change of sweeping frequency with dithering range in three level inverter
using SVPWM dithering.
Dithering Range
Sweeping frequency, fsweep
Peak value of FFT
19-21 kHz
240 Hz
121.4 dB
18-22 kHz
480 Hz
115.0 dB
16-24 kHz
960 Hz
114.2 dB
16-26 kHz
1200 Hz
114.3 dB
14-26 kHz
1920 Hz
113.4 dB
12-28 kHz
3840 Hz
113.3 dB
From the Table 4.14, it can be observed that as the dithering frequency range increases,
the sweep frequency that produces lower peak value of FFT spectrum of switch voltage
also need to be increased.
46
Figure 4.6 shows how the sweep frequency changes as the dithering range increases for a
fundamental operating frequency of 60 Hz.
Dithering of SVPWM 3 Level Inverter
4000
3
3500
data 1
cubic
2
y = 5.9*x - 1.1e+002*x + 7e+002*x - 8.3e+002
3000
f_sweep
(Hz)
fsweep(Hz)
2500
2000
1500
1000
500
0
2
4
6
8
frange(KHz)
f_range (kHz)
10
12
14
Figure 4.6: The variation of sweeping frequency with change in dithering range.
The sweep frequency function is derived through curve fitting and is approximated to be
a cubic equation as follows:
(4.3)
The function obtained through curve fitting is predicting the required
for a given
very well.
4.5
Control of 3-Phase Cascaded H-bridge Three Level Inverter using Sine PWM
Dithering
The three phase three level cascaded H-bridge multilevel inverter was simulated
in Matlab/Simulink at different dithering frequency ranges with different sweep
47
frequencies to find the best sweep frequency, which would give the minimum peak value
of the FFT spectrum of the switch voltage. Here the sinusoidal pulse width modulation is
used to simulate the multilevel inverter of three levels. The different dithering frequency
ranges for which the inverter is simulated are 19-21 kHz, 18-22 kHz and 16-24 kHz. The
different sweep frequencies considered for each dithering range are 120 Hz, 240 Hz, 480
Hz and 960 Hz. The peak values of the FFT spectrum for various sweep frequencies for
different dithering ranges are tabulated.
Peak Values of FFT spectrum of switch voltage for a dithering range of 19-21 kHz with
various sweep frequencies is shown in Table 4.15.
Table 4.15: Peak values of FFT spectrum in three level inverter with a dithering range of
19-21 kHz using sine PWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
119.0 dB
240 Hz
122.8 dB
480 Hz
124.5 dB
960 Hz
123.7 dB
From the Table 4.15, we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 120 Hz.
FFT spectrum of switch voltage with dithering of switching frequency in the range of 1921 kHz is shown in Figure 4.7.
48
Figure 4.7: Spectrum of switch voltage for the dithering range of 19-21 kHz with a sweep
frequency of 240 Hz.
Peak values of FFT spectrum of switch voltage for a dithering range of 18-22 kHz with
various sweep frequencies is shown in Table 4.16.
Table 4.16: Peak values of FFT spectrum in three level inverter with a dithering range of
18-22 kHz using sine PWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
122.1 dB
240 Hz
125.5 dB
480 Hz
119.3 dB
960 Hz
120.0 dB
From the Table 4.16 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 480 Hz.
49
Peak values of FFT spectrum of switch voltage for a dithering range of 16-24 kHz with
various sweep frequencies is shown in Table 4.17.
Table 4.17: Peak values of FFT spectrum in three level inverter with a dithering range of
16-24 kHz using sine PWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
122.7 dB
240 Hz
118.1 dB
480 Hz
118.9 dB
960 Hz
116.8 dB
From the Table 4.17 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 960 Hz.
As given in above Tables there is a best sweep frequency range that minimizes the peak
value of the FFT spectrum of the switch voltage. The optimum sweeping frequency for
different dithering range is summarized in Table 4.18.
Table 4.18: Change of sweeping frequency with dithering range in three level inverter
using sine PWM dithering.
Dithering Range Sweeping Frequency, fsweep Peak value of FFT
19-21 kHz
120 Hz
119.0 dB
18-22 kHz
480 Hz
119.3 dB
16-24 kHz
960 Hz
116.8 dB
50
From the above Table 4.18, it can be observed that as the dithering frequency range
increases, the sweep frequency that produces lower peak value of FFT spectrum of switch
voltage also need to be increased. Figure 4.8 shows how the sweep frequency changes as
the dithering range increases for a fundamental operating frequency of 60 Hz.
Dithering of Sine PWM 3 Level Inverter
4000
3
3500
data 1
cubic
2
y = 1.2*x - 19*x + 2.5e+002*x - 3.2e+002
3000
f_sweep
(Hz)
fsweep(Hz)
2500
2000
1500
1000
500
0
2
4
6
8
10
frange(KHz)
f_range (kHz)
12
14
16
Figure 4.8: The variation of sweeping frequency with change in dithering range.
The sweep frequency function is derived through curve fitting and is approximated to be
a cubic equation as follows:
(4.4)
The function obtained through curve fitting is predicting the required
very well.
51
for a given
4.6
Comparison of PWM Techniques with respect to EMI
Simulations have been performed using sine PWM and space vector PWM for
both three phase voltage source inverter and cascaded H-bridge three level inverter with
various combinations of dithering ranges and sweeping frequencies. From the simulation
results it is observed that the peak value of the FFT spectrum of switch voltage is lower
with the space vector PWM compared to sine PWM. The DC bus utilization is lower with
sine PWM compared to space vector PWM. The number of IGBT’s switching with space
vector PWM is less compared to sine PWM. Hence, the switching losses in space vector
PWM are less compared to the one with sine PWM which reduces the EMI and the
switching losses considerably.
FFT analysis of the switch voltage has been done for PWM techniques. The
relationship between the control parameters involved in dithering such as dithering
frequency range and sweeping frequency is observed with both sine PWM and space
vector PWM. From the simulations it is observed that as the dithering frequency range
increases, the sweep frequency that produces lower peak value of FFT spectrum of switch
voltage also need to be increased. The sweep frequency function is derived through curve
fitting and is approximated to a cubic equation. The function obtained through curve
fitting predicts the required
4.7
for a given
very well.
Summary
The dithering algorithm has been implemented for both 2 and 3 level inverters
using space vector PWM and sine PWM. Results have been tabulated for various
combinations of dithering ranges and sweeping frequencies at a fundamental frequency
of 60 Hz. It has been observed that as the dithering range increases the sweeping
52
frequency at which the peak value of FFT spectrum of the switch voltage also increases.
Therefore the sweep frequency, which produces lower peak value of FFT spectrum of
switch voltage, needs to be increased as dithering range increases.
53
CHAPTER V
HARDWARE IMPLEMENTATION AND EXPERIMENTAL RESULTS
5.1
Introduction
The simulation results indicate a relationship can be deduced from the various
parameters of the proposed dithering algorithm. These results motivated us to design a
prototype to validate the control algorithm of dithering of switching frequency in
inverters. In this chapter software implementation, hardware design and the prototype
used to test the simulation results has been discussed. Experimental results have been
tabulated for various combinations of dithering ranges and sweeping frequencies for three
phase voltage source inverter.
5.2
Hardware Implementation
The power, sensing, protection and interface circuitries were designed for a three
phase voltage source inverter. The schematics of the detailed circuitry are drawn using
ORCAD Capture CIS. The schematic design was followed by the PCB layout design
using ORCAD PCB Layout Plus. PCB’s are populated to form the system. The
schematics of module interface circuit, fault output circuit, voltage sensor circuit, current
sensor circuit, power output circuit and the PCB layouts of the overall system are given in
Appendices C and D.
54
The block diagram of overall experimental system is shown in Figure 5.1 below.
Figure 5.1: Block diagram of experimental system.
5.2.1 Inverter Module Circuit
The inverter module used in the hardware implementation is PS22A76. It is a
1200V, 25-Ampere DIP Intelligent Power Module. DIPIPMs are intelligent power
modules that integrate power devices, drivers, and protection circuitry. Design time is
reduced by the use of application-specific HVICs and value-added features such as linear
temperature feedback.
Figure 5.2: Inverter module PS22A76.
55
5.2.2
DSP to Inverter Module Interface
The module interface circuit shown in Appendices C.2 and C.3 generates the
necessary PWM signals required for the inverter module. The capacitor C 105 is used to
eliminate the low frequency noise. The schmitt trigger buffer SN7404N is used as level
shifter. The 3.3 V level signal input is converted into 5 V level signal output using the
schmitt trigger buffer. The 5 V signal is fed to optocoupler 6N135. The optocoupler
provides isolation between the control unit and power unit. These isolated outputs are
filtered using a low pass filter and fed into buffer. The buffered outputs are the PWM
signals fed to the inverter module.
5.2.3
Fault Output Interface
The fault output interface circuit shown in Appendix C.6 sends the fault signals
out which are generated in inverter module. The capacitor C 59 is used to eliminate the
low frequency noise. The supply to SN7404N buffer is 5 V. The inputs to the buffer are
FO and FO_2, which comes from inverter module. The outputs of the buffer are fed into
the opto-isolator for isolation purpose. The isolated outputs are filtered using a low pass
filter. The filtered outputs are fed into HCT buffer. The HCT buffer is used to obstruct
the reverse flow of signals.
5.2.4
Voltage Sensor Circuitry
The voltage sensor circuit is shown in Appendix C.7. Voltage amplifier AD202 is
used to measure dc voltage of the system. Voltage divider circuit is used to decrease the
high voltage level to be able to measure it. C11, C12, C13 and R13 values are used as
recommended for amplifier, the output of voltage sensor can be +Ve or –Ve depending
on the input voltage. Figure 5.3 shows the voltage amplifier AD202 and interfacing
56
circuit.
Voltage (+Ve)
Voltage isolater/Sensor
ISO_Voltage_Sensor
Power
Voltage divider
R11
195k
R13
Output VISO1
Input+
2k
3
R12
5k
C11
C12
100pf
0.1u
Input-
Power common
Output HI
Output LO
Output VISO+
38
2
20
37
+15V
C13
0.1u
22
19
18
36
Input Feedback
Input common
DGND
AD202
Voltage (-Ve)
Figure 5.3: Voltage sensor circuit.
5.2.5 House Keeping Power Supplies
The schematic for power supplies circuitry is shown in Appendix B.4. PTK15Q24-D15 is an isolated DC-DC converter used to obtain the isolated DC output voltage.
L4941BV is a linear voltage regulator used to obtain the 5 V DC from a 15 V DC supply.
PTK10-Q24-D15 is used to obtain the -15 V DC output from +15 V DC supply.
LE33CZ-TR is a linear voltage regulator used to obtain 3 V DC output from a 5 V supply.
5.3
Embedded Control Program
The controller is based on one 16-bit Microchip DSP dsPIC33FJ64GS610. The
control program is developed in the C language and the DSP is programmed by an InCircuit Debugger (ICD) interface using Explorer-16 development board. The interfacing
between the DSP and the inverter was done by the Microchip PicTail Plus daughter board.
The basic specifications of the DSP dsPIC33FJ64GS610 are given in Table 5.1.
57
Table 5.1 DSP specifications.
Parameter Name
Value
Architecture
16-bit
CPU Speed (MIPS)
40
Memory Type
Flash
Program Memory (KB)
64
Temperature Range (0C)
-40 to 125
Operating Voltage Range
3 to 3.6 V
I/O Pins
85
Pin Count
100
Internal Oscillator
7.37 MHz
ADC Channel
24
16-Bit PWM Channel
18
Timers
4x16-bit 1x32-bit
In the DSP dsPIC33FJ64GS610, there are twelve PWM channels used in the
control algorithm. The DSP dsPIC33FJ64GS610 has nine high-speed PWM generators. It
offers individual time based duty cycle for each PWM output with a frequency resolution
of 1.04 ns. The primary control registers of the PWM module are PTCON, PTPER,
PDCx, PWMCONx, DTRx, ALTDTRx and IOCONx.
58
Figure 5.4: PWM generation for the inverter switches using three PWM generator
modules in the DSP.
59
The software flow diagram of overall embedded code is shown in Figure 5.5.
Figure 5.5: Software flow diagram
60
5.4
Test Setup
The prototype of the voltage source inverter is developed by using inverter
modules (PS22A76) on a four-layer printed circuit board. The control algorithm is
developed in a Microchip 16-bit DSP dsPIC33FJ64GS610 using the In Circuit Debugger
(ICD) and the Explorer-16 development board. The developed experimental system has
been tested extensively to evaluate the control algorithm. In these tests, high precision
measurement instruments were used for better data collection and evaluation. Voltage
and PWM waveforms were acquired using the Tektronix four channel digital
oscilloscopes (Tektronix MSO 2024), HV differential voltage probes (Tektronix P5200).
The inverter module was run at a dc bus voltage of 150 Volts. The dithering
space vector algorithm was implemented for various dc bus voltages and the same pattern
has been observed for different range of switching frequencies and sweep frequencies.
The results of the switch voltage of the inverter module are tabulated for a dc bus voltage
of 150 Volts.
61
Figure 5.6: Experimental Setup.
5.5
Experimental Results
The experimental results have been tabulated for various combinations of
dithering ranges and sweep frequencies using SVPWM dithering and sine PWM
dithering.
5.5.1
Control of 3-Phase Two Level Inverter using SVPWM Dithering
Experimental setup has been built for the three phase voltage source inverter and
the inverter is controlled using space vector modulation algorithm. The inverter was run
at different dithering frequency ranges with different sweep frequencies to find the best
62
sweep frequency, which would give the minimum peak value of the FFT spectrum of the
switch voltage. The different dithering frequency ranges for which the inverter is
simulated are 19-21 kHz, 16-20 kHz and 16-24 kHz. The different sweep frequencies
considered for each dithering range are 120 Hz, 240 Hz, 480 Hz and 960 Hz. The peak
values of the FFT spectrum for various sweep frequencies for different dithering ranges
are tabulated.
Peak values of FFT spectrum of switch voltage for a dithering range of 19-21 kHz with
various sweep frequencies is shown in Table 5.2.
Table 5.2: Peak values of FFT spectrum in two level inverter with a dithering range of
19-21 kHz using SVPWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
126.5 dB
240 Hz
128.7 dB
480 Hz
128.3 dB
960 Hz
129.9 dB
From the Table 5.2 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 120 Hz.
Peak values of FFT spectrum of switch voltage for a dithering range of 16-20 kHz with
various sweep frequencies is shown in Table 5.3.
63
Table 5.3: Peak values of FFT spectrum in two level inverter with a dithering range of
16-20 kHz using SVPWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
123.5 dB
240 Hz
117.5 dB
480 Hz
122.6 dB
960 Hz
126.1 dB
From the Table 5.3 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 240 Hz.
Peak values of FFT spectrum of switch voltage for a dithering range of 16-24 kHz with
various sweep frequencies is shown in Table 5.4.
Table 5.4: Peak values of FFT spectrum in two level inverter with a dithering range of
16-24 kHz using SVPWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
126.2 dB
240 Hz
121.8 dB
480 Hz
121.5 dB
960 Hz
121.1 dB
64
From the Table 5.4 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 960 Hz.
FFT spectrum of switch voltage with dithering of switching frequency in the range of 1624 kHz is shown in Figure 5.7.
Figure 5.7: Spectrum of switch voltage for the dithering range of 16-24 kHz with a sweep
frequency of 960 Hz.
As given in Tables 5.2 to 5.4, there is a best sweep frequency range that minimizes the
peak value of the FFT spectrum of the switch voltage. The optimum sweeping frequency
for different dithering range is summarized in Table 5.5.
65
Table 5.5: Change of sweeping frequency with dithering range in two level inverter using
SVPWM dithering.
Dithering Range Sweeping Frequency, fsweep Peak value of FFT
19-21 kHz
120 Hz
126.5 dB
16-20 kHz
240 Hz
117.5 dB
16-24 kHz
960 Hz
121.1 dB
From the above Table 5.5, it can be observed that as the dithering frequency range
increases, the sweep frequency that produces lower peak value of FFT spectrum of switch
voltage also need to be increased. Figure 5.8 shows how the sweep frequency changes as
the dithering range increases for a fundamental operating frequency of 60 Hz.
Dithering of SVPWM 2 Level Inverter
1000
900
data 1
quadratic
y = 20*x 2 - 60*x + 1.6e+002
800
f_sweep (Hz)
fsweep(Hz)
700
600
500
400
300
200
100
2
3
4
5
frange(KHz)
f_range (kHz)
6
7
8
Figure 5.8: The variation of sweeping frequency with change in dithering range.
66
The sweep frequency function is derived through curve fitting and is approximated to be
a quadratic equation as follows:
(5.1)
The function obtained through curve fitting is predicting the required
for a given
very well.
The experimental PWM waveforms for the 3-phase voltage source inverter using space
vector control technique and dithering algorithm are shown below. The waveforms are
captured at a DC bus voltage of 100 V.
Figure 5.9: Three phase PWM output waveforms with 6 kHz noise filter.
67
Figure 5.10: Three phase output voltage waveforms with 6 kHz noise filter.
5.5.2
Control of 3-Phase Two Level Inverter using Sine PWM Dithering
Experimental setup has been built for the three phase voltage source inverter and
the inverter is controlled using sinusoidal pulse width modulation. The inverter was run at
different dithering frequency ranges with different sweep frequencies to find the best
sweep frequency, which would give the minimum peak value of the FFT spectrum of the
switch voltage. The different dithering frequency ranges for which the inverter is
simulated are 19-21 kHz, 16-20 kHz and 16-24 kHz. The different sweep frequencies
considered for each dithering range are 120 Hz, 240 Hz, 480 Hz and 960 Hz. The peak
values of the FFT spectrum for various sweep frequencies for different dithering ranges
are tabulated.
Peak values of FFT spectrum of switch voltage for a dithering range of 19-21 kHz with
various sweep frequencies is shown in Table 5.6.
68
Table 5.6: Peak values of FFT spectrum in two level inverter with a dithering range of
19-21 kHz using sine PWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
138.0 dB
240 Hz
140.0 dB
480 Hz
142.4 dB
960 Hz
142.0 dB
From the Table 5.6 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 120 Hz.
Peak values of FFT spectrum of switch voltage for a dithering range of 16-20 kHz with
various sweep frequencies is shown in Table 5.7.
69
Table 5.7: Peak values of FFT spectrum in two level inverter with a dithering range of
16-20 kHz using sine PWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
137.6 dB
240 Hz
136.6 dB
480 Hz
135.3 dB
960 Hz
136.8 dB
From the Table 5.7 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 480 Hz.
FFT spectrum of switch voltage with dithering of switching frequency in the range of 1620 kHz is shown in Figure 5.11.
Figure 5.11: Spectrum of switch voltage for the dithering range of 16-20 kHz with a
sweep frequency of 960 Hz.
70
Peak values of FFT spectrum of switch voltage for a dithering range of 16-24 kHz with
various sweep frequencies is shown in Table 5.8.
Table 5.8: Peak values of FFT spectrum in two level inverter with a dithering range of
16-24 kHz using sine PWM dithering.
Sweeping Frequency (fsweep) Peak Value of FFT
120 Hz
136.2 dB
240 Hz
141.8 dB
480 Hz
142.5 dB
960 Hz
135.1 dB
From the Table 5.8 we can see that the minimum peak value of FFT spectrum of switch
voltage is obtained for a sweep frequency of 960 Hz.
As given in Tables 5.6 to 5.8 there is a best sweep frequency range that minimizes the
peak value of the FFT spectrum of the switch voltage. The optimum sweeping frequency
for different dithering range is summarized in Table 5.9.
71
Table 5.9: Change of sweeping frequency with dithering range in two level inverter using
sine PWM dithering.
Dithering Range Sweeping Frequency, fsweep Peak value of FFT
19-21 kHz
120 Hz
138.0 dB
16-20 kHz
480 Hz
135.3 dB
16-24 kHz
960 Hz
135.1 dB
From the above Table 5.9, it can be observed that as the dithering frequency range
increases, the sweep frequency that produces lower peak value of FFT spectrum of switch
voltage also need to be increased. Figure 5.12 shows how the sweep frequency changes
as the dithering range increases for a fundamental operating frequency of 60 Hz.
Dithering of Sine PWM 2 Level Inverter
1000
900
y = - 10*x
2
data 1
quadratic
+ 2.4e+002*x - 3.2e+002
800
f_sweep (Hz)
fsweep(Hz)
700
600
500
400
300
200
100
2
3
4
5
f_range (kHz)
frange(KHz)
6
7
8
Figure 5.12: The variation of sweeping frequency with change in dithering range.
72
The sweep frequency function is derived through curve fitting and is approximated to be
a quadratic equation as follows:
(5.2)
The function obtained through curve fitting is predicting the required
for a given
very well.
The experimental PWM waveforms for the 3-phase voltage source inverter using sine
PWM technique and dithering algorithm are shown in Figure 5.13. The waveforms are
captured at a DC bus voltage of 100 V.
Figure 5.13: Phase to phase inverter output voltage operating at 50 V DC bus voltage
without scope filtering.
73
The output voltage waveform of a three phase voltage source inverter is shown in Figure
5.14.
Figure 5.14: Phase to phase inverter output voltage operating at 100 V DC bus voltage
with 6 kHz scope filtering.
5.6
Summary
The experimental results of three phase two level voltage source inverter are
obtained. The dithering algorithm has been implemented for two level voltage source
inverter using sine PWM and space vector PWM techniques. FFT analysis of the switch
voltage has been done for both PWM techniques. Results have been tabulated for various
combinations of dithering ranges and sweeping frequencies at a fundamental frequency
of 60 Hz. It is observed that as the dithering frequency range increases, the sweep
frequency that produces lower peak value of FFT spectrum of switch voltage also need to
be increased. The sweep frequency function is derived through curve fitting for both
space vector and sine PWM techniques. As the number of IGBTs switching in the space
74
vector PWM is less compared with sine PWM, the switching losses in space vector PWM
are low. Hence the EMI is lower in space vector PWM compared to sine PWM.
In this chapter, the hardware design and the software implementations are
discussed in details. The experimental results obtained by using the implemented inverter
were presented. The experimental results obtained also follow a trend as observed in
simulation results.
75
CHAPTER VI
CONCLUSION AND FUTURE WORK
The three phase two level voltage source inverter and cascaded H-bridge three
level inverter has been simulated using the sine PWM and space vector PWM control
techniques by applying the dithering algorithm. FFT analysis of the switch voltage has
been done. A relationship between the control parameters such as dithering range and
sweeping frequency in dithering concept has been developed based on simulation results
obtained. An experimental setup has been built to test the validity of the relationship
obtained through simulations.
A three phase two level voltage source inverter prototype has been developed and
the experimental results are obtained. The dithering algorithm has been implemented
using both sine PWM and space vector PWM techniques. The number of IGBT’s
switching with space vector PWM is less than that compared to sine PWM. Hence, the
switching losses in space vector PWM are less compared to the one with sine PWM,
which reduces the EMI and the switching losses considerably.
FFT analysis of the switch voltage has been done. Results have been tabulated
for different combinations of dithering ranges and sweeping frequencies for a given
fundamental frequency. It is observed that as the dithering frequency range increases, the
sweep frequency that produces lower peak value of FFT spectrum of switch voltage also
needs to be increased.
76
A method to reduce the common mode EMI arising from the switching
in
PWM inverters is proposed. A dithering technique relating the individual control
parameters has been developed. The FFT spectrum of the switch voltage for various
combinations of dithering ranges and sweeping frequencies have been analyzed to come
up with an algorithm to find the dithering control parameters. A relationship between the
parameters of dithering range and sweeping frequency at which low
occurs is obtained
for a given fundamental operating frequency. The function obtained through analysis of
control parameters and curve fitting predicts the required
for a given
.
Future work includes more extensive study of the relationship developed among
the parameters involved in the dithering algorithm. A theoretical analysis supporting the
relationship should be studied.
77
REFERENCES
[1]
Joshua D. Kagerbauer, T. M. Jahns, “ Development of an Active dv/dt Control
Algorithm for Reducing Inverter Conducted EMI with Minimal Impact on
Switching Losses,” IEEE Transactions on Power Electronics, pp. 894–900, 2007.
[2]
Abbas A. Fardoun, Esam H. Ismail, “ Reduction of EMI in AC Drives Through
Dithering Within Limited Switching Frequency Range,” IEEE Transactions on
Power Electronics, vol. 24, no. 3, pp. 804–811, 2009.
[3]
Abbas A. Fardoun, Ali Assi, Esam H. Ismail, “Reduction of EMI Through
Switching Frequency Dithering,” Circuits and Systems, 2007. MWSCAS 2007 50th
Midwest Symposium, pp. 538-541, 2007.
[4]
C.M.Liaw, Y.M.Lin, C.H.Wu, K.I.Hwu, “Analysis, Design and Implementation
of a Random Frequency PWM Inverter,” IEEE Transactions on Power
Electronics, vol. 15, no. 5, pp. 843–854, Sep. 2000.
[5]
T. Habetler, D. Divan, “Acoustic noise reduction in sinusoidal PWM drives using
a randomly modulated carrier,” IEEE Transactions on Power Electronics, vol. 6,
no. 3, pp. 356–363, Jul. 1991.
[6]
S. Mariethoz, “Resolution and Efficiency Improvements of 3-Phase Cascaded
Multilevel Inverters,” Power Electronics Specialists Conference, vol. 6, no.3, pp.
4441-4446, 2004.
[7]
S. Bolognani, R. Conton, M. Zigliotto, “Experimental Analysis of the EMI
Reduction in PWM Inverters Using Random Space Vector Modulation,” IEEE
International Symposium on Industrial Electronics, vol.1, no.4, pp.482-487, 1996.
[8]
Yuqing Tang, “High Power Inverter EMI Characterization and Improvement
Using Auxiliary Resonant Snubber Inverter,” December 1998.
[9]
Xuejun Pel, Jian Xiong, Yong Kang, Jian Chen, “Conducted EMI Emissions in
PWM Inverter,” The 4th International Power Electronics and Motor Control
Conference, vol. 2, pp. 630-635, 2004.
[10]
K.Karanun, W. Khan-ngern, S. Nitta, “The Characteristics of Conducted EMI
Emission on PWM Inverters with Various PWM Patterns,” International
Symposium on Electromagnetic Compatibility, pp. 533-536, 2002.
[11]
Jaroslaw Luszcz, Krzysztof Iwan, “Conducted EMI Propagation In Inverter-fed
AC Motor,” Electrical Power Quality and Utilization, vol.2, no.1, 2006.
[12]
A. M. Trzynadlowski, W. Zhiqiang, J. M. Nagashima, C. Stancu, M. H.
Zelechowski, “Comparative investigation of PWM Techniques for a New Drive
78
for Electric Vehicles,” IEEE Transaction on Industrial Applications, vol. 39, no.
5, pp. 1396–1403, October 2003.
[13]
Haoran Zhang, Annette Von Jouanne, Shaoan Dai, Alan K. Wallace, “Multilevel
Inverter Modulation Schemes to Eliminate Common-Mode Voltages,” IEEE
Transactions on Industry Applications, vol.37, no.1, pp. 3-3, 2001.
[14]
Arnaud Videt, Philippe Baudesson, Jean-Jacques Franchand, Jacques Ecrabey,
“Motor Overvoltage Limitation by Means of a New EMI Reducing PWM strategy
for Three-level Inverters,” IEEE Transactions on Industry Applications, vol.45,
no.5, pp. 1678-1687, 2009.
[15]
Nikola Celanovic, Dushan Boroyevich, “A Fast Space-Vector Modulation
Algorithm for Multilevel Three phase Converters,” IEEE Transactions on
Industry Applications, vol. 37, no. 3, pp. 637–641, 2001.
[16]
Minsub Han, Su-Dong Lee, Chanook Hong, Chun-Suk Yang, Kyung-Seo Kim,
“Development of Water-Cooled Heat Sink for High Power IGBT Inverter,”
International Conference on Power Electronics, pp. 295-299, 2007.
[17]
Keliang Zhou, Danwei Wang, “Relationship between Space Vector Modulation
and Three Phase Carrier Based PWM,” IEEE Transactions on Industrial
Electronics, vol.49, no.1, pp. 186-196, 2002.
[18]
J. Chiasson, L. Tolbert, K. McKenzie, Zhong Du, “Eliminating Harmonics in a
Multilevel Converter Using Resultant Theory,” Power Electronics Specialists
Conference, vol.2, no.8, pp. 503-508, 2002.
[19]
Keith Corzine, Yakov Familiant, “A New Cascaded Multilevel H-Bridge Drive,”
IEEE Transactions on Power Electronics, vol.17, no.1, pp. 125-131, 2002.
[20]
Zhong Dul, Leon M. Tolbert, J.N. Chiasson, B. Ozpineci, “A Cascade Multilevel
Inverter Using a Single DC Source,” Annual IEEE Applied Power Electronics
Conference and Exposition, no.5, 2006.
[21]
N. A. Azli, Y. C. Choong, “Analysis on the Performance of a Three phase
Cascaded H-Bridge Multilevel Inverter,” IEEE International Power and Energy
Conference, no.1, pp. 405-410, 2006.
[22]
A. Tahri, A. Draou, “A Comparative Modelling Study of PWM Control
Techniques for Multilevel Cascaded Inverter,” Applied Power Electronics
Laboratory, 2001.
[23]
Shuo Wang, Fred C. Lee, “EMI Research Nuggets,” Center for Power Electronics
Systems, 2008.
[24]
K. M. Muttaqi, M. E. Haque, “Electromagnetic Interference Generated from Fast
Switching Power Electronic Devices,” International Journal of Innovations in
Energy Systems and Power, vol.3, no.1, 2008.
79
APPENDICES
80
APPENDIX A
SIMULINK DIAGRAMS
A.1
Block diagram of cascaded 3 level inverter with space vector PWM technique.
A.2
Block diagram representing the generation of phase duty ratios using space vector
algorithm
81
A.3
Block diagram representing the generation of gate pulses for a cascaded H-bridge
three level inverter.
A.4
Block diagram representing the dithering algorithm with a dithering range of 16-
20 kHz and a sweep frequency of 960 Hz.
82
A.5
Block diagram of 3 level cascaded h-bridge multilevel inverter
linevol
+ v
-
1
To Workspace
+
v
-
z
Unit Delay
g
1
A
phasevol
+
+ v
-
A
B
To Workspace 1
-
Universal Bridge
1
Ref
1
z
Unit Delay 1
g
2
B
+
+ v
-
A
B
1/3
Gain1
-
Universal Bridge 1
1
g
z
Unit Delay 2
3
C
+
+ v
-
A
B
-
Universal Bridge 2
A.6
Block diagram of 3-phase voltage source inverter using space vector PWM
technique.
83
A.7
Block diagram representing the voltage reference block.
A.8
Block diagram of 3-phase two level inverter with sine PWM technique.
84
APPENDIX B
MATLAB CODES
B.1
Matlab code for control of cascaded h-bridge multilevel inverter using space
vector PWM control technique.
%%conversion into g-h coordiantes
function sys = mdlOutputs(t,x,u)
Vb=u(2);
Va=u(1);
Vc=u(3);
V4=(Va-Vb);
V5=(Vb-Vc);
V6=(Vc-Va);
k=1;
Vrefg=(((2*k)/3)*V4)+(((-k)/3)*V5)+(((-k)/3)*V6);
Vrefh=(((-k)/3)*V4)+(((2*k)/3)*V5)+(((-k)/3)*V6);
sys(1) = Vrefg;
sys(2) = Vrefh;
% end mdlOutputs
%% Identifying nearest three vectors
function sys = mdlOutputs(t,x,u)
g=u(1);
h=u(2);
if g>0
gu=floor(g)+1;
gl=floor(g);
else
gu=floor(g)+1;
gl=floor(g)-1+1;
end
if h>0
hu=floor(h)+1;
hl=floor(h);
else
hu=floor(h)+1;
hl=floor(h)-1+1;
end
sys(1) = gu;
85
sys(2) = gl;
sys(3) = hu;
sys(4) = hl;
sys(5) = u(1);
sys(6) = u(2);
% sys(7) = x1;
% end mdlOutputs
%% Determination of duty cycles
function sys = mdlOutputs(t,x,u)
gu=u(1);
gl=u(2);
hu=u(3);
hl=u(4);
Vrefg=u(5);
Vrefh=u(6);
if ((Vrefg+Vrefh)-(gu+hl))>0
dul=hu-Vrefh;
dlu=gu-Vrefg;
dz=1-dul-dlu;
else
dul=Vrefg-gl;
dlu=Vrefh-hl;
dz=1-dul-dlu;
end
sum=dul+dlu+dz;
sys(1) = dul;
sys(2) = dlu;
sys(3) = dz;
sys(4) = sum;
% sys(6) =region;
% end mdlOutputs
%%region determination
g=1.5;
h=0;
%sector1
if g>=0 && g<=1
if h>=0 && h<=1
if g+h>=0 && g+h<=1
reg1=1;
elseif g+h>1 && g+h<=2
reg1=3;
end
else
reg1=4;
end
elseif g>=1 && g<=2 && g+h>=1 && g+h<=2
reg1=2;
end
86
%sector2
if g>=-1 && g<=0
if h>=0 && h<=1
if g+h>=0 && g+h<=1
reg1=5;
end
elseif g+h>1 && g+h<2
reg1=8;
elseif g+h>0.5 && g+h<1
reg1=7;
end
elseif h>=1 && h<=2 && g+h>0 && g+h<1
reg1=6;
end
%sector3
if h>=0 && h<=1
if g>=-1 && g<=0
if g+h>=-1 && g+h<0
reg1=9;
end
elseif g<=-1 && g>=-2 && g+h<=0 && g+h>=-1
reg1=12;
elseif g<=-1 && g>=-2 && g+h>=-2 && g+h<=-1
reg1=10;
end
elseif h>=1 && h<=2 && g+h>=-1 && g+h<=0
reg1=11;
end
%sector4
if g>=-1 && g<=0
if h>=-1 && h<=0
if g+h>=-2 && g+h<=-1
reg1=15;
elseif g+h>-1 && g+h<=0
reg1=13;
end
elseif h>=-2 && h<=-1 && g+h>=-2 && g+h<=-1
reg1=16;
end
elseif h>=-1 && h<=0 && g>=-2 && g<=-1 && g+h>=-2 && g+h<=-1
reg1=14;
end
%sector5
if g>=0 && g<=1
if h>=-1 && h<=0
87
if g+h>=-1 && g+h<0
reg1=17;
end
elseif h<=-1 && h>=-2 && g+h<=-1 && g+h>=-2
reg1=18;
elseif h<=-1 && h>=-2 && g+h>=-1 && g+h<=0
reg1=19;
end
elseif g>=1 && g<=2 && g+h>=-1 && g+h<=0
reg1=20;
end
%sector6
if h>=-1 && h<0
if g>=0 && g<=1
if g+h>=0 && g+h<1
reg1=21;
end
elseif g<=2 && g>=1 && g+h<=1 && g+h>=0
reg1=23;
elseif g<=2 && g>=1 && g+h>=1 && g+h<=2
reg1=22;
end
elseif h>=-2 && h<=-1 && g>=1 && g<=2 && g+h>=0 && g+h<=1
reg1=24;
end
%%Determination of duty ratios
function sys = mdlOutputs(t,x,u)
dul=u(1);
dlu=u(2);
dz=u(3);
reg1=u(4);
% FIRST SET
if reg1==1
dA=1;
dB=dz+dlu;
dC=dz;
elseif reg1==2
dA=dz+2*dul+2*dlu;
dB=dlu;
dC=0;
elseif reg1==3
dA=dul+dlu+2*dz;
dB=dz+dlu;
dC=0;
elseif reg1==4
dA=dz+2*dul+2*dlu;
dB=dz+dul+2*dlu;
88
dC=0;
elseif reg1==5
dA=dz+dul;
dB=1;
dC=dul;
elseif reg1==6
dA=dz;
dB=dul+2*dlu+2*dz;
dC=0;
elseif reg1==7
dA=dul+dlu;
dB=2*dlu+dul+dz;
dC=0;
elseif reg1==8
dA=2*dz+dul+dlu;
dB=dul+2*dlu+2*dz;
dC=0;
elseif reg1==9
dA=dul;
dB=1;
dC=dul+dz;
elseif reg1==10
dA=0;
dB=dul+2*dlu+2*dz;
dC=dul+dlu+2*dz;
elseif reg1==11
dA=0;
dB=dul+2*dlu+2*dz;
dC=dz;
elseif reg1==12
dA=0;
dB=dz+dul+2*dlu;
dC=dlu+dul;
elseif reg1==13
dA=dz;
dB=dz+dlu;
dC=1;
elseif reg1==14
dA=0;
dB=dz+dul+2*dlu;
dC=dz+2*dul+2*dlu;
elseif reg1==15
dA=0;
dB=dz+dlu;
dC=2*dz+dlu+dul;
elseif reg1==16
dA=0;
dB=dlu;
dC=2*dlu+2*dul+dz;
elseif reg1==17
dA=dlu+dul;
89
dB=dlu;
dC=1;
elseif reg1==18
dA=dul;
dB=0;
dC=2*dul+2*dz+dlu;
elseif reg1==19
dA=dul+dz;
dB=0;
dC=dz+dlu+2*dul;
elseif reg1==20
dA=dlu+dz+2*dul;
dB=0;
dC=dlu+2*dz+2*dul;
elseif reg1==21
dA=1;
dB=dlu;
dC=dlu+dul;
elseif reg1==22
dA=dlu+2*dz+2*dul;
dB=0;
dC=dul;
elseif reg1==23
dA=dlu+dz+2*dul;
dB=0;
dC=dz+dul;
elseif reg1==24
dA=dlu+2*dz+2*dul;
dB=0;
dC=dlu+dz+2*dul;
end
diff1=dA-dB;
diff2=dB-dC;
diff3=dC-dA;
sys(1) = dA;
sys(2) = dB;
sys(3) = dC;
sys(4)= diff1;
sys(5)=diff2;
sys(6)=diff3;
B.2
Matlab code for control of 3-phase two level voltage source inverter using space
vector PWM control technique.
%%Determination of duty cycles
function sys = mdlOutputs(t,x,u)
x1=u(2);
Magnitude=u(1);
vdc=2;
pi=3.14;
90
if x1>0&&x1<pi/3
x2=1;
elseif x1>pi/3&&x1<2*pi/3
x2=2;
elseif x1>2*pi/3&&x1<pi
x2=3;
elseif x1>-pi&&x1<-2*pi/3
x2=4;
elseif x1>-2*pi/3&&x1<-pi/3
x2=5;
elseif x1>-pi/3&&x1<0
x2=6;
else
x2=3;
end
x3=x1-((x2-1)*(pi/3));
a=Magnitude/(sqrt(2/3)*vdc);
dx=a*sin(pi/3-x3)/sin(pi/3);
dy=a*sin(x3)/sin(pi/3);
dz=1-dx-dy;
sum=dx+dy+dz;
sys(1) = dx;
sys(2) = dy;
sys(3) = dz;
sys(4) = x2;
%% Determination of phase duty ratios
function sys = mdlOutputs(t,x,u)
dx=u(1);
dy=u(2);
dz=u(3);
sector=u(4);
if sector==1
dA=1;
dB=dz+dy;
dC=dz;
elseif sector==2
dA=dx;
dB=dx+dy;
dC=0;
elseif sector==3
dA=dz;
dB=1;
dC=dy+dz;
elseif sector==4
dA=0;
dB=dx;
dC=dx+dy;
elseif sector==5
dA=dz+dy;
91
dB=dz;
dC=1;
elseif sector==6
dA=dx+dy;
dB=0;
dC=dx;
end
sys(1) = dA;
sys(2) = dB;
sys(3) = dC;
92
APPENDIX C
SCHEMATICS
C.1
Schematics of Inverter module
93
C.2
Schematics of DSP to Module Interface-I
5
4
3
2
1
ISO_+5V
U22
1
8
NC C(Vcc)
2
7
A B(Vb)
3 C C(Vo) 6
4
5
NC E(GND)
R78
104
R77
4.1k
+ C101
0.1uF
C102
15pf
6N135
CONTROL_+5V
U23
D
C105
0.1u
R80
104
U25
1
2
3
4
5
6
7
Vcc
13
12
11
10
9
8
1A 14
1Y 6A
2A 6Y
2Y 5A
3A 5Y
3Y 4A
GND4Y
1
2
3
4
NC
A
C
NC
C(Vcc) 8
B(Vb) 7
C(Vo) 6
E(GND) 5
R79
4.1k
C103
0.1u
+ C104
0.1uF
1 OE1 Vcc 20
C106
15pf
2 A0 OE2 19
6N135
U26
SN7404N
R82
104
1 NC C(Vcc) 8
2 A B(Vb) 7
3
6
C C(Vo)
4
5
NC E(GND)
R81
4.1k
+ C107
0.1uF
C
B
6N135
O 30
O 29
UP
Y1 17
VP
16
WP
Y3 15
WN
14
VN
13
UN
A3
7
C108
15pf
8
R83
4.1k
Y2
A5
Y4
A6
Y5
9 A7
1 NC C(Vcc) 8
2 A B(Vb) 7
3 C C(Vo) 6
4 NC E(GND) 5
R84
104
U28
Y0 18
4 A2
6 A4
U27
Up_1
GND
Vp_1
GND
Wp_1
GND
Un_1
GND
Vn_1
GND
Wn_1
GND
Up_2
GND
Vp_2
GND
Wp_2
GND
Un_2
GND
Vn_2
GND
Wn_2
GND
FO
GND
FO_2
GND
GridInte_En
GND
3 A1
5
6N135
CONTROL_GND
D
U24
Y6 12
10 GND Y7 11
+ C109
0.1uF
74hct7541N,112
C110
15pf
U29
O 28
27
O
1
8
NC C(Vcc)
2 A B(Vb) 7
3 C C(Vo) 6
4
5
NC
E(GND)
R86
104
O 26
25
O
O 24
23
O
6N135
U30
O 22
21
O
O 18
O 17
6N135
O 16
O 15
+ C111
0.1uF
C
C112
15pf
ISO_GND
1 NC C(Vcc) 8
2 A B(Vb) 7
3 C C(Vo) 6
4 NC E(GND) 5
R88
104
O 20
O 19
R85
4.1k
R87
4.1k
+ C113
0.1uF
C114
15pf
O 14
O 13
O 12
O 11
10
O
9
O
U31
8
O
7
O
6
O
5
O
FO_CON
O 4
O 3
FO_2_CON
O 2
O 1
GridInte_Enable
1
2
3
4
R90
104
NC
A
C
NC
C(Vcc)
B(Vb)
C(Vo)
E(GND)
8
7
6
5
C118
DIGITAL CONNECTIONS
+ C115
0.1uF
C116
15pf
6N135
U32
30pinSocket
R89
4.1k
0.1u
U34
1
2
3
4
5
6
7
Vcc
13
12
11
10
9
8
1A 14
1Y 6A
2A 6Y
2Y 5A
3A 5Y
3Y 4A
GND4Y
SN7404N
R92
104
1
2
3
4
NC
A
C
NC
C(Vcc) 8
B(Vb) 7
C(Vo) 6
E(GND) 5
R91
4.1k
C117
U33
1 OE1 Vcc 20
C120
15pf
2 A0 OE2 19
6N135
U35
R94
104
1
2
3
4
NC
A
C
NC
8
C(Vcc)
7
B(Vb)
C(Vo) 6
E(GND) 5
3
R93
4.1k
UP_2
17
VP_2
Y2 16
WP_2
15
WN_2
7 A5
Y4 14
VN_2
8 A6
Y5 13
UN_2
9 A7
Y6 12
6
C122
15pf
R95
4.1k
A1
Y0
A2
Y1
5 A3
6N135
6N135
18
4
+ C121
0.1uF
U36
1 NC C(Vcc) 8
2 A B(Vb) 7
3 C C(Vo) 6
4 NC E(GND) 5
R96
104
B
0.1u
+ C119
0.1uF
A4
Y3
"_2" refer to the 2nd inverter side
10 GND Y7 11
+ C123
0.1uF
74hct7541N,112
C124
15pf
U37
1 NC C(Vcc) 8
2
7
A B(Vb)
3
6
C C(Vo)
4 NC E(GND) 5
R98
104
A
6N135
U38
1 NC C(Vcc) 8
2 A B(Vb) 7
3 C C(Vo) 6
4
5
R100 NC E(GND)
104
6N135
5
4
R97
4.1k
+ C125
0.1uF
A
C126
15pf
R99
4.1k
+ C127
0.1uF
Title
C128
15pf
Size
C
3
2
94
Date:
IsoPWMInputs
Document Number
<Doc>
Thursday, June 09, 2011
Rev
<RevCode>
1
Sheet
6
of
10
Schematics of DSP to Module Interface-II
5
4
3
C85
ISO_+15V
2
1
+
C.3
C1,56uf
C86
D7
R71
D1,1.8v,2.2A
R1,10
C2,0.33uf
VUFB
D8
VUFS
DZ1,24v,1w
D
D
+
C87
C1,56uf
C88
C2,0.33uf
D9
R72
D10
D1,1.8v,2.2A
R1,10
DZ1,24v,1w
VVFB
VVFS
+
C89
C1,56uf
C90
C2,0.33uf
D11
R73
D12
D1,1.8v,2.2A
R1,10
DZ1,24v,1w
VWFB
VWFS
C
C
VN1
+ C91
D13
C1,56uf
DZ1,24v,1w
C92
C2,0.33uf
ISO_GND
VNC
+
C93
C1,56uf
C94
C2,0.33uf
D14
R74
D15
D1,1.8v,2.2A
R1,10
DZ1,24v,1w
VUFB_2
VUFS_2
B
B
+
C95
C1,56uf
C96
C2,0.33uf
D16
R75
D17
D1,1.8v,2.2A
R1,10
DZ1,24v,1w
VVFB_2
VVFS_2
+
C97
C1,56uf
C98
C2,0.33uf
A
D18
R76
D19
D1,1.8v,2.2A
R1,10
DZ1,24v,1w
VWFB_2
A
VWFS_2
VN1_2
+ C99
D20
C1,56uf
DZ1,24v,1w
C100
Title
VNC_2
5
4
<Title>
C2,0.33uf
3
Size Document Number
Custom<Doc>
Date:
2
Thursday, June 09, 2011
Rev
<RevCode>
Sheet
95
5
1
of
10
C.4
Schematics of House Keeping Power Supplies
5
4
3
2
1
15W, 0.5A
U44
4 CNT
H8
C147
D
2 VIN- VOUT- 7
1 VIN+
COM 6
2pinH
VOUT+ 5
PTK15-Q24_D15
ISO_GND
+
2 DSP_GND
1 Sig
0.1u
Trim 8
C148
22uf
ISO_+15V
D
inverter module supply
CONTROL_GND
CONTROL_+15V
"CONTROL_" -- DSP side supply;
"ISO_" -- power circuit side
supply;
U45
CONTROL_+15V
H9
1 IN OUT 3
2 COM
2pinH
BA78M10CP
C
CONTROL_GND
U46
1 I O 3
2 GND
ISO_+15V
2 DSP_GND
1 Sig
C151
+ C149
0.33u
47uf
curr sensor
FO pull-up
vol sensor
vol sensor buffer
L4941BV
5V, 1A
C152
C150
+
PWM opto coupler
FO buffer
PWM buffer
C
22u
0.1u
ISO_GND
ISO_+5V
10V, 0.5A supply for DSP
CONTROL_GND
0.1u
CONTROL_+15V
CONTROL_-15V
U47
2 -Vin -Vout 5
COM 4
1 +Vin+Vout 3
+
C153
C154
47uf
curr sensor
vol sensor buffer
PTK10-Q24-D15
10W, +-15V
B
B
U48
CONTROL_+15V
1 I O 3
2 GND
L4941BV
C156
CONTROL_GND
CONTROL_+5V
5V, 1A
0.1u
C155
+
22u
U49
3 IN
CONTROL_+5V
FO opto coupler
PWM buffer
CONTROL_+3V
OUT 1
2 GND
A
C157
0.1u
curr sensor buffer
FO buffer
LE33CZ-TR
A
C158
+
3.3V, 0.1A
Title
10u
CONTROL_GND
<Title>
Size Document Number
Custom<Doc>
5
4
Date:
3
96
Thursday, June 09, 2011
2
Rev
<RevCode>
Sheet
9
1
of
10
C.5
Schematics of Three Phase Output Connectors
5
4
3
2
1
connect to a toggle for
bypass the resistors
D
D
U68
U67
1 o
P
o 1
hole
hole
H10
4 IN2
3 IN2
C129
C130
C132
C133
+
+
C3, 470uF C3, 470uF +
+
C5,0.22uf
C3, 470uF C3, 470uF
C131
C
U56
U
1 o
o 1
hole
U57
V
1 o
U59
W
1 o
hole
B
2pinT
C
1 U
2 U
hole
U58
o 1
hole
2 IN1
1 IN1
H4
U55
P_2
3 V
4 V
hole
U60
o 1
5 W
6 W
hole
NU
B
NU_2
3posT
NV
NV_2
NW
NW_2
A
A
ISO_GND
Title
Power Output 1
Size Document Number
Custom<Doc>
5
4
3
97
Date:
2
Thursday, June 09, 2011
Rev
<RevCod
Sheet
1
7
of
10
C.6
Schematics of Fault Output Interface
5
4
3
2
1
CONTROL_+5V
CONTROL_+3V
FO
D
D
U16
FO_CON
FO_2_CON
Enable
C55
DIR Vcc
A0 OE
A1 B0
A2 B1
A3 B2
A4 B3
A5 B4
A6 B5
A7 B6
GND B7
20
19 0.1u
18
17
16
15
14
13
12
11
U17
C56
15pf
C57
R49
+
1
2
3
4
5
6
7
8
9
10
4.1k
0.1uF
5
6
7
8
E(GND) NC
C(Vo) C
B(Vb) A
C(Vcc) NC
U18
4
3
2
1
6N135
R50
105 C58
0.1u
1
2
3
4
5
6
7
1A Vcc
1Y 6A
2A 6Y
2Y 5A
3A 5Y
3Y 4A
GND4Y
14
13
12
11
10
9
8
SN7404N
ISO_+5V
C59
0.1u
ISO_GND
CONTROL_GND
CD74HCT245E
C
C
C60
0.1u
GridInte_Enable
FO_2
U19
C61
15pf
C62
R52
+
B
4.1k
0.1uF
5
6
7
8
E(GND) NC
C(Vo) C
B(Vb) A
C(Vcc) NC
R51
4
3
2
1
B
105
6N135
A
A
Title
Size
A
5
4
Date:
3
98
<Title>
Document Number
<Doc>
Thursday, June 09, 2011
2
Rev
<RevCode>
Sheet
2
1
of
10
C.7
Schematics of Voltage Sensor Circuit
5
4
3
2
1
CONTROL_+15V
P
U50
R1BB4
430K
D
RBB1
17K
450V bus
voltage
C161
100pf
2k
R2BB4
3k
C159
0.1u
1 OUT V+ 8
R116
4 FB
RG4
1M
C162
0.1u
Vo 38
RF4
20K
3 IN-
D
2 IN- OUT 7
U51
C
R114
330
R115
1k
3 IN+ IN- 6
C160
4 V- IN+ 5
0.1u
busvol_sense
AD712
LO 37
D26
1 IN+
2 IN COM
15V DC 31
DZ1
CONTROL_+15V
6 +VISO OUT
ISO_GND
C
C163
0.1u
power return 32
CONTROL_GND
C164
0.1u
5 -VISO OUT
CONTROL_-15V
AD202
3V goes into AD202 and output 3V to AD712;
Voltage follower output 3V to DSP;
B
B
A
A
Title
Size
A
5
4
Date:
3
99
<Title>
Document Number
<Doc>
Thursday, June 09, 2011
2
Rev
<RevCode>
Sheet
10
1
of
10
APPENDIX D
PCB LAYOUTS
D.1
Top Layer
100
D.2
Inner 1 Layer
D.3
Inner 2 Layer
101
D.4
Bottom Layer
102