OpenStax-CNX module: m11358
1
Transistor Loads for Inverters
∗
Bill Wilson
This work is produced by OpenStax-CNX and licensed under the
Creative Commons Attribution License 1.0
†
Abstract
Discussing some other kinds of MOSFET's, and transistor loads for inverters.
There are other kinds of MOSFET's besides the one we have studied so far. Strictly speaking, what we
have seen up to now is called an n-channel enhancement mode MOSFET. It turns out that you can
build a MOSFET which looks just like a previous gure1 , except that by putting some additional impurities
under the gate region, we can arrange it so that there is a channel formed, even with Vg = 0. The transistor
now has a negativeVT . The process by which the additional impurities are added is called a VT adjust.
A MOSFET with a negative VT can be expected to have Id − Vds curves similar to those for a positive VT
device, except for one thing. For Vgs = 0, the device is already turned on, and so we get a usual MOSFETtype curve. Positive gate voltage turns it on even more, while negative Vgs tends to reduce the drain current.
It takes a negative gate voltage to turn the thing o. Figure 1 shows comparative characteristic curves for
an enhancement and depletion mode devices.
∗ Version
1.2: Jun 23, 2003 12:00 am +0000
† http://creativecommons.org/licenses/by/1.0
1 "MOS
Transistor", Figure 1 <http://cnx.org/content/m11353/latest/#g14>
http://cnx.org/content/m11358/1.2/
OpenStax-CNX module: m11358
Figure 1:
2
Enhancement and depletion characteristic curves
For an enhancement mode transistor, you have to get Vg > VT (-1 Volt in this example) to enhance the
conductivity or channel to make it conduct. For a depletion mode device, a gate voltage Vgs of 0, still nds
the device conducting. You have to put some negative voltage on the gate to deplete the channel, in order
to turn it o. We now have a depletion mode n-channel MOSFET.
How would we use a depletion mode device in an inverter gate? The answer is fairly straight-forward. In
the schematic in Figure 2, we indicate a depletion mode MOSFET by adding a second line, under the gate,
to suggest that a channel already exists in the device, even with no Vg . Note that the gate of the depletion
mode transistor (also sometimes called the pull up transistor) is connected to its source, so, in fact, Vgs
does equal 0 for this device. The input transistor (or the pull down transistor) is just an enhancement
mode MOSFET like we had before. It is not hard to choose appropriate W and L so that Idsat for the pull
up transistor is on the order of the 500 µA that we need to get our 1 ns rise time on the capacitive load.
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OpenStax-CNX module: m11358
Figure 2:
3
Depletion mode load
In order to get the transfer characteristic for this circuit, we rst note that
Vsdd = Vdd − Vsde
(1)
where Vsde is the source-drain voltage for the pull-down, or enhancement transistor, and Vsdd , is the sourcedrain voltage for the depletion-mode transistor. If we want to plot the load-line for the pull-down transistor
that is created by the pull-up or depletion mode transistor, we should take its Vgs = 0 characteristic curve,
shift it over by an amount Vdd , and then reverse its polarity. When we do this we get the following shown
in Figure 3. Noting the intersection points of the load line and the characteristic curves allows us the
opportunity for drawing the transfer characteristic (Figure 4). This is a better looking curve. It is symmetric
around the mid-voltage point, and gets closer to zero for its output "low" condition. The transition from
"high" to "low" is also somewhat more abrupt, which is advantageous. Can you gure out why?
Figure 3:
Characteristic curve and load line for a depletion MOS load
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OpenStax-CNX module: m11358
Figure 4:
4
Transfer characteristics for a depletion load inverter
Well, we solved one problem. At least we have a pull up structure that we can manufacture. It turns
out not to be too hard to build an enhancement MOSFET that has an equivalent resistance in the range we
need without taking up too much chip area. We have not solved the other problem however. We are still
looking at a huge current draw for large circuits. Since on average, half of the inverter gates will be "on"
in a logic circuit, we still have a large current sink to ground. This is something that would be completely
prohibitive in a modern-day VLSI integrated circuit.
Fortunately, we have not run out of options for MOS structures2 yet.
2 "CMOS
Logic" <http://cnx.org/content/m11359/latest/>
http://cnx.org/content/m11358/1.2/