Journal of Scientific & Industrial Research
Vol. 63, October 2004, pp 795-806
Emerging trends in ultra-miniaturized CMOS (Complementary metal-oxidesemiconductor) transistors, single-electron and molecular-scale devices:
A comparative analysis for high-performance computational nanoelectronics
V K Khanna
Solid State Devices Division, Central Electronics Engineering Research Institute, Pilani 333 031
The current status and trends of the three ultra-small scale integrated circuit technologies, namely nanoscale CMOS,
single- and molecular electronics are comprehensively reviewed. A comparative study is made, pointing out their relative
pros and cons for nanoelectronic computing. Crucial aspects of MOS downscaling include, from the physical viewpoint, the
infamous short-channel effect caused by drain induced barrier lowering (DIBL), the narrow width effect associated with
small channel width, the combined small-geometry effect, and hot-carrier degradation; together with the conflicting
requirements of shallow silicided junctions and low junction leakage; random doping fluctuations; ultrathin gate oxide
reliability; polysilicon depletion effect; atomic scale roughness at the Si/SiO2 interface; and high lithographic expenses, on
the technological side. For sustaining growth in device density, a possible route for the microelectronics industry is to shift
from the traditional field-effect transistor-based paradigm to one based on nanostructures. Single electronics has not been
able to bear the envisaged fruits. While prospects of solo single-electron logic are murky, the concept of a mixed singleelectron device/FET multi-valued logic and memory appears to be beneficial. But to achieve the ultimate performance, it
may be expedient to transform our philosophy fundamentally to start from the molecular level, instead of scaling down old
technologies to nanometer level. Molecular electronics appears to be the appropriate approach because the development cost
of scaled technologies, and cost-effectiveness of resulting devices is not encouraging. The review seeks to provoke keen
interest in these futuristic nanotechnologies.
Keywords: Nanotechnology, Computers, Single-electron transistor, Molecular electronics, Nanocells, Quantum dots
IPC Code: Int. Cl.7: H 01 L 29/00, H 01 L 21/336, H 01 L 27/00
1 Introduction
The computer industry has progressed by leaps and
bounds. This phenomenal success is ascribed to the
constant downsizing of contemporary CMOS devices
and circuitry resulting in lower cost, faster, and denser
computers with reduced power consumption and
enhanced functionality. Consumer’s demand for
portable battery-operated products has stimulated
considerable efforts for exploration of low-voltage
devices. MOSFETs (Metal-oxide-semiconductor
field-effect transistors) having decananometer channel
lengths are already mass fabricated while those less
than 10 nm have been demonstrated in research
environments. Below 10 nm, MOSFETs are close to
their basic limits of operation1, and at this scale, their
realization is confronted with gigantic physical and
financial constraints. Information technology needs
high-speed devices. Naturally, alternative approaches
like, single electronics and molecular electronics have
attracted the attention of researchers all over the
globe2. This paper discusses critically the obstacles
____________
Email: vkk@ceeri.ernet.in
faced by the nanoMOSFET technology, and sheds
light on the upcoming technologies to maintain the
constant pace of progress in this vital sector.
Investment in terms of development effort and cost
together with relative economic and technological
gains expected are the prime factors under
deliberation.
2 Prelude to Switching and Amplifying Devices
for Nanocomputers
To enable the reader to understand the subject and
appreciate the importance of the issues raised, we
begin with an introduction to the switching and
amplifying devices that constitute the hardware of
present-day electronic digital computers. All digital
computers contain a basic structural unit, ‘the
transistor’ which is a device capable of performing
two functions: switching and amplification. The state
of the transistor can be employed to adjust the voltage
on a wire as high or low, designated as binary zero and
one on the computer. Further, using a small input
signal the transistor can control an output signal that is
several-fold larger than this signal. The switching
796
J SCI IND RES VOL 63 OCTOBER 2004
Fig. 1—(a) Simplified structure of N-channel MOSFET. (b) Pchannel and N-channel MOSFETs in an N-well CMOS
technology
function allows the implementation of logical and
arithmetic functions in a computer while amplification
permits the transmission of signals within the computer
without attenuation.
The transistor most commonly used in digital
computers is the metal-oxide-semiconductor fieldeffect transistor (MOSFET)[Fig. 1(a)]. In this device,
current flows from the source terminal to the drain
terminal when the voltage applied to the gate terminal
is sufficient to invert the underlying silicon to form a
conducting channel from source to drain. A pair of
complementary devices, one P-channel MOSFET and
one
N-channel
MOSFET
constituting
the
complementary metal-oxide-semiconductor (CMOS)
structure, [Fig. 1(b)], is widely used in digital circuits.
To augment the capabilities of computers, their
fundamental structural unit, namely the MOSFET, has
been made progressively smaller in size resulting in
ultradense electronic circuits. The MOSFET has now
reached a stage where its further miniaturization will be
prevented by limitations of fabrication technology and
quantum mechanical laws governing the device
operation. As a solution to this problem, two categories
of alternative devices to the MOSFET have appeared
viz., single-electron transistors and molecular devices.
In the next section, the problems encountered in
shrinking MOSFETs are addressed. Then the novel
nanoelectronic switching and amplifying devices are
described. Although the operating principles of these
devices are radically different from those of the
MOSFET, these devices retain the terminology of
source, drain and gate in the same conceptual roles as
the MOSFETs. To acquaint the reader with the
terminology of these devices the single-electron
transistor3-10 contains a small island of semiconductor
or metal, ranging in size from 5-100 nm. This island is
embedded between two narrow walls of some other
material or an insulating oxide of the island material. It
is said that the island is enclosed between two potential
energy barriers.
Electrons confined to islands exhibit two essential
quantum mechanical effects: energy quantization and
tunneling. These effects control the electron transport
in a nanoelectronic device. Quantum mechanics allows
the energy of each electron to be one of a finite number
of one-electron energy levels. Moreover, when the
potential barriers are very thin, ~ 5-10 nm, there exists
a finite probability for ‘tunneling’ of electrons to move
to or from the island, provided there is a vacant state of
the same energy on the opposite side.
The other approach of molecular electronics11-19 is
based on devising molecular structures that can act as
switching elements, and assembling these molecules
into the accurate extended structures for computation.
The ability of a single molecule to conduct current
was not recognized easily because very constricted
wire structures offer high resistance even if they are
made from good electrical conductors. Chain
molecules composed of repeating units of aromatic
groups with acetylene linkage are known to conduct
electric current. They are called molecular wires and
can be made appreciably long. Incorporating quantum
wells into molecular structures for confinement of
mobile electrons, switching devices can be made. A
quantum well can be embedded in a molecular wire
by inserting pairs of barrier groups that break the
sequence of conjugated π-orbitals.
With this brief tutorial, we begin to investigate the
problems encountered in shrinking the MOSFET
devices.
KHANNA: COMPARATIVE ANALYSIS FOR HIGH-PERFORMANCE COMPUTATIONAL NANOELECTRONICS
3 Downscaling of MOS Devices, Significant Problems and Recourse to Other Approaches
Ever since J S Kilby invented and demonstrated the
integrated circuit in 1958, the manufacturing of
semiconductor ICs has continued to grow
exponentially. In 1965, Gordon Moore, the co-founder
of Intel, observed that the number of transistors per unit
area in an integrated circuit doubles every 18 months.
This observation referred to as the Moore’s law has
been corroborated during the past four decades as
integrated circuit complexity has advanced from smallscale integration (SSI: active device count 1-100 per
chip), through medium-scale integration (MSI: 100103), large-scale integration (LSI: 103-104), and very
large-scale integration (VLSI: 104-105) to ultra largescale integration (ULSI: 105-106). This have been
possible due to the continued reduction of minimum
device dimension. Breakthroughs in semiconductor
device fabrication during the past two decades have
pushed the minimum feature sizes down to the
nanometer region. Driven by the advances in extreme
ultraviolet lithography, electron-beam lithography and
X-ray lithography, epitaxial growth with atomic layer
accuracy by molecular beam epitaxy (MBE), and using
state-of-the-art process technology, miniaturization of
silicon MOSFET-based integrated circuits have been
intensively pursued for data processing and memory
functions. In the past few years, MOSFET dimensions
have reached the decananometer scale with dimensions
ranging between 10 to 100nm. Devices with physical
gate lengths 40-50 nm are already available. Within the
next 2 to 3 y, 35 nm gate length transistors will be
available for mass manufacturing. The prediction is
that the current trend will continue to progress at the
same pace with a new technology every 3 y and the
minimum feature size scaled down by a factor of
approximately 0.7. At 2009, a 70-nm linear dimension
CMOS technology will become available. By 2012 the
leading edge devices will employ gate lengths of 50 nm
with gate oxide thickness ≤ 1.5 nm. It is forecasted that
after 2016, the MOSFET will shrink down to
nanometer scale when its physical dimensions in a
mass production environment will reach 9 nm (ref. 20
and 21).
Main problems of MOS scaling along with
applicable remedies are enumerated below:
797
when the channel length becomes comparable to the
source-substrate or drain-substrate depletion depth,
and is caused by the overlapping of the depletion
region due to the gate field with the depletion regions
near the source and drain junctions, terminating the
built-in fields from source and drain22. This
overlapping decreases the total amount of depleted
charge available in the P-substrate to compensate the
field applied to the gate. The net result of this charge
sharing is that the depletion region below the gate is a
trapezoidal-shaped region instead of the rectangularshaped volume visualized for easy calculation.
Therefore the charge near the non-parallel sides of the
trapezium is subtracted from the bulk charge,
accounting for the lower threshold voltage.
The first step towards preventing short channel
effect is to ensure suitable gate control of the scaled
channel by shortening the lateral extension of the
junctions by reducing their depth. Thus the
source/drain regions comprise two parts, viz. a
shallow drain/source extension region and a deep
source/drain junction region. Raising the substrate
doping level to prevent the lateral extension of the
drain depletion region further alleviates the shortchannel effect. This produces a significant
deterioration of the performance of the transistor
because the carrier mobility in a heavily doped
substrate region is drastically reduced. Also the
leakage current increases. As a result, a higher offstate current is obtained, accompanied by a larger
subthreshold swing. A better remedy is to achieve the
same goal by a vertical doping redistribution with the
(a) Short -channel Effect
The primary effect is the reduction of threshold
voltage with the shortening of the channel, which can
be understood from Fig. 2. It becomes significant
Fig. 2—Charge sharing between gate and source, and gate and
drain in a MOSFET
798
J SCI IND RES VOL 63 OCTOBER 2004
help of a retrograde doping profile. The drain source
extension regions are built for decreasing the parasitic
resistances and pockets or halos are made by ion
implantation for increasing the doping concentration
below the channel region. Thus the low-concentration
region at the surface controls the threshold voltage
while the halos assure the short-channel immunity.
These pockets are made in such a way that they lie
close to the source/drain junctions for averting
punchthrough while the channel region with a lighter
doping for low threshold voltage remains unaffected.
The peak doping concentration in the halo implant
must be greater than that required with uniformly
doped subsurface layer. Although retrograde profiles
provide improved carrier mobility, unfortunately the
removal of the dopant from the interfacial channel
region decreases the threshold voltage, leading to
unacceptably high off current. Therefore the
advantages derived are subject to trade-off between
on-state and off-state currents. To illustrate, using a
smaller channel depletion width and a smaller sourcedrain depletion width reduces short-channel effect.
But a smaller channel depletion width increases the
subthreshold swing producing either a lower oncurrent or a higher off-current. Similarly the reduction
of source-drain depletion widths by raising the
substrate doing concentration alters the balance
between on-current and off-current.
(b) Narrow-width Effect
The increase in threshold voltage for narrow
channel width can be interpreted with reference to
Fig. 3. On approaching the edge of the device the
contour of the depletion region makes a transition
from the deep depletion region under the thin gate
oxide to the shallow depletion region under the
thicker field oxide22. Practically, this transition takes
place smoothly instead of the abrupt transition shown
by the dotted lines for simplifying the calculations.
Hence the triangular region of additional charge
between the dotted lines and the smooth bend must be
considered for threshold voltage calculation. For
wider MOSFETs the contribution of this charge in
comparison to the bulk charge is negligible but for
narrower widths, this charge becomes an appreciable
fraction of the total bulk charge, thereby raising the
threshold voltage of the device. In effect the threshold
voltage increases because of loss of some of the gateinduced space charge in the fringing field.
Additional increase in threshold voltage is
produced due to the encroachment of the heavily-
Fig. 3—Cross-section of the MOSFET width showing the actual
and ideal shapes of depletion regions
doped region under the field oxide called the channel
stop during high-temperature processing steps into the
channel region. This encroachment increases the
density of charge in the channel region near its sides.
To counteract the effect of this charge, a higher
voltage has to be applied for inversion, raising the
threshold voltage. A further increase in threshold
voltage occurs due to the bird’s beak effect. Here, a
tapering of the oxide, results in extra charge under the
oxide structure yielding a higher threshold voltage.
(c) Small-geometry Effect
When the channel length and width are
simultaneously reduced the resultant small-geometry
structure exhibits not only short-channel and narrowwidth effects but shows a combined effect due to the
coupling of the aforesaid two effects. This joint
manifestation of short-channel and narrow-width
effects is referred to as small-geometry effect.
(d) Shallow and Deep Source/Drain Contact Regions
For smaller depth junctions, the cross-sections of
source and drain junctions shrink, increasing the
parasitic series resistance of the MOSFET. Hence,
deeper junctions are necessary for minimizing the
source and drain resistances. But shallow junctions
are desirable for controlling the short-channel effects.
Therefore, a trade-off is needed between very shallow
junction depths and degradation of source/drain
resistances. Additionally the junction curvature
increases for shallow junctions, raising the electric
field in the drain region, thereby lowering the
breakdown voltage and increasing the susceptibility
of the device to hot-carrier effects. Furthermore, in
smaller depth junctions the likelihood of junction
damage increases, promoting the leakage current.
The source/drain contact structure comprises the
extension region of smaller depth and the contact
KHANNA: COMPARATIVE ANALYSIS FOR HIGH-PERFORMANCE COMPUTATIONAL NANOELECTRONICS
region of larger depth. The drain extension decreases
the peak electric field near the drain end of the
channel and hence the hot electron damage, besides
reducing the short-channel effect. The deeper
contacting junction is formed to accommodate the
thickness of the silicide layer and minimize the
junction leakage. The depth of the deeper junction
should not be larger than necessary because a larger
value requires a thicker spacer oxide and a longer tab
extension, resulting in higher resistance.
(e) Randomness of Dopant Placement in the Transistor
Channel
As there are only 100 dopant atoms in a 50 nm ×
50 nm FET the impact of the randomness of dopant
distribution on the transistor characteristics becomes
more severe in the small devices21. This is because the
doping is performed by ion implantation or thermal
diffusion. In both these processes the precise position
of the individual dopant atoms cannot be controlled.
There are statistical variations of both the number and
position of the dopant atoms. The total number and
spatial distribution of the dopant atoms in the channel
is scattered around an average value.
(f) Oxide Integrity
Since the invention of the MOSFET, thermally
grown silicon dioxide has been the unrivalled gate
insulator due to its remarkable properties unmatched
by other materials23. But silicon dioxide below 3 nm
is not expected to be robust enough for future
transistor gate dielectric applications. Direct tunneling
is very sensitive to oxide thickness, increasing
exponentially with thickness. The increased current
raises the standby power dissipation, thereby
adversely affecting the MOSFET performance. For
gate oxide thickness < 5 nm, an anomalous
degradation mode referred to as quasi-breakdown
(QB) has been reported, causing high gate leakage
current at low oxide field and large gate signal
fluctuations. For sub-100 nm gate length MOSFETs
the major challenge is suppression of gate leakage
current to a permissible level < 1 A/cm2 for desktop
and < 1 mA/cm2 for portable applications at a
required gate capacitance without serious impairment
of channel mobility.
Hence, thermal oxide is likely to be replaced by
higher dielectric constant materials such as, silicon
oxynitrides, TiO2, Ta2O5, Si3N4 and (Ba, Sr) TiO3.
Tantalum oxide with a dielectric constant of 25 can be
made 6.4-times thicker than silicon dioxide with a
799
dielectric constant of 3.9 for the same equivalent
oxide thickness. Hence, a 6.4 nm thick Ta2O5 layer
has the same effect as an SiO2 layer of thickness 1
nm. The former, due to the necessity of a thicker film,
provides easy control of thickness. But the quality of
Si-SiO2 interface must be ensured for achieving high
channel mobility. If such an interfacial SiO2 layer is
required with Ta2O5, the latter may pose
implementation difficulties because the required
thickness of the interfacial layer may itself be 1 nm.
(g) Polysilicon Depletion Effect
This phenomenon24 is caused by boron penetration
from P+ polysilicon gate through the thin gate oxide.
Nitrided oxide or oxynitride gate dielectrics are
utilized for preventing boron penetration but they
deteriorate the properties of the MOS interface so that
oxynitrides without nitrogen at the interface are
useful. A metal gate electrode such as, W/TiNx is a
promising technology for sub-50 nm MOSFETs
because of its smaller gate depletion, high thermal
stability, low resistivity, and CMOS-process
compatibility.
(h) Hot-carrier Degradation of Small MOSFETs
Carriers are said to be hot25 when they possess high
energies parametrized by an effective temperature
temperature Te greater than the lattice temperature T.
Obviously, these carriers cannot transfer their
energies to the lattice atoms fast enough to maintain
thermal balance and are therefore not in thermal
equilibrium with the lattice. They are generated in the
substrate or insulating regions of the device or the
inverted channel region when the MOSFET is
operating in the linear or saturation mode. Main
problems associated with hot carriers are shift of
threshold voltage with time, decrease in
transconductance, drain current degradation, sourcedrain breakdown induced by avalanche, minoritycarrier current in the substrate, majority-carrier
substrate current and parasitic gate currents. Special
care is taken during device design to nullify their
effects.
P-channel MOSFETs are less prone to hot-carrier
problems than N-channel MOSFETs due to the larger
ionization coefficient of holes and greater barrier
height at the insulator interface. In NMOSFETs, hot
carriers consist of substrate hot electrons (SHE),
channel hot electrons (CHE), avalanche hot electrons
(AHE) and avalanche hot holes (AHH).
SHE are produced when the electrons are
accelerated by the gate field towards the surface.
800
J SCI IND RES VOL 63 OCTOBER 2004
Energy of most of these electrons decreases through
inelastic scattering. When the electric field is > 20
kV/cm, the electron drift velocity saturates. Further
increase in gate field causes impact ionization and
under suitable biasing conditions, a fraction of
electrons acquire sufficient energy to surmount the SiSiO2 interfacial barrier. The number of electrons
injected into the gate oxide is determined by the
emission probability, which, in turn, is controlled by
the barrier height. The emission probability is greatly
increased by raising the substrate doping
concentration. Some of the electrons injected into the
gate oxide remain trapped inside it, and the number of
such trapped electrons increases with time. The
accumulated electrons change the flatband voltage
and hence the threshold voltage of the device.
CHE are created by attraction of electrons by the
positive drain voltage. Some of the electrons are
heated by the high electric field in the drain depletion
region. It is found that the drain voltage required for
maintenance of injection of hot electrons into the
insulator decreases with channel length reduction.
This happens because of the increased electric field in
the drain region and the effect of 2-D nature of the
fields in the smaller devices.
AHE and AHH are produced when the drain
voltage is high enough to initiate weak avalanching
by impact ionization in the pinch-off region of the
MOSFET. AHE and AHH are collectively known as
avalanche hot carriers (AHC).
Using graded drain profile reduces generation of
hot carriers but if the source junction is also graded
like the drain the injection efficiency of source into
the channel and hence the transconductance
decreases, whereby the channel resistance increases.
(i) N-Channel and P-Channel MOSFETs
In larger MOSFETs the 2-3-times higher mobility
of electrons as compared to holes results in three-toone current drive ratio as well as faster switching
speed for NMOS than PMOS devices. But similar
remarks do not apply to small NMOS and PMOS
devices because the current in these devices is
determined by saturation velocities of carriers which
is ~ 1×107 cm/s for both electrons and holes.
Therefore, comparable transconductance values are
obtained from both NMOS and PMOS devices.
But PMOS devices have a higher series resistance
than their NMOS counterparts. The reason is that
PMOS shallow source/drain junctions are formed by
boron diffusion, whereas NMOS shallow junctions
use arsenic diffusion. Higher diffusion coefficient of
boron than arsenic, results in larger peak surface
concentration of arsenic than boron. On the other
hand, P-channel MOS devices are more resistant to
hot carrier effects than N-channel devices. This is a
major advantage favouring PMOS.
The above hurdles in MOS scaling have
necessitated that research must resort to other
approaches to achieve further development in this
area.
Because continuous shrinkage of MOS device
dimensions has to meet both functionality and
manufacturability requirements, it is necessary to look
for new device structures, such as delta-doped (DD)
MOSFET, pocket-implanted (PI) MOSFET, partiallyand fully-depleted (PDSOI and FDSOI) MOSFETs
and double-gate (DG) MOSFET, to sustain the
growth of the IC industry in the nanotechnology era26.
Retrograded doping profile can lower the minimum
achievable channel length by 20 per cent, i.e., up to
70 nm. Partially-depleted SOI MOSFET has a
comparable scaling potential to the bulk MOSFET but
fully-depleted SOI MOSFET is difficult to be scaled
below 150 nm for satisfactory short-channel
performance. Only the DG MOSFET can achieve
very small channel length with low threshold voltage
and thick gate oxide > 4 nm. The two gates provide
good electrostatic integrity minimizing the draininduced barrier lowering and threshold voltage
variation with channel length.
Nanotechnology is the creation of materials,
devices and systems through the control of matter on
the nanometer length scale (at the level of atoms,
molecules and supramolecular structures) and the
utilization of novel properties and phenomena
occurring at that scale. As all natural materials and
processes lay down their groundwork at the nanoscale
the control of matter at this scale means tailoring the
fundamental properties exactly at the scale where they
are determined. A nanometric structure is one which
has at least one characteristic dimension measured in
nanometers.
4 Basic Physics of Single Electronics
Single electronics is concerned with the controlled
flow of electrons between small conducting
islands27-29. The underlying idea of single electronics
is shown in Figure 4, where a small conductor called
the island is electrically neutral in the beginning
(Figure 4a). Hence, an additional electron is
transferred to the conductor even by a feeble force,
e.g., by tunneling across an energy barrier produced
KHANNA: COMPARATIVE ANALYSIS FOR HIGH-PERFORMANCE COMPUTATIONAL NANOELECTRONICS
801
Fig. 5—Schematic of the single-electron box
Fig. 4—The basic concept of single-electronics
by a thin dielectric layer. This electron upsets the
charge balance of the island making it electrically
negative. The negative charge thus acquired by the
island prevents any further electron from reaching in
its vicinity (Fig. 4b) due to the high electric field
created by it which may be ~ 140 kV/cm on the
surface of sphere of 10-nm diameter in vacuum. The
high electric field is an effect produced by the
extremely small size of the island. This effect is
expressed in terms of the charging energy given by
2
,
E =q
C
c
… (1)
where q is the electronic charge and C is the
capacitance of the island. The blockage of the transfer
of any further electron to the island by virtue of
Coulomb repulsion is called the Coulomb blockage
effect. A single-electron device is defined as an
electronic component in which the addition or
subtraction of electrons to/from an electrode is
controlled with the precision of a single electron
using the Coulomb blockade effect.
As the island size is decreased, in the limiting case
when it becomes comparable with the de Broglie
wavelength of electrons in the island the energy
quantization phenomenon becomes pronounced.
Hence, in place of the charging energy, a more
relevant concept is the electron addition energy Ea
expressed as:
E a = Ec + E k ,
… (2)
of which the charging energy Ec is one component and
the remaining part is the quantum kinetic energy of the
electron (Ek).
The condition for appearance of Coulomb blockade
effect is that the Coulomb energy becomes comparable
to thermal energy. When the island size is 100 nm, Ec
has the major contribution to Ea which is around 1
meV ~ 10 K. To avoid the suppression of singleelectron effects by thermal noise the experiments
must be conducted below 1 K. For island size of 10
nm, Ea is 100 meV so that the device is capable of
room-temperature operation. But for many singleelectron devices the island size has to be reduced to
less than 1 nm, which is inconveniently smaller than
present day lithographic resolution permits. Then Ek
starts to play the decisive role. Hence, such small
islands are known as quantum dots. At this scale the
transport properties are extremely sensitive to dot size
and shape, and therefore islands of this size are
generally avoided.
5 Principal Single-Electron Devices (SEDs)
(a) Single-electron Box, the Conceptually Simplest Singleelectron Device
This device (Fig. 5) consists of a reservoir of
electrons called the source separated by a tunnel
barrier from an island beyond which is placed a gate
electrode. On applying a voltage to the gate electrode,
electron tunneling is initiated between the source and
the island. As an electronic component of a digital
computer the single-electron box has the disadvantage
that the number of electrons in the box uniquely
depends on the applied voltage so that the component
cannot be used as a memory device for storing
information. Furthermore the component is unable to
carry direct current. Hence, an electrometer is
required to measure its charge state.
(b) Single-electron Transistor
This structure (Figure 6) overcomes the drawbacks
of the single-electron box. It consists of a small
conducting island sandwiched between two tunnel
barriers, and a controlling gate electrode. Effectively,
it comprises a conducting island placed between the
source and drain terminals instead of the channel or
inversion layer in a MOSFET. Every time a single
electron is added to the island the transistor turns ON
802
J SCI IND RES VOL 63 OCTOBER 2004
Fig. 6—The capacitively-coupled single-electron transistor
and OFF.
The building block for single electron devices is
the multiple tunnel junction containing multiple
tunnel barriers and electron islands. Electron islands
are made by pattern dependent oxidation (PADOX)
method28. Naturally formed islands are also used.
Nanosilicon materials too have been investigated.
6 Advantages and Shortcomings of Single
Electronics; and Emphasis on Single-electron
Memory Instead of Logic
Major advantages of single electronics are: (i) Easy
scalability which results from the operation of devices
on Coulomb repulsion between electrons allowing the
devices to operate at atomic dimensions rendering
ultra-large scale integration possible, (ii) Low power
dissipation because of the involvement of a very
small number of electrons to accomplish basic
operations, and (iii) High operating speed because of
transference of a small number of electrons in a
process contrary to the charging or discharging of a
large number of electrons ~ 105 in a single digital
operation.
The foremost difficulty encountered when using
single-electron devices in a logic functional unit is
their poor current drive capability as compared to
CMOS devices. Since communication with a distantly
located logic unit is a prime requirement, this task is
performed by CMOS devices. The second serious
shortcoming is the need for low-temperature
operation. Such operation may be suitable for
understanding the physical mechanisms of devices but
the impact of the technology on industry and society
will be felt only when the devices are capable of
operating at room temperature, a feature which
requires sub-10 nm structures that are not easy to
fabricate from the lithographic standpoint. Thirdly,
tunneling is exponentially sensitive to atomic layer
fluctuations in barriers producing unacceptably large
device to device variations.
Like the CMOS circuits, research in single-electron
devices has also tended to pursue binary logic30-32.
Methods used for single-electron device research are
direct electron beam writing and scanning probe
manipulation. Low speed prevents the application of
these methods to whole chip or whole wafer level.
Consequently the fabrication of ULSI circuits with
nm resolution seems a prohibitively costly affair. The
prospects of single electronics, at least for computer
logic, are therefore, discouraging27. Furthermore, it
must be emphasized that present-day technological
problems like long interconnect delay and large power
consumption cannot be satisfactorily solved by simply
replacing the conventional devices with the singleelectron ones. By this one-to-one substitution the
situation may even get worsened because of the low
drivability resulting from the high tunneling
resistance of single-electron devices. The inferior
drive capability of a single-electron device leads to its
poor interaction with a remotely located logic unit.
This problem is circumvented by using a multi-valued
logic scheme33 that achieves high functionality with
fewer components and interconnections. Singleelectron transistor has unique characteristics34 such as
periodic increase and decrease of drain current with
gate voltage besides staircase-like increase of drain
current with drain voltage thus providing more
functions by using a smaller number of circuit
components.
But single electronics/FET hybrid memory is
promising. Here, also the requirement of high-cost
ULSI nanofabrication methods such as multiple
electron beam writing is a major economic
disadvantage. Besides, single electronics also
provides the physical understanding of the limitations
of single-electron charging effects on nanoscale
devices. It has applications in unique scientific
instrumentation like metrology or as tools of scientific
research, and for fundamental standards of current,
resistance and temperature.
7 Necessity of Molecular Electronics, and the
Advantages Offered
Any successful technology must allow room
temperature operation at the atomic level. It must use
self-aligned fabrication. Interconnections between
KHANNA: COMPARATIVE ANALYSIS FOR HIGH-PERFORMANCE COMPUTATIONAL NANOELECTRONICS
devices must also be addressed. Molecular electronics
is an emerging field that seeks to utilize the properties
of individual molecules or groups of molecules,
notably polyphenylene chains, carbon nanotubes,
porphyrins, ploythiophenes, and DNA (deoxyribonucleic acid) strands to perform logic or memory
functions in microelectronic circuits that are now
implemented by semiconductor devices35-39. As
molecules are 107-times smaller than transistors, they
afford substantial miniaturization so that lithographic
advances will have to care of the size advantage
offered by molecules to provide proportionate
increase in computation capability per unit area.
Moreover, as transistor costs fall on bulk
manufacturing, molecular devices also benefit from
batch production by replication of molecules in large
numbers with high yields. Thus in manifold ways,
molecular electronics seems to be more rewarding.
8 Distinction between Bulk Applications of
Molecules and Molecular-scale Electronics;
Enabling Technologies and Terminological
Analogies
Molecular materials, mainly organic type, have
long been used for electronic and photonic
applications such as, liquid crystal displays (LCDs),
light-emitting diodes (LEDs), lasers, transistors, and
sensors. But in molecular electronics the molecule
itself is looked upon as an active electronic device,
e.g., unimolecular rectification takes place through
the molecular orbitals of a single D-σ-A molecule by
through-bond tunneling mechanism (D denotes an
electron donor having a low ionization potential, A is
a high electron-affinity electron acceptor, and σ is a
covalent bridge).
Polyphenylene molecules act as conductors.
Carbon nanotubes or bucky tubes of different
diameters and helicities, exhibit wide-ranging
behaviour from conductors to insulators. A junction
between two types of chiral structures results in a
diode switch. A field-effect transistor is made by
incorporating a single-wall nanotube between two
metal electrodes. Experiments on DNA have yielded
various results from insulating properties to metallic
conduction due to different DNA sequencing
conditions.
Enabling technologies for molecular electronics are
the nanofabrication techniques in conjunction with
atomic imaging techniques such as, scanning
tunneling microscope (STM) and atomic force
microscope (AFM). ATM and AFM are the main
803
Fig. 7— A simple nanocell
tools for detection, measurement and maneuvering of
individual molecules. The key requirement in
molecular electronics is the placement and connection
of a molecule between metal electrodes. An important
technique uses the spontaneous self-absorption of
molecules between contacts such as, the ability to
form self-assembled monolayers (SAM) of oligomers
on metals.
The terminology of solid-state physics is modified
in molecular electronics as: Highest occupied and
lowest occupied molecular orbitals take the place of
valence and conduction bands. Similarly, instead of
doping for Fermi level modification, one refers to
changes in electron affinity and ionization potential of
molecules through chemical substitution. The
analogue of bandgap engineering is designing in
molecular orbitals.
9 Nanocell Circuits for Logic and Memory
Functions
The nanocell40,41 is a molecular electronics
architecture comprising a random, self-assembled
array of molecules and conducting nanoparticles
which are addressed by metallic leads or input/output
(I/O) pins, for programming the nanocell as a logic
gate or memory device, after the fabrication of the
cell. Fig. 7 shows a simple nanocell containing two
nanoparticles depicted as circles and five molecular
switches indicated by dark and bright lines, dark for
ON and bright for OFF states of molecules, and the
two input/output leads shown as black rectangles.
Immediately after fabrication the nanocell conducts
electricity across its leads in a non-linear fashion.
Only after proper programming does it carry out the
desired functions. The programming is done by
804
J SCI IND RES VOL 63 OCTOBER 2004
Fig. 8—A clocked six-dot quantum-dot cellular automata cell
applying voltage pulses in an algorithmically defined
order to the cell leads whereby the molecules switch
their states in accordance with voltage dependent
switching rules, and the cell is configured for the
targeted logic function. The nanocell exploits the selfassembling tendency of molecules to place them in
predefined regions at the required densities, thereby
building the interconnection pathways. Thus the focal
idea of a nanocell is to simplify cell fabrication and
transfer the difficult tasks to the post-fabrication
programming. Although the constructional units of the
nanocells are molecules the nanocells have dimensions
on the micron scale so that lithographic techniques can
be utilized for making the inteconnections.
10 Clocked Molecular Quantum-dot Cellular
Automata (QCA)
Another favourite molecular electronics design is
the clocked molecular quantum-dot cellular automata
(QCA)42-45. In this computing approach the present-day
switches are not used. However, binary digits are
retained by representing the information as the
electronic charge configuration among the quantum
dots of a cell. The devices are made up of cells which
themselves are build up of a small number of quantum
dots, defined as regions wherein charge is localized.
Figure 8 shows a clocked six-dot QCA cell. The cell
contains two additional mobile electrons which have a
tendency to minimize their mutual Coulomb interaction
by occupying the opposite corners of the cell. The four
dots occupying the opposite corners of the cells
therefore determine the two energetically equivalent
ground degenerate state polarizations of the cell
designated as the binary “0” and “1”. For computations
the cells are placed near each other. Then interaction
takes place between the adjoining cells via capacitive
coupling. Perturbation of the neighbouring cell on any
cell clicks this cell into an aligned configuration, either
a 1 or 0, without any current flowing between the cells.
The middle dot of each cell is used for clocking
purposes. The potential of this dot can be varied. For a
large, attractive potential the mobile charges are pulled
by the middle dot producing the null state of the cell in
which it contains no information. When the potential of
the middle dot is large but repulsive the charge shifts to
the cell corners resulting in a 1 or 0 state. Clocked
control of the QCA cell provides reduces the power
dissipation and provides power gain. It also furnishes
computational pipelining. In molecular electronics the
role of quantum dots is played by the redox centres
which are reduced by adding an electron or oxidized by
losing an electron, without breaking the chemical
bonds. Thus the QCA paradigm offers the simplicity of
binary representation and general-purpose computation
in nanoscale computing.
11 Conclusions
This paper examines the present status and
forecasts of microelectronic devices and circuits for
the computing industry. Three distinct competing
challenges have emerged: (i) To solve the problems of
the mainstream CMOS technology in the sub-10 nm
region, (ii) To solve the low-temperature operation
problems of single electronics, i.e., the random charge
effect, so that reliable room-temperature device
operation becomes a reality, and (iii) To radically
change the present line of thinking, and visualize
computers built from molecular designs such as QCA,
a transistorless computation paradigm that addresses
device interconnections. Motivation for such
paradigms is provided by the opportunity to break
away from the long-prevailing FET-based logic of
current switches by making the basic logic element an
array of quantum dots.
Amongst these three candidate approaches the
CMOS technology has achieved the highest degree of
maturity. It indubitably occupies the ‘enviable
supreme position’. Prospects of single-electron logic
as a frontier technology are dismal but single
electron/FET hybrid memory, and combined singleelectron/ metal-oxide-semiconductor transistor multivalued logic33 could be used as a supportive
technology to CMOS circuits. The potential of
molecular electronics remains to be harnessed.
Perhaps its impact may be more penetrating and
effective in introducing revolutionary or evolutionary
changes in the scenario in the long run.
KHANNA: COMPARATIVE ANALYSIS FOR HIGH-PERFORMANCE COMPUTATIONAL NANOELECTRONICS
Acknowledgements
The author is thankful to the Director, CEERI,
Pilani for his encouragement in preparation of this
manuscipt.
References
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Khanna V K, Physics of carrier-transport mechanisms and
ultra-small scale phenomena for theoretical modeling of
nanometer MOS transistors from diffusive to ballistic
regimes of operation, Phys Rep (2004) (in press).
Goldhaber-Gordon D, Montemerlo M S, Love J C, Opiteck
G J & Ellenbogen J C, Overview of nanoelectronic devices,
Proc IEEE, 85 (1997) 521-540.
Kastner M A, The single-electron transistor, Rev Mod Phys,
64 (1992) 849-858.
Chou S Y & Wang Y, Single-electron Coulomb blockade in
a nanometer field-effect transistor with a single barrier, Appl
Phys Lett, 61 (1992)1591-1593.
Devoret M H, Esteve D & Urbina C, Single-electron transfer
in metallic nanostructures, Nature, 360 (1992) 547-553.
Ancona M G, Design of computationally useful singleelectron digital circuits, J Appl Phys, 78 (1995)1-14.
Krotkov A N, Wireless single-electron logic biased by
alternating electric field, Appl Phys Lett, 67 (1995)24122414.
Meirav U & Foxmann E B, Single-electron phenomena in
semiconductors, Semiconduct Sci Technol, 10 (1995) 255284.
Takahashi Y, Nagase M, Namatsu H, Kurihara K, Iwadake
K, Nakajima Y, Horiguchi S, Murase K & Tabe M, A
fabrication technique for Si single-electron transistor
operation at room temperature, Electron Lett, 67 (1995)2957.
Ahmed H & Nakazoto K, Single-electron devices,
Microelectronic Eng, 32 (1996) 297-315.
Wolfram S, Computational theory of cellular automata,
Commun Math Phys, 96 (1984) 15-57.
Conrad M, The lure of molecular computing, IEEE
Spectrum, 23 (1986) 55-60.
Tour J M, Wu R & Schumm J S, Extended orthogonally
fused conducting oligomers for molecular electronic devices,
J Am Chem Soc, 113 (1991)7064-7066.
Martin S, Sambles J R & Ashwell G J, Molecular rectifier,
Phys Rev Lett, 70 (1993)218-221.
Tour J M & Schumm J S, Synthesis of molecular wires by a
novel divergent/convergent approach, Polymer Prepr, 34
(1993)368-369.
Hong F T, Molecular electronics: Science and technology for
the future, IEEE Eng Med Biol, 13 (1994) 25-32.
Subramanyam V, Molecular electronics, Curr Sci, 67 (1994)
844-852.
Samanta P, Tian W, Datta S, Henderson J I & Kubiak C P,
Electronic conduction through organic molecules, Phys Rev
B, 53 (1996) p. R7626.
Mujica V, Kemp M, Roitberg A & Ratner M, Currentvoltage characteristics of molecular wires: Eigenvalue
staircase, Coulomb blockade and rectification, J Chem Phys,
104 (1996) 7296-7305.
Taur Y, Mii Y, Frank D, Wong H –S, Buchanan D, Wind S,
Rishton S, Sai-Halasz G & Nowak E, CMOS scaling into the
21 st century: 0.1 µm and beyond, IBM J Res Dev, 39 (1995)
245.
805
21 Asenov A, Brown A R, Davies J H, Kaya S & Slavcheva G,
Simulation of intrinsic parameter fluctuations in
decananometer and nanometer-scale MOSFETs, IEEE Trans
Electron Devices, 50 (2003) 1837-1852.
22 Ferry, D K, Akers L A & Greeneich E W, Ultra large scale
integrated microelectronics (Prentice Hall: Englewood
Cliffs, N J) 1988.
23 Suehle J S, Ultrathin gate oxide reliability: Physical models,
statistics and characterization, IEEE Trans Electron Dev, 49
(2002) 958-971.
24 Aoyama T, Suzuki K, Tashiro H, Tada Y, Arimoto H &
Horiuchi K, Flatband voltage shift in PMOS devices caused
by carrier activation in P+-polycrystalline silicon and by
boron penetration, IEEE Trans Electron Dev, 49 (2002) 473480.
25 Fischetti MV, Laux S E & Crabbé E, Understanding hotelectron transport in silicon devices: Is there a shortcut?, J
Appl Phys, 78 (1995) 1058-1087.
26 Wann, C H, Noda K, Tanaka T, Yoshida M & Hu C, A
comparative study of advanced MOSFET concepts, IEEE
Trans Electron Dev, 43 (1996)1742-1753.
27 Likharev K K, Single-electron devices and their applications,
Proc IEEE, 87 (1999) 606-632.
28 Ono Y, Takahashi Y, Yamazaki K, Nagase M, Namatsu H,
Kurihara K & Murase K, Fabrication method for IC oriented
Si single electron transistors, IEEE Trans Electron Dev, 47
(2000) 147-153.
29 Scholze A, Schenk A & Fichtner W, Single-electron device
simulation, IEEE Trans Electron Dev, 47 (2000) 1811-1818.
30 Tucker J R, Complementary digital logic based on the
Coulomb blockade, J Appl Phys, 72 (1992) 4399-4413.
31 Takahashi Y, Fujiwara A, Yamazaki K, Namatsu H,
Kurihara K & Murase K, Multigate Single electron
transistors and their application to an exclusive OR-Gate,
Appl Phys Lett, 76 (2000) 637-639.
32 Ono Y, Takehashi Y, Yamazaki K, Nagase M, Namatsu H,
Kurihara K & Murase K, Si Complementary single-electron
inverter with voltage gain, Appl Phys Lett, 76 (2000) 31213123.
33 Inokawa H, Fujiwara A & Takahashi Y, A multi-valued logic
and memory with combined single-electron and metal-oxidesemiconductor transistors, IEEE Trans Electron Dev, 50
(2003) 462-470.
34 Inokawa H & Takahashi Y, A compact analytical model for
asymmetric single-electron tunneling transistors, IEEE Trans
Electron Devices, 50 (2003) 455-461.
35 Aviram A, Molecules for memory, logic and amplification, J
Am Chem Soc, 110 (1988) 5687-5692.
36 Reed M A, Molecular-scale electronics, Proc IEEE, 87
(1999) 652-658.
37 Lent C S, Molecular electronics: Bypassing the transistor
paradigm, Science., 288 (2000) 1597-1599.
38 Rastogi S, Rao V R, Jhaveri R, Mukherji S & Ravikanth M,
Status and trends in molecular electronics, IETE Tech Rev,
19 (2002) 307-315.
39 Tour J M, Molecular electronics: Commercial insights,
chemistry, devices, architecture and programming (World
Scientific: River Edge, N J) 2002.
40 Tour J M, VanZandt W I, Husband C P, Husband S M,
Wilson I S, Franzon P D & Nackashi D P, Nanocell logic
gates for molecular computing, IEEE Trans Nanotechnol, 1
806
41
42
J SCI IND RES VOL 63 OCTOBER 2004
(2002) 100-109.
Husband C P, Husband S M, Daniels J H & Tour J M, Logic
and memory with nanocell circuits, IEEE Trans Electron Dev,
50 (2003) 1865-1975.
Snider G L, Orlov A O, Amlani I, Zuo X, Bernstein G H, Lent C
S, Merz J L & Porod W, Quantum-dot cellular automata:
Review and recent experiments, J Appl Phys, 85 (1999) 42834285.
43 Timler J & Lent C S, Dissipation and gain in quantum-dot
cellular automata, J Appl Phys, 91 (2002) 823-831.
44 Lent C S & Isaksen B, Clocked molecular quantum-dot
cellular automata, IEEE Trans Electron Dev, 50 (2003)
1890-1896.
45 Lent C S, Isaksen B B & Lieberman M M, Molecular
quantum-dot cellular automata, J Am Chem Soc, 125 (2003)
1056-1063.