ISSN:2229-6093
S K Raffi et al, Int.J.Computer Technology & Applications,Vol 7 (1),152-161
HARMONICS REDUCTION BY MULTICARRIER PWM TECHNIQUES FOR
CASCADED H-BRIDGE INVERTER
SK.RAFFI
Asst.Professor
Department of Electrical & Electronics
Engineering, VNITSW, GUNTUR
R.SRIKANTH
Asst.Professor
Department of Electrical & Electronics
Engineering, VNITSW, GUNTUR
Abstract
The power electronics device which
converts DC power to AC power at required
output voltage and frequency level is known
as inverter. Inverts can be broadly classified
into single level inverter and multilevel
inverter. The conventional two level inverter
is poor due to the presence of harmonics and
hence produces power loss which reduces
the efficiency of the system. The multilevel
inverter is used to improve the voltage
quality by reducing the harmonics, as the
number of voltage levels of multilevel
inverter is increased the harmonics are
reduced and hence losses are minimized
significantly. A multi-stage inverter is being
utilized for multipurpose applications, such
as active power filters, static VAR
compensators and machine drives for
sinusoidal
and
trapezoidal
current
applications.
In this paper comparison of
multicarrier PWM techniques for 5, 7, 9
and11 level cascaded H-bridge inverters are
simulated using simulink. The simulation
results show that 7-level inverter with phase
opposition disposition technique provides
low total harmonic distortion.
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Keywords: Multilevel inverter, multicarrier
PWM, Phase shifted modulation, Total
harmonic distortion (THD).
I.INTRODUCTION
Dc to Ac converters are known as inverters.
The function of an inverter is to change a dc
input voltage to a symmetric ac output
voltage of desired magnitude and frequency.
The output voltage could be fixed or
variable at a fixed or variable frequency. A
variable output voltage can be obtained by
varying the input dc voltage and maintaining
the gain of the inverter constant. On the
other hand, if the dc input voltage is fixed
and it is not controllable, a variable input
voltage can be obtained by varying the gain
of the inverter which is normally
accomplished by pulse width modulation
(PWM) control within the inverter. The
inverter gain may be defined as the ratio of
ac output voltage to dc input voltage.
The output voltage waveform
of ideal inverter should be sinusoidal.
However, the waveform of practical
inverter is non sinusoidal and contain
certain harmonics. For high-power
applications, low distorted sinusoidal
waveforms are required. With the
availability of high speed power
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S K Raffi et al, Int.J.Computer Technology & Applications,Vol 7 (1),152-161
semiconductor devices, the harmonic
content of the output voltage can be
minimized or reduced significantly by
switching techniques.
Three phase inverters are
normally
used
for
high-power
applications. Three single-phase half (or
full)-bridge inverters can be connected in
parallel as shown in figure to form the
configuration of a three-phase inverter.
The gating signals of single-phase
inverters should be advanced or delayed
by 1200 with respect to each other to
obtain
three-phase
balanced
(fundamental) voltages.
A three-phase output can be
obtained from a configuration of six
transistors and six diodes as shown in
figure 1. Two types of control signals
can be applied to the transistors: 1800
conduction or 1200 conduction. The 1800
conduction has better utilization of the
switches and is the preferred method.
approximate to the sinusoidal waveform.
Multilevel inverters are the modification
of basic bridge inverters. They are
normally connected in series to form
stack of levels.
A multilevel inverter can be defined as a
device that is capable to produce a
stepped waveform. The generalized
stepped waveform is shown in figure 2.
When designing a multilevel inverter,
the most important feature or key issue is
to ensure that the total harmonic
distortion (THD) of the output voltage is
small enough to produce an effective
multilevel inverter. There are standards
prescribed for inverter output voltage
THD and their magnitudes. The value of
the output harmonics must
Fig: 2 Waveform of multilevel inverter
Fig: 1 three phase bridge inverter
II. MULTILEVEL CONCEPT
Recent advances in Power Electronics
have made the multilevel concept
practical. The generalized idea of a
multilevel inverter is to utilize the active
semiconductor to produce power
conversion in small voltage steps that is
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always be below the threshold value. The
lower-order harmonics are difficult to filter
due to the filter size and filter order. The
lower-order harmonics are the most
troublesome harmonic because they can
cause serious distortion in the output
voltage.
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S K Raffi et al, Int.J.Computer Technology & Applications,Vol 7 (1),152-161
Cascaded H-bridge multilevel inverter
The common topologies of the
multilevel inverter are diode clamped
multilevel inverter (DCMI), flying
capacitor multilevel inverter (FCMI) and
cascaded h-bridge multilevel inverter
(CHMI) or modular structured multilevel
inverter (MSMI).
The CHMI is unique because of
its modular properties which consist of a
series of H-bridge inverters with
separated DC sources. The DC source
can be any kind of DC supply such as
batteries, fuel cells, solar cells, etc.
Generally, CHMI operates to produce or
synthesize the required output voltage
from the separate DC sources.
Figure 3.shows the CHMI with nth
level of H-bridge with nth number of DC
sources. Each of the H-bridge consists of
a DC source with a combination of four
switches mainly S1, S2, S3 and S4. Each
of the H-bridge will be able to produce
three different quasi waveform output
which is +VDC, 0, -VDC depending on
the switching state. Each of the
switching always conducts for 180oor
half-cycle regardless of the pulse width
of the quasi-square wave so that this
method will result in the equalization of
the current stress in each of the
components .When each of the H-bridge
is active in certain amount of time at a
different start up angle, the output of the
multilevel inverter will be the sum of the
DC source across the multilevel inverter
as follows:
Va-n=Va1+Va2+Va3+..............+Van
The number of steps of the output
voltage mostly depends on the number of
DC sources which is where
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Fig: 3 Single-phase structure of a CHMI
m =number of steps of the output voltage
n= number of the DC sources10
For example, if there are five DC sources
then the steps of the
Output voltage will be eleven. Figure 2
shows the quasi output waveform of a
multilevel inverter with eleven numbers
of steps. As shown in Figure 2. the
output waveform is almost Sinusoidal.
With appropriate amount of levels and
switching algorithm, the result or output
voltage
will
be
almost
sinusoidal.cascaded H-bridge multilevel
inverter is considered as the main
topology.
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III.MULTICARRIER PWM
Multicarrier PWM method is based
on a comparison of a sinusoidal
reference waveform, with vertically
shifted carrier signals. This method uses
N-1 level carrier signals to generate the
N-level inverter output voltage. In
multilevel inverter, the frequency
modulation index, mf and the amplitude
modulation index, mi are defined as
both carrier waveforms. 3. The converter
is switched to zero when the reference is
greater than the lower carrier waveform
but less than the upper carrier waveform.
4. The converter is switched to 2Vdc
when the reference is less than both
carrier waveforms.
mf =fc/fm
mi =Am/ (n-1) Ac
Where
fc= carrier signal frequency,
fm= reference signal frequency,
Ac= carrier signal amplitude,
Am= reference signal amplitude.
The multicarrier PWM method can
be divided into few strategies.
• Phase disposition (PD-PWM) -All
carrier signals are in phase.
• Phase Opposition Disposition (PODPWM) - All carrier signals about zero
reference is in phase and 1800 out of
phase with those below zero
•
Alternative
Phase
Opposition
Disposition
(APOD-PWM)
-Every
carrier signal is out of phase with its
neighbour carrier by 1800.
• Phase Shifted Carrier (PSC-PWM)
A.PHASE DISPOSITION (PD)
There in, the a-phase modulation signal
is compared with two triangle waveforms.
The rules for the in phase disposition
method, when the number of level N = 5,
are
1. The N –1 = 5-1= 4 carrier waveforms
are arranged so that every carrier is in
phase. 2. The converter is switched to
+Vdc when the reference is greater than
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Fig: 4 Phase disposition
B. PHASE PPOSITION DISPOSITION
(POD)
For phase opposition disposition
(POD) modulation all carrier waveforms
above zero reference are in phase and are
180° out of phase with those below zero.
The rules for the phase opposition
disposition method, when the number of
level N = 5
1. The N –1 = 4 carrier waveforms are
arranged so that all carrier waveforms
above zero are in phase and are 180 out
of phase with those below zero 2. The
converter is switched to + Vdc when the
reference is greater than both carrier
waveforms. 3. The converter is switched
to zero when the reference is greater than
the lower carrier waveform but less than
the upper carrier waveform.4. The
converter is switched to +2Vdc when the
reference is less than both carrier
waveforms.5. When the modulation s
ignal is greater than both the carrier
waveforms, S1 and S2 are turned on and
the converter switches to positive node
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voltage and when the reference is less
than the upper carrier waveform but
greater than the lower carrier, S2and S1
are turned on and the converter switches
to neutral point. When the reference is
lower than both carrier waveforms, S1an
and S2an are turned on and the converter
switches to negative node voltage.
converter switches to –1 Vdc when the
reference is greater than the lowermost.
6. Carrier waveform and lesser than all
other carriers.The converter switches to 2Vdc when the reference is lesser than
the entire carrier waveforms. Switching
pattern produced using the APOD
carrier-based PWM scheme for a fivelevel inverter: Four triangles and the
modulation signal
Fig: 5 phase opposition disposition (POD)
C.ALTERNATE PHASE OPPOSITION
DISPOSITION (APOD)
In case of alternate phase disposition
(APOD) modulation, every carrier
waveform is in out of phase with its
neighbor carrier by 1800. Since APOD
and POD schemes in case of five-level
inverter are the same, a five level inverter
is considered to discuss about theAPOD
scheme. The rules for APOD method,
when the number of level N = 5, are
1. The N –1 = 4 carrier waveforms are
arranged so that every carrier waveform
is in out of phase with its carrier by 180.
The converter switches to +I Vdc when
the reference is greater than all the
carrier waveforms.
2. The converter switches to 2 Vdc when
the reference is less than the uppermost
carrier waveform and greater than all
other carriers. 3. The converter switches
to 0 when the reference is less than the
two uppermost carriers 4. Waveform and
greatest than lowermost carrier. 5. The
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Fig: 6 alternative phase opposition
disposition (APOD)
5.8 phase shifted PWM (PSPWM)
In PSPWM all the triangular carriers
have the same frequency and same peakpeak amplitude. But there is a phase shift
between any two adjacent carrier waves.
For m voltage levels (m-1) carrier
signals are required and they are phase
shifted with an angle of
.
The gate signals are generated with
proper comparison of carrier wave and
modulating signals.
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Fig: 7 .Phase shifted PWM(PSPWM)
IV. 5-LEVEL INVERTER
Fig:8 show the connection diagram
of single phase 5-level cascaded multi
level inverter. It consists of two Hbridges, each of H-bridge unit has its
own dc sources and each H-bridge can
produce three different voltage levels:
+V, 0,-V.by connecting the dc source to
ac output side by different combinations
of the four switches S1,S2,S3,S4 of one Hbridge and S5,S6,S7,andS8 of other Hbridge.the ac output voltage of each Hbridge is connected in series such that
the synthesized output voltage waveform
is the sum of all of the individual Hbridges outputs.
There are many possible switch
combinations to generate the five-level
output voltage.table.1 lists a possible
combination of the voltage levels and
their corresponding switching states.
Fig: 8 five level cascaded H-bridge
multilevel inverter
Using such a switch combination
requires each device to be switched only
once per cycle. It can be noticed from the
table.1 that the switching devices have
unequal turn on time.
V0
S1
S2
S3
S4
S1’
S2’
S3’
S4’
0
0
0
0
0
0
0
0
0
-V 0
0
0
1
0
1
1
0
0
2V
V 0
1
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
2V
Table: 1 switching states of five level
cascaded H-bridge multilevel inverter
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S K Raffi et al, Int.J.Computer Technology & Applications,Vol 7 (1),152-161
V. 7-LEVEL INVERTER
Fig:9 show the connection diagram of
single-phase 7-level cascaded inverter. It
consists of three H-bridges, each of Hbridge circuit has its own dc sources and
each H-bridge can produce three
different voltage levels .By connecting
the dc sources to ac output side by
different combinations of the four
switches similar to 5-level as above.
Here are many possible switch
combinations to generate the seven-level
output voltage.table.2 lists a possible
combination of the voltage levels and
their corresponding switching states.
Using such a switch combination
requires each device to be switched only
once per cycle. It can be noticed from the
table.1 that the switching devices have
unequal turn on time.
Fig: 9 7-level cascaded-bridge multilevel
inverter
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S K Raffi et al, Int.J.Computer Technology & Applications,Vol 7 (1),152-161
VI. SIMULATION AND RESULTS
5-level inverter with Multicarrier PWM
techniques (with fc=1 kHz
A.PSPWM (Phase Shifted Carrier) Method
Fig: 12 Phase voltage waveform of 5-level
inverter with PD-PWM
Fig: 10 Phase voltage waveform of 5-level
inverter with PS-PWM
Fig: 13 FFT Analysis
C.5-level CHB multilevel invert with
POD-PWM
Fig: 11 FFT Analysis
B.5-level CHB multilevel invert with
Phase disposition PWM
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Fig: 14 Phase voltage waveform of 5-level
inverter with POD-PWM
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S K Raffi et al, Int.J.Computer Technology & Applications,Vol 7 (1),152-161
7-LEVEL INVERTER WITH POD
PWM
Fig: 15 FFT Analysis
D.5-level CHB multilevel invert with
APOD-PWM
Fig: 18 Phase voltage waveform
of 7-level inverter with POD-PWM
Fig: 16 Phase voltage waveform of 5-level
inverter with APOD-PWM
Fig: 20 FFT Analysis
Fig: 17 FFT Analysis
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REFERENCES
VII.COMPARISIONS
THD(%) COMPARISION OF MULTI
CARRIER BASED PWM TECHNIQUES
PWM
5-LEVEL
7-LEVEL
PS
31.58
23.07
PD
30.95
22.86
POD
30.63
20.30
APOD
30.50
21.95
Table 2. THD (%) Comparison
VIII.CONCLUSION
In this paper 5 and 7 cascaded H-bridge
multi level inverters are simulated
using MATLAB/simulink software.
Multicarrier based sinusoidal pulse width
modulation (SPWM) scheme is used for
controlling the output voltage and THD
value by controlling amplitude of
modulating wave and carrier frequency
respectively. This simulation results
shows that the 7-level with Phase
Opposition Disposition (POD) gives
better THD i.e 20.30% compared to 5
levels.This level change gives reduced
THD values and good quality output
voltage with reduced harmonics.
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