SINGLE PHASE FIVE LEVEL INVERTER FOR PHOTOVOLTAIC
DISTRIBUTED GENERATION
1
NITHIN P N, 2STANY E GEORGE
1
M.Tech Scholar( EEE Department, FISAT ), 2Assistant Professor (EEE Department, FISAT)
Abstract- A new 5 level inverter topology is developed which can be efficiently utilized to inject real power in to the grid. The
switching losses, total harmonic distortion and electromagnetic interference remain less. A photovoltaic module is used to
source the inverter. Perturb and Observe (P&O) algorithm is utilized to track the maximum power point by switching a boost
converter. The inverter is composed of six power electronic switches out of which only two are high frequency PWM switched
and the rest four are switched in utility frequency. The output current of the 5 level inverter is controlled to generate a
sinusoidal current in phase with utility voltage. The inverter is switched such that the capacitor voltages remain balanced. A
carrier based level shifted PWM is utilized to reduce THD in the output voltage of the inverter
Keywords-Level Shifted Pulse width Modulation, Maximum Power Point Tracking (MPPT), Perturb and Observe (P & O)
and Total harmonic Distortion (THD).
multilevel converter topologies are the neutral point
clamped (NPC), flying capacitor (FC), cascaded
H-bridge (CHB). These converters present widespread
applications in ac motor drives such as in conveyors,
pumps, fans etc. Cascaded H-bridge has been
successfully commercialized for very high power and
power quality demanding applications up to range of
31MVA due to its series expansion capabilities. This
paper reveals the working and simulation of a new 5
level inverter topology sourced from a photovoltaic
module which proves to overcome some of the
limitations of conventional multilevel topologies.
I. INTRODUCTION
Energy scenario is changing. The intensified research
on renewable energy has lead to the emergence of a
new era where renewable energy resources like solar,
wind etc play the lead role. The use of hazardous fossil
fuels has become obsolete. The birth of semiconductor
technology and its widespread acceptance and
applications fuelled the design of various power
converter topologies. It has become the key
responsibility of these converters to integrate the
renewable energy sources in to the grid with required
efficiency.
II. CIRCUIT CONFIGURTAION
However, there exist a tough competition between
classic power converter topology using high voltage
semiconductor and new converter topologies like
multilevel inverters using medium voltage
semiconductors. Nowadays multilevel converters
prove to be a good solution to power application due to
the fact that they can achieve high power using
medium power semiconductor devices.
The new topology consist of six power electronics
switches, two dc link capacitors and two diodes which
constitute the five level inverter. The inverter is
sourced from a solar cell array and a boost converter is
used o transfer the maximum power utilizing perturb
and observe (P&O) maximum power point tracking
algorithm. The developed topology is shown in Figure
I.
A. Topology Description
i. Photovoltaic cell model
A photovoltaic (PV) cell is basically a PN junction and
acts as a current source. Energy from sunlight is
directly converted in to electrical energy. Where the
photons are absorbed by the semiconductor and free
electrons are released. The generated voltage of PV is
low and typically lies around 0.5V and 0.8V which
depends on the semiconductor used.
Multilevel converters present great advantage when
compared with two level converters. These advantages
are fundamentally focused on improvement in output
signal quality. As the number of level increase, the
THD in the inverter output remain less when
compared to two level inverters. The electromagnetic
interference is also minimized.
While bestowing all these advantages, the multilevel
converters bear some limitations too. The control of
the converter is complex when compared to
conventional topologies.
Since a single cell cannot be directly utilized to drive
an application, it is necessary to connect a number of
cells in series and parallel combination to form a PV
module. A mathematical model of PV array was
developed and I-V and P-V curve was obtained.
Balancing of dc capacitor voltage, high switching
losses still remain a serious issue. The most common
Proceedings of Second IRF International Conference on 10th August 2014, Cochin, India, ISBN: 978-93-84209-43-8
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Single Phase Five Level Inverter for Photovoltaic Distributed Generation
i. Maximum power point tracking
The PV panel output varies with variation in the
received solar energy and hence it is necessary to track
the maximum available power. This function can be
initiated by a dc/dc converter which transfers the
maximum power when switched at an appropriate
duty cycle. The switching signal can be derived by a
maximum power point tracking algorithm. A boost
converter is introduced that steps up the PV module
output voltage and also incorporates the function of
tracking the maximum power.
Figure I: Circuit Configuration of Developed Photovoltaic
Generation System
Perturb and Observe (P & O) algorithm is used for
maximum power point tracking. In this algorithm a
slight perturbation is introduced in the system. If this
perturbation results in an increase in power,
perturbation is continued in that direction. If it results
in decrease in power, the perturbation is preceded in
the opposite direction. This procedure is continued till
the steady state is reached. A PI controller then acts
moving the operating point of the PV module to the
voltage corresponding to the maximum power.
Figure II: Equivalent Circuit of PV Cell
The variation in series resistance influences the PV
cell outputs. The resistance is usually low and its
variation results in maximum power point deviations.
When series resistance increases maximum power
decreases. Shunt resistance of PV cell must be high
enough for higher output power. Low shunt resistance
results in sudden and steep collapse of cell current and
also the maximum power reduces. The simulation
results are shown in Figure III and Figure IV.
Figure V: Flowchart for Perturb and Observe
i. Five level inverter
The operation of five level inverter can be explained
using eight modes which include four modes for
positive half cycle and four modes for negative half
cycle. The voltage levels are +Vdc/2, +Vdc, 0, -Vdc/2
and -Vdc. Modes 1 to 4 explaining operation of
positive half cycles are shown below.
Figure III: Power versus Current Curve
Figure IV: Current versus Voltage Curve
Figure VI: Mode 1 Operation
Proceedings of Second IRF International Conference on 10th August 2014, Cochin, India, ISBN: 978-93-84209-43-8
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Single Phase Five Level Inverter for Photovoltaic Distributed Generation
Such a switching pattern keeps the capacitor voltage
balanced. This proves to be a great advantage when
compared to conventional topologies where capacitor
voltage balancing itself is a complex and tedious
process.
Figure VII: Mode 2 Operation
Figure VIII: Mode 3 Operation
Figure X: Simulation Circuit of Developed Topology
Figure IX: Mode 4 Operation
Modes 5 to 8 for negative half cycle is similar to
positive half cycle, except for switches S4 and S5
switches S6 and S7 will conduct. Among the six power
electronic switches, two switches S1 and S2 are
switched in high frequency PWM and the rest four
switches of H- bridge converter is switched in utility
frequency. The switching frequency is chosen as 20
kHz.
Figure XI: Generation of Switching Logic
In order to connect the inverter to the grid, the inverter
output has to be synchronized with that of grid. A
phase locked loop (PLL) has to be introduced to lock
the inverter frequency to that of utility frequency. For
this purpose, the grid current is sensed and it is send to
a PLL. The output of the PLL is a sine wave of unit
amplitude and utility frequency. The inverter output
voltage is sensed and compared to a set voltage. The
error signal is multiplied with the PLL output signal.
This gives the reference for inverter output current.
The inverter output current is sensed and compared
with reference current and further utilized for
generating inverter switching signals for switches S2
and S3.
The selection of switch S2 and S3 depends on the
voltage Vc2 and Vc3 across the capacitors C2 and C3.
When utility voltage is less than Vdc/2, S2 is switched
in high frequency PWM if Vc2> Vc3 and S3 is switched
in high frequency PWM if Vc3> Vc2. When utility
voltage is greater than Vdc/2, S2 is switched in high
frequency PWM if Vc3> Vc2 and S3 is switched in high
frequency PWM if Vc2> Vc3. The complete switching
states of the 5 level inverter is shown in Table. I
Table I: Switching States of Five Level Inverter
S2 S3 S4 S5 S6 S7
Vout
1
1
1
0
0
1
+Vdc
1
0
1
0
0
1
+Vdc/
2
0
1
1
0
0
1
+Vdc/
2
0
0
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
1
0 -Vdc/2
0
1
0
1
1
0 -Vdc/2
1
1
0
1
1
0
-Vdc
The detected utility voltage is also sent to a
comparator to obtain the switching signal for the full
bridge inverter switches S4 to S7. These switches are
switched in utility frequency. For positive half cycle
switches S4 and S7 are turned ON. For negative half
cycle switches S5 and S6 are turned ON.
Figure.XI describes the switching logic. As mentioned
earlier, only two power electronic switches S2 or S3 in
the five-level inverter should be switched in high
frequency, and only one of them is switched in high
frequency at any time, and the voltage level of every
Proceedings of Second IRF International Conference on 10th August 2014, Cochin, India, ISBN: 978-93-84209-43-8
26
Single Phase Five Level Inverter for Photovoltaic Distributed Generation
switching is Vdc/2. Therefore, the five-level inverter
can reduce the switching loss effectively.
III. SIMULATION RESULTS
The
circuit
model
was
simulated
in
MATLAB/Simulink. The parameters used in
simulation are shown in Table II. The grid voltage was
chosen to be 110V. The PV panel output was found to
be 48.24 volt that almost corresponds to maximum
power which is clear from the P-V curve obtained.
Waveforms of grid voltage, inverter output current,
inverter output voltage and capacitor voltages were
obtained which are shown in Figure.XII to Figure.
XIV. The THD of inverter current was found to be
3.79%. THD of inverter output voltage was found to be
11.39%. The voltage of dc link capacitors is shown in
Figure. XVI. The dc link voltage was found to be
balanced found to be balanced.
Figure XV: Inverter Output Current
Figure XVI: Capacitor Voltage
CONCLUSION AND FUTURE
ENHANCEMENT
Table II: Parameters Used in Simulation
DC bus capacitor (C2 2,200 µ F
and C3)
Filter inductor (Lf)
5mH
Transformer
1:1
Switching
20kHz
frequency(PWM)
Utility voltage
110V
Utility frequency
60Hz
Load resistor
100Ω
5 level inverter sourced by a PV panel was simulated
and necessary waveforms were obtained. Waveforms
of grid voltage, inverter current, voltage, capacitor
voltage etc were obtained. The capacitor voltage was
found to be almost balanced. The THD of inverter
current and voltage were verified. THD was found to
be within limits. The P&O algorithm implemented
was found successful in tracking the maximum power
from the PV panel. The switching losses will be less
when compared to conventional topologies since less
number of power electronic switches are used .Thus as
a whole the newly developed 5 level inverter is found
to have good performance under grid connected
application. The circuit can be extended to seven
levels which would probably improve its performance.
Battery energy storage system can be included in the
circuit which can counter sudden changes in the
received solar energy.
Figure XII: Grid Voltage
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Single Phase Five Level Inverter for Photovoltaic Distributed Generation
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