ISSN 2319-8885
Vol.03,Issue.02,
February-2014,
Pages:0285-0291
www.semargroup.org,
www.ijsetr.com
A Single-Phase Five-Level PWM Inverter for Grid Connection with Less
Number of Power Components
K.SRIHARIBABU1, CH.SRINIVASULU REDDY2
1
PG Scholar, Dept of EEE, PBR Visvodaya Institute of Technology & Science, Kavali, A.P, India.
Assoc Prof, Dept of EEE, PBR Visvodaya Institute of Technology & Science, Kavali, A.P, India.
2
Abstract: Recently, the emergence of single phase multilevel inverter has been increased due to its advantages over traditional
one. This paper proposes a single-phase five level pulse width modulation (PWM) inverter for grid connection employing PI
controller to perform unity power factor. Two triangular carrier signals identical to each other with an offset equivalent to the
amplitude of the reference signal were used to generate PWM signals for the switches. The proposed inverter has the advantage
of less number of components. Operational principles with switching functions are analyzed. A digital proportional integral
current control algorithm is implemented in FPGA XC3S400 to control the injected current into the grid to be almost
sinusoidal. The inverter offers much less total harmonic distortion and can operate at near-unity power factor. Some switches
operate at fundamental frequency and others operate at switching frequency. The proposed inverter has been compared with the
conventional single-phase five-level PWM inverter. The effectiveness of the proposed inverter and its control technique has
been verified theoretically, using PSIM simulation program, and experimentally, using laboratory prototype system.
Keywords: Multi-Level Inverters, Grid Connection, PWM.
I. INTRODUCTION
Multilevel Inverters (MLI) began with the neutral point
clamped inverter topology proposed by Nabaeetal
.Recently; multilevel inverters have become more
attractive for researchers due to their advantages over
conventional three-level pulse width-modulated (PWM)
inverters. MLI has two main advantages compared with the
conventional H-bridge inverters the higher voltage
capability and the reduced harmonic content in the output
waveform due to the multiple dc levels. MLI is now
preferred in high power medium voltage applications due
to the reduced voltage stresses on the devices. MLI
incorporates a topological structure that allows a desired
output voltage to be synthesized among a set of isolated or
interconnected distinct voltage sources. Numerous
topologies realize this connectivity, and can be generally
divided into three major categories, namely, diode clamped
MLI, flying capacitor MLI, and separated dc sources
(cascaded voltages) MLI Recently renewable energy
sources for grid connected applications are increased due
to the world energy crisis. Injecting power to the utility
must meet the world harmonic standards.
Therefore, single phase MLIs become a good solution
for those applications unfortunately one of the most
particular disadvantages of MLI is the large number of the
required power semiconductor switches. Although low
voltage rate switches can be utilized in a multilevel
inverter, each switch requires a related gate drive circuit.
This may cause the overall system to be more expensive
and complex. So, in practical implementation, reducing the
number of switches and gate driver circuits have become
an essential point. Recently, many topologies of the MLI
and its control techniques have been published. The MLI
technique is implemented in by adding one switch and four
power diodes to the H-bridge single phase inverter.
Another solution can be found in by using two switches
and two power diodes with the H-bridge single phase
inverter. Those two systems can generate only five levels
in the output voltage with less harmonic contents. The
other solution, shown in is a modular inverter that can
reach to any required voltage levels. But these inverters
topologies can be improved by reducing their switches
without affecting their performances.
This paper presents a single-phase five-level PWM
inverter with less number of power elements and hence
less gate drive circuits in addition to less circuit layout
complexity. Its output voltage has the following five
levels: Zero, +Vdc, +2Vdc, −Vdc, and −2Vdc. As the
number of output levels increases, the harmonic content
can be reduced. This inverter topology uses two carrier
signals to generate PWM signals for the switches. Some
switches operate at fundamental frequency and others at
switching frequency. Sections II and III explain the
principle of operation and PWM strategy for the proposed
Copyright @ 2014 SEMAR GROUPS TECHNICAL SOCIETY. All rights reserved.
K.SRIHARIBABU, CH.SRINIVASULU REDDY
inverter, respectively. The switching algorithm that used in
PWM is presented in section IV. Section V contains a
harmonic analysis for MLI. Moreover, a results and
comparison between the proposed MLI inverter and
conventional one are presented in section VI. Simulation
and experimental results are included in order to verify the
operating principle of the proposed MLI inverter and its
capability to inject active grid.
II. OPERATIONAL PRINCIPLE OF THE
PROPOSED INVERTER
Figure 1 shows the proposed structure single phase MLI
inverter. It consists of ‘n’ cells of switch circuits. For cells
from ‘1’ to (n-1), each k-cell is composed of one dc
voltage source and two switches (
) one switch ( )
is connected in series with a dc voltage source and the
other switch ( ) is connected in parallel with both the dc
voltage source and the series switch. Based on this
configuration, each cell can generate two states (0V) and
the dc voltage source associated with the considered cell.
Cell ‘n’ is composed of only the dc source voltage
resulting in generating only one state (Vn). As a result, the
dc link voltage
has (n-1) states, they are
(
), as shown in Fig. 2. Figure
Compared to the conventional topologies without affecting
the inverter performances. This is due to that; the zero
voltage can be generated using the idea of the upper or
lower H-bridge inverter to generate this state. The pulse
width modulation (PWM) control algorithm can be
applied, also, for this topology. The PWM control
algorithm, which adopted in this paper, consists of one
modulation signal with amplitude ( ) and n (number of dc
link cell) carriers with same amplitude ( ) Each carrier is
shifted with the carrier amplitude ( ) from the former one.
The amplitude ( ) can be changed from 0 to n*
according to changing modulation index from 0 to 1.
III. SINGLE-PHASE FIVE-LEVEL PWM INVERTER
In order to generate five levels, the number of the
required cascaded cell is n = 2. One cell uses two switches
with the dc source while the other cell is only the dc source
as shown in Fig. 3. Assume that the dc voltage sources are
equal; = =
The dc link bus voltage
will have
two states,
or
and the load output voltage will have
five states
,0,- . The zero state can be
generated either by switching the upper switches together
or the lower switches together. The other four states can be
Figure3. Proposed Single-Phase Five-Level Inverter
Configuration.
Figure1. Structure of the Proposed Cascaded dc Link
MLI.
Figure2. Typical Output Waveform of
.
Figure 4: PWM Switching Strategy.
International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.02, February-2014, Pages:0285-0291
A Single-Phase Five-Level PWM Inverter for Grid Connection with Less Number of Power Components
generated from the dc bus voltage
based on
folded cascade unit operation. The operation of the singlephase five-level inverter, employing PWM, can be divided
into 10 switching states based on the direction of the output
current as given by table I. The signal generation
waveforms are generated using one modulating signal and
two carriers. The amplitude of the modulating signal is ( )
and the amplitude of each carrier is ( ) In addition, each
carrier is shifted with the carrier amplitude ( ) from the
former one, as shown in Fig. 4.
TABLE I
Operational States According To the Switch on
Conditions and the Direction of The Load Current
Switching The
The Direction ON State
States
Output of the Output
Switches
Voltage Current
1
Vdc
positive
Q1,Q2 and S11
2
Vdc
negative
D1,D2 and S11
3
2Vdc
positive
Q1,Q2 and S12
4
2Vdc
negative
D1,D2 and S12
5
0
positive
Q1,D3 or Q2,D4
6
0
negative
D1,Q3 or D2,Q4
7
-2Vdc
positive
D3, D4 and S12
8
-2Vdc
negative
Q3,Q4,S12
9
-Vdc
positive
D3,D4 and S11
10
-Vdc
negative
Q3,Q4 and S11
inverter. The distribution of the harmonic components in
output voltage is similar to that of the conventional inverter
having the values of two times the modulation index. The
mentioned above is the first operational mode. On the other
hand, if the required output voltage is increased beyond the
modulation index 0.5, the output will result from
comparing the upper carrier signal with the same reference
signal. Therefore, the second level of the output voltage
will be generated and it will be the second mode.
According to the amplitude of the voltage reference, the
operational interval of each mode varies within a certain
period. The modes are determined as the phase angle
depends on the modulation index.
Mode A: 0 < wt
, 2 < wt
Mode B:
1 < wt
Mode C:
< wt
2
3,
4 < wt
Mode D: 3 < wt
The modulation index M1 of the proposed five-level
PWM inverter is defined as follows
MI =
(1)
Where:
The peak value of the modulating (sinusoidal) signal,
i.e. the voltage reference (
IV. SWITCHING ALGORITHM FOR THE
PROPOSED INVERTER USING PWM
The switching patterns employed in the proposed inverter
are illustrated in Fig.5. The output voltage levels,
according to the switch ON/OFF conditions, are shown in
Table II. In this paper, the switching strategy used to
generate the gate signals is accomplished by comparing the
reference signal, which is rectified sinusoidal, with two
triangular carrier waveforms having the same frequency
and phase angle, but with different offset voltages. When
the lower carrier signal is compared with the reference
signal, the first level of output voltage will be generated.
This means that the modulation index (MI) is less than or
equal 0.5 (50%). The behavior of proposed inverter is
similar to the conventional full–bridge three-level PWM
2
).
The peak–to–peak value
of the carrier (triangular).
Figure 5. Switching Patterns of the Proposed Inverter
International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.02, February-2014, Pages:0285-0291
K.SRIHARIBABU, CH.SRINIVASULU REDDY
Also, the frequency ratio
where:
is defined as follows:
=
The frequency of the carrier (triangular)
signal.
The frequency of the modulating (sinusoidal)
signal.When the modulation index is less than 0.5, the
phase angle displacement is equal to: 1= 2 =
3= 4
=
And when the modulation index is greater than 0.5,
the phase angle displacement is 1=
2=
( )
3= + 1
4=
- 1
The switching Patterns of the proposed inverter is
illustrated in Fig.5. In one period, switches
and
operate at the fundamental frequency (i.e., 50 Hz). The
switch
will be completely switched at the carrier
and
TABLEII.
Output Voltage According To the Switch On/Off
Conditions
Switching State
Q1
Q2
Q3
Q4
S11
S12
ON
ON
OFF
OFF
OFF
ON
+Vdc
ON
ON
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
OFF
0
-Vdc
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
ON
ON
ON
OFF
-2Vdc
OFF
OFF
ON
ON
OFF
ON
Vab
+2Vdc
- 1
signal frequency, whereas
performed. The output voltage produced by comparing the
reference signal and two carrier waves can be expressed as:
( )=
+
+
sin
)
(3)
will be switched in
both low and high switching frequency. The switch
is
switching at high frequency in a certain time of the period
and off elsewhere. The output voltage according to the
switch ON/OFF conditions is shown in Table II. As shown
in Fig. 5, the control signals are generated by the signals
and , coming from the comparators, which compare
the respective carrier signals with the voltage reference
(
). The main six periods P1, P2, P3, P4, P5 and P6 can
be calculated from the intersection of the reference
waveform with the carrier signals. Then switches signals
- ,
can be formulated based on P1, P2, P3,
P4, P5 and P6 by the phase angle displacement as given by
equation (6). Figure 6 describes a simplified description for
generating the control signals of switches.
- ,
The switching functions of proposed inverter are then
given by the logical (AND, OR, NOT) gates as follows:
=
+
+
+
=((
+
).
=
+
=(((
=(
If there are ‘P’ pulses per a quarter periods and it is an
odd number, the coefficients
and
will be zero, where
‘k’is an even number. Therefore, equation can be rewritten
as follows:
( )=
cos k
+
=((
) + ((
)) + ((
+
).
+
)
).
)
+
+
+
).
)+
).
+
)).
)| +((
+
Figure6. Simplified Descriptions for Generating the
Control Signals of the Inverter Switches.
).
)
=-
sin(k
)] (4)
(2)
V. HARMONIC ANALYSIS
The harmonic components in output voltage of the
proposed inverter are calculated as follows. From the two
carrier waves and output voltage in Figure5, the Analysis
of harmonic components in the proposed inverter can be
Where, ‘m’ is a pulse number. The Fourier series
coefficients of the conventional Single-phase full-bridge
inverter by sinusoidal PWM are given as:
=
International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.02, February-2014, Pages:0285-0291
sin(k
)]
(5)
A Single-Phase Five-Level PWM Inverter for Grid Connection with Less Number of Power Components
VI. RESULTS AND DISCUSSION
The feedback controller used in this application utilizes
the PI algorithm as shown in Fig.7. The grid current
and
always ON and
grid voltage
MI is less s than √2
are detected by sensors for the controller to
estimate the reference grid current
. The reference
amplitude is assumed constant and it phase angle is
obtained from grid voltage waveform to achieve unity
power factor. The instantaneous current e error is fed to a
PI controller. The resulting error signal (u) which forms
is compared with the two triangular carrier signals to
produce PWM signals for the switches. A FPGA kit of
XC3S400 is used as a controller in the laboratory
prototype. Proposed topology has been simulated using
PSIM software to verify the performance of the proposed
configuration. A two cells (n = 2) with h five-level output
voltage waveform has been chosen and simulated.
However the topology can be extended to ‘n’ cells. A
closed loop control for grid connection with wide range of
modulation index has been simulated at 10 kHz switching
frequency. Two identical power supplies of 20 V ea ach
have been used for the dc bus (>√2 ; in this case,
is
30 V RMS) in order to inject current into the grid. The MI
will determine the shape of the inverter output voltage e
and the grid current . Figure 8 (a), (b), and (c) shows
the inverter output voltage
and the grid current
at
MI equal to 0.4, 0.8, and 1.2 respectively. When the m
is always OFF) and the upper capacitor
only is used to feed the load and generate
figure 8(a). It can be noted here that
. As shown in
at 0.4 value of
. This means that the current will be
injected from the grid into the inverter so this condition
must be avoided to protect the inverter from damage. In
case of over modulation index, at MI =1.2, the reference
signal exceed the maximum amplitude of both carrier
signals. This will cause
to have a flat portion at the peak
of the waveform m, so it will not be pure sinusoidal
waveform. Whereas when the modulation index is larger
than 0.5 (1/n) and less than 1.0, the lower capacitor will
share the upper capacitor r in generating
resulting in
five-level inverter output voltage.
TABLE III
Current and Voltage rating for Inverter Switches
MAX current Settings
All switches
%(Iswitch/Iload)max=100
Max voltage ratings
S11,s12
Q1,Q2,Q3,Q4
%Vswitch max/Vdc)=1/n=0.5
%(Vswitch max/Vdc)=1
TABLEIV
Component compression for the Proposed Inverter and
Others
1st[8]
2nd[10]
proposed
Main
Switches
Main
Diodes
m
m+3
m+1
(m-1)*2
0
0
TABLE V
Component Comparison for Producing A5-Level
Output Voltage
1st[8]
2nd[10]
proposed
5
8
6
Main
Switches
4
0
0
Main
Diodes
Figure7.Five-Level
Algorithm
Inverter
with
PI
Controller
modulation index is less than or equal 0.5 (1/n), the
behavior of the proposed inverter will be similar to the
conventional full bridge three level PWM inverter. In this
case the lower capacitor bank is always disconnected ( is
So, to optimize the power transferred from dc link to the
grid, it is recommended to operate at 0.5≤ MI ≤ 1.0 as
shown from the inverter output t voltage and grid current in
Fig.8(b). It is clear that the grid current is almost a pure
sinusoidal waveform and thus s the THD can be reduced
drastically. To validate the proposed inverter, an
experimental prototype of the proposed five experimentally
level inverter has been built, carried out, and compared
with the simulation results. Fig. 9 shows the system setup
in laboratory. The inverter circuit t has been built using
International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.02, February-2014, Pages:0285-0291
K.SRIHARIBABU, CH.SRINIVASULU REDDY
power MOSFET as switches. The u used switching
frequency is 10 kHz. The switching signals are generated
using an FPGA of type XC3S400 as a controller. Two
identical dc power supplies of 20 V each were used for the
dc bus. The proposed inverter system is tested
experimentally using closed loop condition f for grid
connection with PI current controller, which is
implemented into FPGA XC3S400 and with L filter equal
to 3.3mH. The output inverter voltage
and g grid
current have been measured for two values of MI greater
than 0.5 and less than 0.5 as shown in Fig.10(a) & (b)
respectively. Once more for MI less than 0.5 the e behavior
of the five-level inverter will be same as the e conventional
single-phase three-level inverter. The grid voltage and
current for MI greater than 0.5 are shown in Fig. 11.
It is clear that the proposed system can inject active
power into the grid. Figure 12 shows the gate signals of
switches for MI greater than 0.5. It can be noted d that
some switches operate at line frequency and others s
operate at the switching frequency. Switch voltage and d
current ratings have been measured as shown in table III I.
It is clear that all switches carry load current and thus their
current ratings depends on it. The H-bridge inverter
switches have higher voltage ratings compared to the cell
switches; they have the cell dc voltage as a maximum
voltage rating. While the cell switches have equal voltage
blocking capability inversely proportional with the number
of cell ‘n’.
(a)
(c)
Figure 9: Prototype of the Proposed Five-Level PWM
Inverter by comparing the prop posed inverter with
three conventional single phase inverter topologies.
VI. CONCLUSION
This paper has presented a new single-phase five-level
PWM inverter with grid connection control. The propose
control technique for PWM switching and for the grid
injected current control has been presented. A digital PI
current control algorithm is implemented in FPGA
XC3S400 to optimize the performance of the proposed
inverter. The major benefits of the proposed inverter are
summarized as follow:
 It has less number of power elements.
 Some switches operate at fundament load frequency
and others operate at carrier frequency.
 Smaller filter size, less circuit layout complexity and
high efficiency can be achieved. Both the grid voltage
and the grid current are in phase, so the system
operates at unity power factor, and hence inject active
power to the grid. Simulation and experimental results
prove that the proposed single-phase multilevel
inverter has the capability of grid connection with high
efficiency as compared with conventional type.
VII. ACKNOWLEDGMENT
This work is sponsored by Egyptian Science and
Technology Development Funds (STDF) under STDF
project # 658. Any opinions, findings, and conclusions or
recommendations expressed in this material are those of
the author(s) and do not necessarily reflect the views of the
funding agencies.
VIII. REFERENCES
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[2] Siriroj Sirisukprasert, Jih-Sheng Lai, and Tian-Hua Liu,
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International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.02, February-2014, Pages:0285-0291
A Single-Phase Five-Level PWM Inverter for Grid Connection with Less Number of Power Components
Transactions on Industrial on Electronics, Vol. 49, Issue 4,
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Author’s Profile:
Kokolu Sriharibabu is PG Scholar
(Power Electronics during 2011-2013
in PBRVITS, Kavali, Andhra Pradesh,
India.
Ch.Srinivasulu Reddy, has received
his B.Tech in Electrical and Electronics
engineering and M.Tech degree in
Electrical power Engineering from
JNTU Hyderabad.He is dedicated to
teaching field from the last 10 years.
His research areas Renewable Energy
Sources, Power quality improvement. At present he is
working as HOD of EEE Department PBR Visvodaya
Institute of Technology & Science, Kavali, Andhra
Pradesh, India.
[7] José Rodríguez, Jih-Sheng Lai, and Fang Zheng Peng,
"Multilevel inverters: a survey of topologies, controls, and
applications", IEEE Transactions on Industrial Electronics,
Vol. 49, Issue 4, pp. 724- 738, August 2002.
[8] Sung-Jun, Park,Feel-Soon Kang, Man Hyung Lee, and
Cheul-U Kim, "A New Single-Phase Five-Level PWM
Inverter Employing a Deadbeat Control Scheme", IEEE
Transactions on power electronics, Vol. 18, No. 3, May
2003, pp: 831-843
[9] Agelidis, V. G., Baker, D. M., Lawrance, W. B.,
andNayar, C. V.,“A multilevel PWM inverter topology for
photovoltaic applications,” Proceedings of the IEEE
International symposium on Industrial Electronics, Vol. 2,
pp. 589-594, July 1997, Portugal, Guimaraes.
[10] Gui-Jia Su, “Multilevel DC-Link Inverter”, IEEE
Transactions on Industry Applications, Vol. 41, No. 3,
May/June 2005, pp. 848-854.
International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.02, February-2014, Pages:0285-0291