New multilevel inverter topology with minimum
number of switches
Rokan Ali Ahmed
Department of Electrical Engineering
University of Malaya
50603 Kuala Lumpur, Malaysia
E-mail: Rokan_L4@yahoo.com
Hew Wooi Ping
Department of Electrical Engineering
University of Malaya,
50603 Kuala Lumpur, Malaysia
E-mail: wphew@um.edu.my
S. Mekhilef
Department of Electrical Engineering
University of Malaya,
50603 Kuala Lumpur, Malaysia
E-mail: saad@ um.edu.my
to clamp the voltage levels.[10] H-bridge inverters have
isolation transformers to isolate the voltage source but they
do not need either clamping diode or flying capacitor
inverters. Also, some soft-switching methods can be
implemented for different multilevel inverters to reduce the
switching losses and to increase efficiency. Recently, several
multilevel inverter topologies have been developed [11],
[12],[13], [14].
Abstract—This paper presents two types of multilevel
inverters, known as symmetrical and asymmetrical multilevel
inverter. Both types are very effective and efficient for
improving the quality of the inverter output voltage. Firstly, we
describe briefly the structural parts of the inverter then
switching strategy and operational principles of the proposed
inverter are explained and operational topologies are given.
The proposed topology reduces the number of switches, losses,
installation area and converter cost. Finally, the simulation
results are provided to validate the proposed theory.
The disadvantages of multilevel configurations over the
two-level inverter configuration are the increase in the
number of power devices required and the circuit
complexity, which necessitates complex control schemes that
add to the cost and reduces the reliability of the converter.
This may lead the overall system to be more complex. There
for , in practical implementation, reducing the number of
switches and gate driver circuits is very important.
Keywords—Asymmetrical multilevel Inverter, Bidirectional
switch, Cascade Multilevel Inverter (CMLI), Total Harmonic
Distortion (THD).
I. INTRODUCTION
Power electronic inverters are becoming popular for
various industrial drives applications. In recent years,
inverters have even become a necessity for many
implementations such as motor controlling and power
systems [1],[2]. The concept of utilizing multiple small
voltage levels to perform power conversion was patented by
an MIT researcher over twenty years ago[3]. The multi-level
inverter system is very promising in AC drives, when both
reduced harmonic contents and high power are required
[4],[5]. Multilevel inverters have been mainly used in
medium or high power system applications, such as static
reactive power compensation and adjustable-speed drives
[6],[7]. A multilevel inverter not only achieves high power
ratings, but also enables the use of renewable energy sources.
Renewable energy sources such as photovoltaic, wind, and
fuel cells can be easily interfaced to a multilevel inverter
system for a high power application [8].
New topologies of symmetrical and asymmetrical
multilevel inverters been investigated in this Paper. Which is
generally for high number of steps associated with a low
number of switches and gate driver circuits for switches and
for generating all levels at the output. Finally, simulation
results verify the validity of the proposed multilevel inverter.
II. CASCADE MULTILEVEL INVERTER
Cascade Multilevel Inverter (CMLI) is one of the most
important topologies in the family of multilevel and multipulse inverters [15]. It is built to synthesize a desired AC
voltage from several levels of DC voltages. The DC levels
are considered to be identical since all of them are either
batteries, solar cells, etc. [16],[17]. It requires least number
of components when compared to diode-clamped and flying
capacitors type multilevel inverters and no specially designed
transformer is needed as compared to multi pulse inverter
[17],[18]. A cascaded multi-level inverter consists of a
number of H-bridge inverter units with separate dc source for
each unit and it is connected in cascade or series as shown in
Fig.1 [12]. Each H-bridge can produce three different voltage
levels: V , 0, and V by connecting the dc source to ac
output side by different combinations of the four switches S1,
S2, S3, and S4. The magnitude of the ac output phase voltage
is given by:
The concept of multilevel inverters was first introduced
in 1975. The term multilevel began with the three-level
inverter. Subsequently, several multilevel inverter topologies
have been developed [3], [9]. Up to now, several topologies
of multi-level inverter system have been introduced. The
main topologies used to generate a high voltage waveform
using low voltage devices are the series H-bridge design,
diode clamped inverter system and flying capacitor inverter
system. Each of these topologies has a different mechanism
for providing the voltage level.
Comparing with the other components, for instance, DClink capacitors having the same capacity per unit, diode
clamped inverter has the least number of capacitors among
the multi-level inverter system topologies but it requires
additional clamping diodes[4].The flying-capacitor topology
followed diode-clamped after few years. Instead of series
connected capacitors, this topology uses floating capacitors
(1)
For symmetric inverter all dc voltage sources in Fig. 1
equal to Vdc, the number of available voltage step levels is :
2
1
(2)
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size, cost, installation area and control complexity. To
provide a large number of output levels without increasing
the number of bridges, a new power circuit topology and a
suitable method to determine the dc voltage sources level for
symmetrical and asymmetrical multilevel inverter are
proposed in this paper.
Fig. 2 shows the proposed basic unit for a symmetrical
multilevel inverter. The output for 11-level topology is
shown in Fig. 3.
Fig. 1. Configuration of cascaded multilevel inverter
Where n represented the number of full-bridges and the
maximum output voltage (Vomax) of this n cascaded
multilevel inverter is:
Fig. 2. Suggested basic topology for a symmetrical inverter
(3)
For asymmetric cascaded multilevel inverter, DC voltage
sources of different cells are non-equal. Asymmetric inverter
provides an increased number of voltage levels for the same
cells number than its symmetric counterpart. If the DC
voltages of individual cells Fig.1 are selected according to a
geometric progression with a factor of two or three [10].For
n cascaded multilevel inverters, then the number of voltage
steps count is:
N
2
1 ifV
2
V
for j
1,2, … , n
(4)
N
3
ifV
3
V
for j
1,2, … , n
(5)
Fig. 3. Typical output waveform of 11-level
To increase the number of levels one power supply shall
be added with two switches only. This proposed method is
different from the method in [19] since it does not have any
bidirectional switch and different from the method in [10]
since it has less number of switches.
The maximum output voltages of these n cascaded
multilevel inverters are:
The effective number of output voltage steps (Nstep) in
symmetric multilevel inverter is:
V
V
(2
1)V
ifV
2
V
for j
1,2, … , n
(6)
V
ifV
3
V
for j
1,2, … , n
(7)
III.
2
1
(8)
Where n represents the number of dc voltage sources and
the maximum output voltage (Vomax) of this n cascaded
multilevel inverter is:
PROPOSED TOPOLOGY
In all well-known multilevel inverter topologies, the
required number of power devices depends on the output
voltage level. However, increasing the number of power
semiconductor switches also increases the inverter circuit
(9)
Vo can be increased by connecting the N basic circuit
given in Fig 2 in series as shown in Fig. 4.
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Contrary to method as in [20] by using this equation all
levels can be obtained without losing any level which
reduces THD at the output. The number of output voltage
levels in a cascaded multi-level inverter is then:
5
2
number
(11-a)
5
3
number
(11-b)
The maximum output voltage Vomax of this new topology is
(
V
)
(
number
)
number
(12-a)
(12-b)
The number of the basic element in Fig. 5 is connected in
series as shown in Fig 6 to increase the output voltage. The
resulting proposed asymmetrical inverter configuration can
generate a stepped voltage waveform without any loss at any
level.
Fig. 4. N basic unit connected in series .
Fig 5 shows the new basic element which used for this
implementation of single-stage asymmetrical inverter. The
circuit consists of k many dc voltage sources (cell) and
2(k-1) many bidirectional switches.
Fig. 6. Proposed asymmetric multilevel inverter based on N stages
IV. MODULATION TECHNIQUE FOR SWITCHES
The implementation of the various carrier PWM
techniques is possible for multi-level inverters. This paper
uses multi-level triangular waves generation as derived in
[21] [22]. It can be a useful solution for pulse generation for
this topology. This technique in [23] is called carrier
redistribution (CR) technique. This technique is derived from
the triangular carrier and has individually the lowest
switching frequency among the multi-level PWM methods
[24].
Fig. 5.. New basic element (one stage) of asymmetric multilevel inverter
with Kdc sources (cells).
This circuit is different from the method in [10] since it
has less number of switches and different from method [20]
in choosing the dc sources. DC sources should be chosen
according the equation below and arrangement to produces
output voltage without losing any level.
n
1
n
2
1
2
3,5, … ..
n
2
n
2
(10-a)
1
Fig. 7. Triangular comparison with sine wave for 7-level inverter.
(10-b)
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V. SIMULATION RESULTS
The waveforms given in Fig. 9,10 and 11 are the filter
input voltage, load voltage and load current, respectively.
THD values of these voltages and this current are 18.23, 0.88
and 0.88, respectively.
The simulation studies are carried out for two different
cases. The first case is the ordinary symmetrical multilevel
inverter. This case is studied to examine the characteristics of
the output voltage and output current.
The second case is ordinary asymmetrical multilevel
inverter. It is studied to examine the characteristics of the
output voltage and output current to compare with other
methods.
To compare the harmonic performance of the two
techniques several harmonic measurement methods are
possible. The total harmonic distortion (THD) is one of
these, which evaluates the quantity of harmonic contents in
the output waveform and is a popular performance index for
power converters.
Fig. 9. Simulated input voltage to filter Vin.
To validate the proposed multilevel inverter in the
generation of a desired output voltage waveform, a prototype
is simulated based on the proposed topology according to
that one shown in Fig. 2. The Matlab Simulink power
blockset software has been used for simulation. The
symmetrical multilevel shown in Fig. 8 is adjusted to
produce a 50-Hz, 7-level staircase waveform. Test has been
made on the used filter was L =0.5mH, C=10µf and the load
of 25Ω.
Fig. 10. Simulated output voltage (VL).
Table I shows the ON switches lookup table. Note that
there are different switching patterns for producing the zero
level, and in Table I, only one of them is shown. The main
idea in the control strategy is to deliver the load a voltage
that minimizes the error with respect to the reference voltage
This is achieved in this paper by using carrier redistribution
(CR) technique.
Fig. 11. Output current (IL).
To examine the performance of the proposed
asymmetrical multilevel inverter in the generation of a
desired output voltage waveform, a prototype is simulated
based on the proposed topology according to the one shown
in Fig. 5. The same software, filter, load and modulation are
used for simulation the symmetrical multilevel shown in
Fig. 12 .It is adjusted to produce a 50-Hz, 13-level staircase
waveform. Table II shows the ON switches look-up table.
The proposed multilevel inverter requires bidirectional
switches with the capability of blocking voltage and
conducting current in both directions.
Fig. 8. 7-Level multilevel inverter (according to first method
Table I
N switches look-up table.
Fig. 12. 13-Level multilevel inverter (according to first method
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inverter generates near-sinusoidal output voltage and as a
result, very has low harmonic content.
Table II
ON switches look-up table.
A new algorithm for determination of dc voltage source
magnitudes has been presented in asymmetrical multilevel
inverter, too. This technique provides more flexibility to
designers and can generate more voltage levels without
losing any level which worsens THD characteristics. The
possibility of extension or series connection of this basic nit
in two topologies has been studied. Through simulations it is
seen that proposed inverter topology generates a high-quality
output voltage waveform and harmonic components of
output voltage and current are low.
The waveforms given in Fig. 13, 14 and 15 are the filter
input voltage, load voltage and load current, respectively.
THD values of these voltages and this current are 9.19, 0.46
and 0.46, respectively.
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Fig. 13. Simulated input voltage to filter Vin.
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Fig. 14. Simulated output voltage (VL).
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Fig. 15. Output current (IL).
VI. CONCLUSION
[14]
A novel symmetrical multilevel inverter topology has
been proposed in this paper. The most important feature of
the system is being convenient for expanding and increasing
the number of output levels simply without using any
bidirectional switches. This method results in the reduction
of the number of switches, losses and cost of the converter.
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