International Journal for Research and Development in Engineering (IJRDE)
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ISSN: 2279-0500
Special Issue: pp- 289-296
Analysis of Various Sinusoidal Pulse Width Modulation Techniques
for a Five Level H6 Bridge Inverter
N.Tejesvi1, N. Sujitha2, R. Hemantha kumar3 and Dr.M. Sasikumar4
1,2,3
PG Scholar, 4Professor,Head of the Department EEE
Jeppiaar Engineering College, Chennai.
Abstract
This paper deals with the novel five level H6 bridge inverter with
various sinusoidal pulse width modulation techniques. The
proposed inverter includes the full bridge topology with two
additional power switches and two diodes connected to the
midpoint of the DC link. The midpoint voltage is balanced using
the various sinusoidal pulse width modulation techniques. Thus
the two added levels are obtained by the discharge of the two
capacitors from the DC link. Simulation study of the inverter
employing alternative phase opposition disposition and third
harmonic injection sinusoidal pulse width modulation technique
has been done using MATLAB/SIMULINK .
Index terms—Five level H6 bridge inverter, alternative phase
opposition disposition (APOD), third harmonic injection.
I.
INTRODUCTION
This paper concerns about the implementation of multilevel
topologies for single phase converters. By the use of these
multilevel inverter harmonic level of the system can be
reduced to a considerable amount, as a result of which efficient
output can be derived with the help of smaller and cheaper
filters itself[1][2]. This also helps in the improvement of
output waveform and reduction of electromagnetic interference
(EMI) [3].
The basic idea of the multilevel inverter is that to provide
the intermediate voltage levels between the reference potential
and the dc link voltage [4]. In half bridge neutral point
clamped inverter the additional levels are provided by
clamping the series of dc link capacitors or the flying
capacitors and the balancing system is required such as an
external circuit [5] or modified PWM strategies [6],[7].
Cascaded full bridge inverter needs several dc sources such
as PV strings [8]. Using the transformers, inverter can also use
the single dc supply [9]. Cascaded full bridge inverter employs
different PWM techniques [10] such as APOD, SPWM, SVM
[11], [12]
In hybrid topologies, a novel NPC full bridge is presented
[13] with NPC three level leg (four switches) and the other leg
with two devices switches at low frequency. A similar
approach was presented in [14], where four low frequency
devices (instead of the two employed in [13]) were employed
in a full-bridge configuration.
A different topology was proposed in [15] where only six
devices are needed and the positive rail of full bridge can be
connected to dc link or the mid point of dc link capacitors thus
the maximum number of conducting devices is three.
This paper proposes a five level output by the help of a full
bridge inverter along with two diodes and two power switches
connected to the midpoint of the DC link. The midpoint
voltage control and unity power factor of the circuit is obtained
by implementing various sinusoidal pulse width modulation
techniques like alternative phase opposition disposition
(APOD) and third harmonic injection. The most efficient
method is derived out from the analysis of above mentioned
techniques.
II. FIVE LEVEL H6 BRIDGE INVERTER
This H6 bridge inverter is mainly designed and
implemented inorder to maintain constant output voltage
incase of transformerless inverter for photovoltaic applications.
The output voltage of the five level inverter can be written as
Vout = mVdc
Various pulse width modulation stratagies are applied
according to the modulation index value. Four zones of
operation are identified in this circuit. The output voltage of
the power converter differs for each mode of operation.
A. Circuit Diagram
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International Journal for Research and Development in Engineering (IJRDE)
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ISSN: 2279-0500
Special Issue: pp- 289-296
During Mode2 operation transistors T1, T4 and T5 will be
in ON condition. During this mode of operation the output
voltage varies from +Vdc to +VMP. Vdc is obtained during the
active phase whereas +VMP is obtained during the freewheeling
phase. The current flow of this mode of operation is as shown
in figure 3.
Fig. 1. Circuit diagram of Five level Inverter
The circuit consist of a voltage source Vdc, two capacitors,
power switches, diodes and four transistors with a R load. The
midpoint voltage control between these capacitors will be
achieved with the help of PWM strategies. The output voltage
level +VMP is obtained by the discharge of the lower side
capacitor CLS and the –VMP is obtained by the discharge of the
higher side capacitor CHS. Transistors T1, T4 are in ON
condition during the positive semiperiod whereas the
transistors T3, T2 are in ON condition during the negative
semiperiod.
B. Modes Of Operation
Mode 1:
During the operation of Mode1 transistors T1, T4 and T6
will be in ON condition whereas the transistors T2, T3 and T5
will be in off condition. The turn ON of transistor T6 varies the
output voltage value between +VMP and 0V. The output
voltage +VMP is obtained with the help of the lower side
capacitor CLS and the NULL voltage is obtained during the
freewheeling operation of diodes D1 and D2. The current flow
for the Mode 1 operation is as shown in figure 2.
Fig. 3. Five-level PWM strategy for Zone 2 (a) Active phase (b)
Freewheeling phase.
Mode 3 and Mode 4:
The operation of mode 3 and mode 4 are similar to that of
mode 1 and mode 2 except that they work for the negative
semiperiod. Here the transistors T2 and T3 will be in ON
condition for both modes of operation whereas T6 will be ON
during mode 3 and T5 will be ON during mode 4 operation.
C. Midpoint Voltage Control
During symmetrical conditions midpoint voltage drift does
not arise but during asymmetrical conditions the midpoint
voltage drift arises. The lower side and the higher side
capacitors are used to balance this drift. The midpoint voltage
control is explained with the help of the figure 4. The HS
capacitor and the LS capacitor helps in providing constant
output voltage VMP to the full bridge converter. The output
voltage level +VMP is obtained by the discharge of CLS and –
VMP is obtained by the discharge of the higher side capacitor
CHS.THE two configurations shown in figure 4 helps out to
balance the charge of the two capacitors. Figure 5 is taken for
the analysis of midpoint voltage control. Here Vdc is kept
constant and the capacitors are considered to be equal.
That is
CHS=CLS=C
Fig. 2. Five level P W M strategy for mode 1. (a) Active phase.
(b) Freewheeling phase.
Mode 2:
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ISSN: 2279-0500
Special Issue: pppp 289-296
For a m-level
level inverter the APOD technique requires m
m-1
carrier signals which has to be phase disposed from each other
by an angle of 180 degree. Four carrier signals are required for
bipolar mode of operation, two signals which are phase
displaced by 180 degree are used for upper half and two for the
lower half. The unipolar carrier signal arrangement for
alternative phase opposition disposition technique is given in
figure 6.
Fig. 4. T5 and T6 configurations providing the same voltage
v
VMP to
the full- bridge rails. In (a), the HS capacitor is discha
discharging, and in (b),
the LS capacitor is discharging.
Fig. 6. APOD signal
Fig. 5. DC capacitor circuit employed for the analytical analysis of
the MVC.
From figure 5 it is evident that
D(VMP/dt) = -IMP/2C
Each carrier wave generated have the same frequency and
amplitude.
e. Based on the inverter level the amplitude of the
modulation signal is modified.
B. Third Harmonic Injection
The third harmonic injection signal arrangement
arr
is as
shown in figure 7.
This means that IMP affects the midpoint
int voltage. While
considering mode1 operation during the active phase the
midpoint current IMP will be equal to that of the load current
while the load current will be zero during the freewheeling
operation. Now considering the mode 2 operation, the
midpoint current IMP is zero during the active phase while the
midpoint current IMP equals the load current during the
freewheeling operation. Thus the midpoint voltage control is
achieved.
III. SINUSOIDAL PULSE WIDTH MODULATION
TECHNIQUES
The comparison of various sinusoidal pulse width
modulation techniques like
ike alternative phase opposition
disposition method (APOD) and third harmonic injection are
explained below.
A. Alternative phase opposition disposition
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ISSN: 2279-0500
Special Issue: pppp 289-296
sinusoidal signals must have the same fundamental frequenc
frequency
f0 and amplitude Am. The pulses are generated based on the
intersection between the sinusoidal signals and the carrier
signal. The single carrier sinusoidal pulse width modulation
technique arrangement is shown in figure 88.
Fig 8 Single carrier SPWM signal
SIMULATION RESULTS
The five level H6 bridge inverter operation and its various
results at R load are studied and discussed below. The simulink
representation of APOD pulse generation is shown in Figure.9
Fig. 7. Third harmonic injection signal arrangement
Sinusoidal PWM technique is considered to be the simplest
modulation scheme but the drawback is that it cannot
completely utilize the Dc supply voltage. To overcome this
problem the Third Harmonic Injection pulse width modulation
technique is introduced. Byy using this method the inverter
performance can be improved. Here in this method a triple
frequency term
y = sinθ+Asin3θ
is added with the fundamental component. From the figure it is
evident that due to the third harmonic injection to the peak
magnitude of the modulation wave, the effect of reducing the
peak value of output waveform without changing the
fundamental amplitude is achieved. By this method the
amplitude of the modulating waveform can be increased, as a
result of which the full output voltage can be utilized. There
will be 15.5% increase in the amplitude of the fundamental
phase voltage due to the third harmonic injection.
n.
C. Single Carrier Sinusoidal Pulse Width Modulation
Technique
This technique is implemented when there is usage of multiple
sinusoidal modulating signals and a single carrier signal. These
Methods Enriching Power and Energy Development ((MEPED) 2014
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ISSN: 2279-0500
Special Issue: pp- 289-296
(b)
Fig. 9: APOD signal (a) simulink representation (b) generated pulses.
(b)
The simulink representation of third harmonic injection
strategy is shown in figure 10 and that of SCSPWM is shown
in figure 11.
Fig. 10. Third Harmonic injection (a) simulink representation
(b) generated pulses
(a)
(a)
(b)
Fig. 11. Single Carrier Sinusoidal Pulse Width Modulation Technique
(a) simulink representation (b) generated pulses
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Block diagram representation of five level H6 bridge inverter
is shown in figure 12.
(a)
Fig 12. Simulink for five level H6 bridge inverter
The switching sequence waveform of each switch T1 through
T6 using APOD is shown in Figure 13(a) the switching
sequence waveform using third harmonic injection is shown in
figure 13(b) and that of SCSPWM is shown in figure 13(c).
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International Journal for Research and Development in Engineering (IJRDE)
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ISSN: 2279-0500
Special Issue: pp- 289-296
(b)
Fig 14. Output voltage waveform of five level H6 bridge inverter
The total harmonic distortion THD using APOD for the
output voltage is about 15.52% and it is 1.23% for third
harmonic injection. The harmonic spectrum in the modulation
region M=0.95 is shown in figure 15.
(a)
(c)
Fig .13. Switching pulses (a) using APOD (b) using third harmonic
injection (c) using SCSPWM technique.
The input voltage applied is 400V and the load resistance is
10ohms. The obtained output voltage of the proposed five
level H6 bridge inverter is shown in figure 14.
(b)
(C)
Fig 15.Harmonic spectrum of output voltage (a) using APOD (b)
using third harmonic injection (c) using SCSPWM.
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Special Issue: pp- 289-296
IV. CONCLUSION
The five level H6 bridge inverter is simulated in
MATLAB- Simulink environment using three different pulse
width modulation techniques such as alternative phase
opposition disposition, third harmonic injection and single
carrier sinusoidal PWM techniques. The effective midpoint
voltage control (MVC) provides two more voltage levels in the
output which decreases the switching losses and EMI. The
harmonic performance of the proposed inverter is analyzed and
it seems to be effective with the single carrier pulse width
modulation technique. This topology can be varied to allow the
four quadrant operations.
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