BenADDA-V4
High-Performance Data Acquisition & Processing
The BenADDA-V4™ integrates multi-channel, high speed
analog I/O with the extreme processing of an FPGA.
The DIME-II™ module combines a Xilinx® Virtex-4™ FPGA
with two Analog Device 14-bit, 105 MSPS ADCs and two
14-bit 160MSPS DACs. The result is a high performance
data acquisition and processing platform in a proven
COTS solution.
When sampling a 40.2 MHz signal at 105 MSPS, each
AD6645 simultaneously achieves up to:
•
12.2 Effective Number Of Bits, ENOB
•
75.3 dB signal-to-noise ratio, SNR
•
65 MHz analog bandwidth (filter OFF)
The BenADDA-V4 is the ideal solution for easy, low risk
system integration or in-field deployment.
14-Bit Dual ADC & DAC Data Acquisition Module
Key features
Benefits
• DIME-II expansion module
• High-speed analog capture coupled to Xilinx FPGA
• Dual 14-bit, 105 MSPS analog capture channels
• Dual 14-bit,160 MSPS analog output channels
• External clock input and onboard high accuracy fixed
oscillator clocking options
• Onboard Xilinx Virtex-4 user FPGA
• 16 MB DDR-II SRAM – 2 independent banks
Easy to implement analog and processing capability
• Commercial-off-the-shelf (COTS) hardware
Shorten time to market and reduce risk
• Compatible with multiple FPGA design flows
Select the appropriate design flow for the application
• Compatible with Nallatech PCI Express, PCI-X, PCI,
PCI-104 and VME54-VXS COTS motherboards
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The Leader in FPGA
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Accelerated Computing
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www.Nallatech.com / contact@nallatech.com
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BenADDA-V4
Technical specification
User FPGA
DIME-II interconnect performance
• Xilinx Virtex-4 FPGA
• Choice of: XC4VSX55-11 or
XC4VLX160-11
• Adjacent bus: Up to 200 MHz
• Local bus: Up to 66 MHz
• P-Link buses: Up to 200 MHz
FPGA key features
SRAM memory
SX55 LX160
55,296 152,064
Logic
Cells
DSP
512
Slices
Kb BRAM 5,760
DAC
AD9772
• 16 MB DDR-II SRAM
• DDR-II SRAM controller IP core
included
• 2 independent 8 MB banks
• 32-bit data bus per bank
• Operating frequency: 200 MHz
• Max. data rate: 400 Mbit/s (DDR)
• Max. bandwidth per bank: 1.6 GB/s
• Capable of buffering two ADC
channels
96
5,184
Full FPGA specification from
www.xilinx.com
LOCAL
OSC
FPGA clocking
• Three programmable clock domains
driven from DIME-II motherboard
Electrical
P LINK 0 (12 BITS)
*P LINK 3 (12 BITS)
P LINK 1 (12 BITS)*
*P LINK 2 (12 BITS)
LOCAL BUS (64 BITS)**
P LINK 5 (12 BITS)
P LINK 7 (12 BITS)
P LINK 4 (12 BITS)*
*P LINK 6 (12 BITS)
ADJ IN (80 BITS)
ADJ OUT (80 BITS)
MOTHERBOARD DIME-II
INTERCONNECT FABRIC
• Two analog input channels
• 14-bit, 105 MSPS Analog Devices
AD6645 ADCs – www.analog.com
• Front end filter options
Anti-aliasing filter
No filter
• Two analog output channels
• 14-bit, 160 MSPS Analog Devices
AD9772 DACs – www.analog.com
• Analog clocking options:
• External clock input ability
• Onboard crystal oscillator – user
changeable
• Clock distribution FPGA to
select analog clock option
• Single-ended Input and Outputs
• MCX type connectors
• 5 MCX coaxial cables supplied
ADC
AD6645
MODULE CONNECTORS
Analog I/O
ADC
AD6645
XILINX VIRTEX-4
USER FPGA
MODULE CONNECTORS
• Embedded JTAG and SELECTMAP
programming through FUSE
software functions
DAC
AD9772
CLOCK
CONTROL
MOTHERBOARD DIME-II
INTERCONNECT FABRIC
FPGA programming
• Power consumption depends on
application
DDR-II SRAM
Application development software
• Supported in Nallatech DIMEtalk
software for FPGA communications
network design and implementation
• Supports multiple design flows
®
including VHDL, Verilog , System
®
Generator
• Compatible with all major synthesis
design flows
• Compatible with Xilinx ISE
Implementation software
Software
• Nallatech FUSE API for Windows
32-bit, Linux 32-bit and 64-bit
• Runtime FPGA programming,
hardware control, and application
communication
• FUSE includes applications and
development API for C/C++
Quality
• Manufactured to IPC610 Class III
(standard options)
• Designed and supplied to
ISO9001:2000 certification
• Not ROHS compliant
Corporate Offices
741 Flynn Road
Camarillo, CA 93012, USA
Tel: (805) 383-8997
Toll Free: 1-877-44-NALLA
Fax: (805) 384-4899
Functional diagram
1 Napier Park
Cumbernauld
G68 0BH, UK
Tel: +44 (0)1236 789567
Fax: +44 (0)1236 789599
DDR-II SRAM
*Not supported on XC4VSX55 **32 bits on XC4VSX55
All DIME-II buses are bi-directional. Where a bus name implies a direction
in/out, this is just a conceptual name and the bus can be used in either
direction. Single-ended LVTTL and Differential LVDS signalling are supported.
Cooling
Environmental
• FPGA active cooling fan or passive
heatsink provided for user FPGA
(specify when ordering)
• Passive heatsink requires adequate
forced-air cooling
•
•
•
•
Cooling: Air convection
Operating temperature: 0°C to 50°C
Storage temperature: -20°C to 80°C
Relative humidity: 45 to 95% (noncondensing)
Ordering and deliverables
Deliverables
Ordering
•
•
•
•
•
• Contact Nallatech for lead-time and
pricing information.
• Detailed datasheet available on
request
• Refer to DIME-II Product Ordering
Guide for product order codes
BenADDA-V4 module
Software and documentation CD
5 MCX-BNC coaxial cables
ADC FPGA IP Cores
30 days product maintenance
(technical support, support lounge
access)
Technical specifications (e.g. FPGA type,
size, external memory capacity etc.) can be
modified to meet the exact needs of
commercial customer applications as
off-the-shelf product available to the
general market.
Additional options
• DIMEtalk software
®
• FUSE Toolbox for MATLAB
www.Nallatech.com / contact@nallatech.com