IEEE PEDS 2011, Singapore, 5 - 8 December 2011
Design and Implementation of Digital Controller
using FPGA for 200-kHz PWM Inverter
Shinya Suzuki, Keiji Wada and Toshihisa Shimizu
Tokyo Metropolitan University, 1-1 Minami Osawa, Hachioji, Tokyo, JAPAN
Abstract—This paper presents design procedure of a 200 kHz
PWM inverter with a current controller. The switching devices
of the inverter consist of Si-MOSFETs and SiC-SBDs, and an
FPGA is used for digital control of output current waveforms.
The authors have developed an FPGA controller with high-speed
and synchronous AD converter. The processing time of FPGA can
be ignored because of less than 100 ns, and the time delay of an
AD converter could not also be taken into account. A laboratory
system rated at 200-kHz PWM inverter is confirmed that the
validity of the design procedure from the experimental results.
Finally, the experimental results of 10-kHz sinusoidal current
control will be shown.
IndexT erm — Current Control, FPGA, High-frequency, PWM
Inverter
I. Introduction
An inverter circuit is widely used for home appliances,
industry applications, and etc. General purpose inverters produce 50 Hz sinusoidal current waveforms for motor driven.
Recently, power devices for fast switching and low losses
are developed, and they are sold on the market. In addition,
SiC(Silicon Carbide) diode and MOSFET can be available
easily. As the results, switching frequency of an inverter can
be set to over 100 kHz[1], [2] using SiC devices. Moreover, a
high-speed digital controller using DSP and/or FPGA has also
been developed for power electronics circuits. For example,
Ref. [3] has presented a digital controller with high-speed
AD converter for a 1-MHz switching rectifier. In addition,
Ref. [4] has proposed a sampling method for an single-phase
PWM inverter, and Ref. [5] has also proposed a current
controller based on a multi-rate deadbeat control method.
These papers are used to FPGA (Field-Programmable Gate
Array) for current control of the PWM inverter.
The ultra-high-speed motor from 100,000 to 500,000-r/min
has been proposed for a micro-gas turbine, an automotive
supercharger [6]-[9] and hand tool applications. These highspeed motors need from 1- to 10-kHz sinusoidal current
waveforms, because a number of revolutions of the ac motors
are decided by frequency of current waveforms. However,
digital controllers of the inverter have been discussed for
grid-connected inverter[10] or motor-driven inverter[11], thus
the frequency bandwidth of the current control is set to less
than 500 Hz. Moreover a 400-Hz power converter system
is used for airplane and aerospace power supplies[12], [13].
On the other hand, Ref. [14] has proposed a high-frequency
bandwidth current controller using a linear amplifier. However,
there are no papers for a PWM inverter with the 10 kHz current
controller.
This paper presents a 200 kHz PWM inverter with a current
control for producing 10-kHz sinusoidal current waveform.
The switching devices of the inverter consist of Si-MOSFETs
and SiC-SBDs, and FPGA is used for the digital control. The
authors have developed FPGA controller with AD converters
and gate drive circuits for the 200-kHz switching PWM
inverter. The whole time delay of the experimental system can
be ignored because the sampling time of the AD converter is
larger than the delay time of the system. A design procedure of
the digital current controller is discussed in detail, and steadyand transient-state characteristics of the control system are also
described. The output current response can realize 5 µs by the
step response, and the current control of sinusoidal waveforms
is shown from the experimental results. A single-phase PWM
inverter is confirmed that the validity of the design procedure
from the experimental results.
II. System Configurations
A. Inverter Circuit
Fig. 1 shows circuit configuration of the single-phase PWM
inverter. Here, the internal resistor r means switching loss
of the PWM inverter, and LR load is connected in the ac
side of the inverter. The resistance r can be derived from the
steady-state error in the experimental results. The switching
frequency of the MOSFETs is set to 200-kHz, so the equivalent switching frequency of the single-phase inverter is 400
kHz. SiC-Diodes (DSiC ) are connected to the MOSFET in
parallel for significantly reducing a reverse-recovery current
and switching losses[15], and Si-Diodes (DSi ) are connected
to the MOSFETs in series for cancelling the body diode. Table
I shows voltage- and current-rating of power devices of the
inverter circuit. Fig. 2 shows circuit configuration of the singlephase PWM inverter with the control diagram, and Table II
shows the circuit parameters.
B. Digital Control using FPGA
The digital controller is consist of an FPGA with AD converters as shown in Fig. 3, and Table III shows the parameters
of the digital controller. The FPGA board has been developed
for power electronics research in our laboratory, and it has four
AD converters and two DA converters. The conversion time
of the AD converters is less than 300 ns because a parallel
type AD converter is used.
The sinusoidal reference signal i∗out from ROM data which
is also 12 bit vertical resolution. The proportional control and
generating the 200-kHz PWM signal can be done by the FPGA
978-1-4577-0001-9/11/$26.00 ©2011 IEEE
1031
DSi
TABLE II
Circuit Parameters of Inverter
DSi
DSiC
S1
S3
DSiC
DC Voltage VDC
Output Power P
Load Inductor L
Load Resistor R
Internal resistor r
Switching Frequency fS W
Dead Time
Sampling Frequency
L iout
r
VDC
DSi
DSiC
S2
Fig. 1.
vout
DSi
S4
R
DSiC
100 V
200 VA
254 µH
38.0 Ω
9.0 Ω
200 kHz
300 ns
400 kHz
Circuit configuration of the inverter circuit
TABLE I
Voltage and current rating of power devices
MOSFET S1 ∼ S4
Diode DSi
Diode DSiC
20N60C3(Infinion)
25CTQ035S
SDP06S60(Infinion)
600 V, 20 A
35 V, 15 A
600 V, 6 A
using VHDL (Very high-speed integrated circuit Hardware
Description Language), and the dead time is set to 300 ns.
Thus it takes 7 clocks from current detection to producing the
PWM signal with the dead time.
Fig. 3.
Picture of FPGA board
III. Time Delay of the Controller
A. Current Sensor and AD Converter
The DCCT (DC current transformer; LEM, LA-55P, 0-200
kHz) detects the output current waveform iout of the inverter.
The time delay of the DCCT can be ignored in this paper.
The sampling frequency of the AD converter should be
set to faster than that of conventional inverters, because the
switching frequency of the inverter is over 10 times as high
as that of conventional inverters. Hence, it is important to
consider the time delay in the interface circuit where it means
both the current sensor and AD converter. The AD converter is
LTC1412(parallel 12-bit, 40 MHz: Linear Technology) is used
to this experiment. The conversion time of the AD converter
takes 300 ns. The synchronous sampling method is applied to
the inverter, and the sampling frequency is set to double of the
r
L
iout
vout
VDC
R
AD converter
Dead
time
Fig. 2.
PWM
Proportional
control
Current
comparator
i∗out
Circuit configuration of the inverter circuit with current controller
switching frequency for single-phase PWM inverter. Because
it can improve the stability and frequency characteristics of
the current controller. Therefore, the sampling frequency can
be set to 400 kHz (sampling time T S : 2.5 µs).
B. Gate drive circuit
Fig. 4 shows a conventional gate drive circuit using photocoupler (TLP350: TOSHIBA) for driving a MOSFET. The
photocoupler which is generally used for an inverter circuit can drive MOSFET directly because it is consist of
an isolation- and amplification-function. Therefore it can be
used for a general-purpose inverter circuit, such as a 10-kHz
PWM inverter. Fig. 5 shows block diagram of the gate drive
circuit in this experimental system. The gate drive circuit uses
digital isolator (ADuM1100, 100 Mbps: Analog Devices) and
amplifier (MIC44F18) for isolation between the control- and
inverter-circuit.
Fig. 6 shows experimental results of the gate drive circuits
when the DC voltage VDC is set to 0 V, and the FPGA produces
pulse signal vFPGA of 167 ns pulse width, as shown in Fig.
6(a). Fig. 6(b) and (c) show experimental results of the gatesource voltage vGS of the MOSFET, respectively. When the
photocoupler is applied to the gate-drive circuit as shown in
Fig. 6(b), the propagation time delay is 250 ns which is 10%
time delay compared with the sampling time. So, it is difficult
to use the photocoupler for 200 kHz PWM inverter with the
current control. On the other hand, in the case of using the
digital isolator as shown in Fig. 6(c), the rise- and fall-time
of the gate-source voltage has some time delay. Moreover, the
1032
TABLE III
Circuit Parameters of FPGA board in Fig. 3
ALTERA CycloneII, 100 MHz
EPCS4
2 ch, 12 bit, 40 MHz
2 ch, 12 bit, 12.5 MHz
16 point
AC 100 V (5 V, 3.3 V, 1.2 V)
120 mm × 110 mm
vFPGA [V]
FPGA
Configuration ROM
AD Converter
DA Converter
Digital Output
Power Supply
Size
(a) Gate signal from FPGA
MOSFET
3.3V
0V
Fig. 4.
0V
Gate drive circuit using photocoupler
3.3V
Buffer
0V
Fig. 5.
vGS
0V
3.3V
FPGA
RG
Photo
-coupler
Buffer
vGS [V]
FPGA
15V
Digital
MOSFET
isolator
driver
0V
20
15
10
5
0
-5
MOSFET
(b) Gate-source voltage of MOSFET in Fig. 4
12V
5V
0V
RG
vGS
0V
vGS [V]
3.3V
8
6
4
2
0
-2
Gate drive circuit using digital-isolator
pulse width of the gate-source voltage is wider than that of
FPGA signal. The time delay of the gate drive circuit is less
than 50 ns, so it is only 2% compared with the sampling time
of 2.5 µs. As the results, it is suitable to use the digital isolator
in the gate drive circuit for 200-kHz PWM inverter.
20
15
10
5
0
-5
(c) Gate-source voltage of MOSFET in Fig. 5
100 ns / div
Fig. 6.
Experimental results of the gate drive circuit
TABLE IV
Time Delay of the Inverter
C. Time Delay of Experimental System
Table IV summarizes the time delay of the experimental
system. The processing time of the FPGA takes 70 ns, because
the clock frequency in the FPGA is set to 100 MHz and the
calculation time of the control uses 7 clocks. The propagation
time delay of the gate drive circuit is 50 ns, and the dead time
of the inverter is set to 300 ns.
The whole time delay of the experimental system is less
than that of the sampling time of the AD converter. Therefore,
the time delay of the digital controller does not take into
consideration in the following section.
Processing Time in FPGA
Propagation Time in Gate Drive
Dead Time of the Inverter
AD Converter
∗
circuit. In this case, the transfer function Iout (s)/Iout
(s) of the
current control system is given by,
Iout (s)
=
∗
Iout
(s)
IV. Analysis of Current Controller
A. Transfer Function of the current control
Fig. 7 shows block diagram of the current controller without
any time delay of the control circuit. The controller is only
applied to the proportional controller KP . Here, H(s) and aL
in Fig.7 are as follows,
1 − e−sTS
H(s) =
s
aL =
r+R
L
(1)
(2)
where T S is a sampling time of the AD converter, and H(s)
represents a zero-order hold circuit which means the inverter
70 ns (7 clocks)
50 ns
300 ns
280 ns
aL KP
(1 − e−sTS )
(r + R)T S
.
aL KP
s2 + a L s +
(1 − e−sTS )
(r + R)T S
(3)
In the following analysis, continuous control system is
converted to discrete control system. Hence z-transformation
is applied to the current control system. Fig. 8 shows the
z-transformation block diagram of Fig. 7, and the transfer
∗
(z) in Fig. 8 is as follows.
function Iout (z)/Iout
Iout (z)
=
W (z) = ∗
Iout (z)
∗
KP
(1 − e−aL TS )
r+R
KP
(1 − e−aL TS )
z − e−aL TS +
r+R
(4)
B. Stability Analysis of the Current Controller
In order to analyze the stability of the controller, the root
locus on z-plane is used. The characteristic equation in (4) is
1033
TS
+
∗
Iout
(s)
Fig. 7.
element
H(s)
KP
−
Im
PWM Inverter Load
aL
s+aL
·
1
r+R
Iout (s)
1
KP =203
-1
Block diagram of the current controller without any time delay
∗
Iout
(z)
+
PWM Inverter and Load
E ∗ (z)
−
KP =97.2
0 KP =50
1−e−aL T S
z−e−aL T S
KP
·
1
r+R
KP =0
1
Re
Iout (z)
-1
Fig. 8.
Block diagram of the current controller using z-transformation
as follows,
KP
(1 − e−aL TS ) = 0
+
(5)
z−e
r+R
Fig. 9 shows the root locus on z-plane when the load of
inverter is connected to only the inductor (L = 254 µH). The
characteristic roots have to exist inside the unit circle on zplane for stable operation, that is, the proportional gain KP is
set to less than 203.
−aL T S
C. Steady-state Error
The steady-state error of the current controller in Fig. (8)
is given by the following equation.
⎛
⎞
KP
⎜⎜⎜
⎟⎟⎟
−aL T S
(1
−
e
)
⎜
⎟⎟⎟ ∗
⎜⎜⎜
r
+
R
∗
⎟⎟⎟ · Iout (z)
(6)
E (z) = ⎜⎜⎜1 −
⎟
KP
⎜⎝
−aL T S ⎟
−a
T
L
S
(1 − e
z−e
+
)⎠
r+R
∗
As the current reference Iout (z) is to step signal,
z
∗
(7)
(z) =
Iout
z−1
the steady-state error is given by substituting (7) into (6).
lim e(nT S ) = e(∞) =
n→∞
r+R
r + R + KP
(8)
The steady-state error e(∞) is decided by the proportional gain
KP , so it is necessary to increase the proportional gain for
reducing the steady-state error.
Fig. 9. Root locus on z-plane when only the inductor is connected to ac
side of inverter
In the case of connecting the only inductor(R = 0) and
KP =50, (9) represents as following approximate equation,
W ∗ (z)KP=50
=
0.471z−1 + 0.209z−2 + 0.0.93z−3 +
0.041z−4 + 0.018z−5 + 0.008z−6 . (11)
In this case, the characteristic root on z-plane is on the
positive real axis in Fig. 9, so the step response does not occur
an overshoot current. And it takes five samples until the steady
state condition from (11).
Due to getting an ideal waveform, the characteristic root
should be set to the origin in z-plane. In the case of z=0 in
Fig. 9, the proportional gain KP is given by,
(r + R)e−aL TS
= 97.2,
(12)
1 − e−aL TS
which is the optimum value of the proportional control. In this
case, the transfer function W ∗ (z) is given by substituting (12)
into (9),
KP =
W ∗ (z)KP=97.2
=
=
KP
(1 − e−aL TS )z−1
r+R
0.915z−1
(13)
As the result, the step response of the controller takes one
samples until the steady state condition.
V. Experimental results
A. Step Response
D. Analysis of Step Response
The transfer function of (4) is converted as following power
series of z−1 ,
KP
(1 − e−aL TS ){z−1 + Az−2 + A2 z−3 + · · · }
(9)
W ∗ (z) =
r+R
where A is given by,
A = e−aL TS −
KP
(1 − e−aL TS ).
r+R
(10)
And z−1 means one sample delay element, and z−n is also n
samples delay.
Fig. 10 shows experimental waveforms when the reference
value i∗out is changing from 1.0 A to 1.5 A as shown in Fig.
10(a). In this case, only the inductor L is connected to ac side
of the inverter, hence the power factor of the circuit is almost
0. In Figs. 10(b) and (c), the proportional gain KP is set to 50
and 100, respectively.
In the case of Fig. 10(b), the output current iout does not
occur overshoot current waveform, and it takes five samples by
the step change. The step response results similar to analytical
results from (11). The steady state values of the experimental
result and analytical result are almost the same. Therefore the
1034
150
1.5
1.0
10 µs
0.5
vout [A]
i∗out [A]
2.0
0
0
-150
(a) Reference signal i∗out
1.5
1.0
0.5
1.5
iout [A]
iout [A]
2.0
0
(b) The output current iout when the proportional gain KP is 50
iout [A]
2.0
0
-1.5
50 µs/div
Fig. 11. Experimental results when the inverter generates 10 kHz sinusoidal
current waveform (power factor = 0.01).
1.5
1.0
0.5
Fig. 10. Step response for the output current with the difference of the
proportional gain KP
150
vout [A]
0
(c) The output current iout when the proportional gain KP is 100
0
-150
iout [A]
1.5
analytical results correspond to the experimental results. When
the KP is set to 100, the output current iout follows as reference
value two samples delay as shown in Fig. 10(c). Moreover,
it can be confirmed by comparison of Figs. 10(b) and (c)
that the response of the output current iout is improved to
increase the proportional gain KP . As the results, the analytical
results of stability and steady-state error correspond to those
experimental results.
0
-1.5
50 µs/div
Fig. 12. Experimental results when the inverter generates 10 kHz sinusoidal
current waveform (power factor = 0.92).
B. Sinusoidal Waveform
vout [A]
150
0
-150
1.5
iout [A]
Figs. 11 and 12 show experimental waveforms of 10 kHz
sinusoidal current waveforms when the power factor of the
RL load is set to 0.01 and 0.92, respectively. In this case, the
proportional gain KP is set to 100, and the current reference
i∗out is set to 10 kHz and the rms value is to 1.06 A.
In the case of Fig. 11, the phase of the output voltage vout
is different in 90 degree from that of the output current iout ,
and the output current waveform is almost sinusoidal. The
amplitude of the output current almost corresponds to the
reference signal (iout = 0.99 A). The output current iout of
Fig. 12 contains switching ripple components, and the rms
value of the output current is 0.71 A.
Fig. 13 shows the experimental results when current reference i∗out is set to 2 kHz and the rms value is to 1.06
A. The load condition is the same as Fig. 12. In this case,
the switching ripple components of the output current can be
reduced compared with Fig. 12, so the current waveform is
almost the pure sinusoidal waveform.
0
-1.5
250 µs/div
Fig. 13. Experimental results when the inverter generates 2 kHz sinusoidal
current waveform (power factor = 0.99).
1035
Gain [dB]
0
0.01
0.1
Frequency [kHz]
10
1
100
0.01
0.1
Frequency [kHz]
10
1
100
-5
-10
-15
-20
Phase [deg]
0
-30
-60
-90
Fig. 14.
Closed loop bode diagram of the current controller and the
experimental results (the inductor and resistor is connected to ac side of the
inverter)
C. Gain- and phase-characteristics
Fig. 14 shows Bode-diagram in (3), and the marks means
the experimental results. The experimental condition is that the
proportional gain KP is set to 100 and the load of the inverter
is connected to the inductor and resistor.
The analytical results of gain- and phase-characteristics are
corresponds to the experimental results in 2 ∼ 20 kHz.
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VI. Conclusion
This paper presents a single-phase PWM inverter with
a current control for producing 10 kHz sinusoidal current
waveforms. A design procedure of the digital controller is
shown in detail. A laboratory system rated at 200-kHz PWM
inverter is confirmed that the validity of the design procedure
from the experimental results.
These experimental results will contribute toward to ultrahigh speed motor drives and a special power supply for
research.
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