ULTRASONIC SENSOR ICs – PCB LAYOUT GUIDELINES
AN 0082
Apr 03, 2013
1 Description
This application note provides hints to hardware developers designing the PCB of an ultrasonic system including
the Elmos Ultrasonic Sensor ICs.
2 Scope
If it is not specially marked, this document is valid for the following Elmos Ultrasonic Sensor ICs:
•
E524.02 / E524.03 / E524.04
•
E524.11 / E524.12 / E524.13 / E524.14
3 PCB layout guidelines
1. During receiving the reflected ultrasonic burst, the system, especially the transformer is very sensitive to
magnetic fields. Therefore place supply and communication traces as far away as possible from trans former and the receiving input circuit and ensure they don’t cross each other.
2. For optimal EMC/EMI performance 4 layer PCB is highly recommended. Top and bottom layers can be
allocated for signal and supply. 2 inner planes are set as grounds. On the top and bottom layers, it is
recommended to separate into 3 distinct sections first before they all come together in a common
ground plane just below the IC, connecting to the exposed Pad of IC.
•
Power and Communication
(IC pins VSUP, GNDP, DRV1, DRV2, IO/LINx and the components C SUP1, CSUP2, CSUP_TD, RSUP_TD and
the transducer)
→ These are the components regarding the supply voltage for the transducer driving and the
communication. These parts can disturb the receiver side.
•
Analog
(IC pins VDDA, GNDA, AINS, AING and the components C VDDA, CAIN1, CAIN2, RAIN, CTD, RTD, transformer and transducer)
→ These are all the components on the transducer matching and receiver side.
•
Digital
(IC pins VDDD, GNDD and test pins, like TDO, TDI, TCK, TMS and TMEN or GPIOs 1-4)
→ These are the rest of the components on the module that can be lumped together and
connected to digital ground.
All components in their respective area (power, analog, digital) should have common ground and should
be connected to the IC respective pins (GNDP, GNDA and GNDD). All areas should be connected to the
GND plane below the IC and the internal layer ground plane.
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QM-No.: 25AN0082E.00
ULTRASONIC SENSOR ICs – PCB LAYOUT GUIDELINES
AN 0082
Apr 03, 2013
3. Internal regulated digital supply decoupling CVDDD place next to pin VDDD and GNDD. Place the decoupling capacitor directly between VDDD (pin 12) and GNDD (pin 13), as shown in figure 1. The ground side
of the capacitor (1) is connected with GNDD and GNDD is directly connected to the exposed Pad. Do not
connect any other ground layer to pin 1 of the capacitor and keep the distance as close as possible. Simil arly, CVDDA must be close to IC pins VDDA and GNDA.
Figure 1: CVDDD placed between VDDD and GNDD
4. Do not connect pin AING and pin GNDA together, even though they are both analog grounds. AING
should connect to transducer receiver circuit while GNDA should be used for decoupling capacitor CVDDA
return ground connection. These 2 grounds only connect back at the central GND below the IC.
5. The ground side of the transducer should be connected to the PCB ground with a good connection. Dur ing an ESD event (several 10 kV) on the surface of the transducer, it is good to have a defined current
path from the transducer to the module GND. Otherwise, if the transducer is only connected to AING, all
the current during this ESD event will flow through the IC and destroy it. Thus, use the inner ground layers to set up a good ground connection to keep the current away from the IC.
6. The resistor RSUP smooths the current spikes during an ultrasonic burst. The transducer driver may generate spikes up to 500 mA and if these spikes are not filtered, they will appear on the supply line. Because
the supply line may be long, it acts a s a good antenna and may fail electromagnetic emission tests. The
resistor withstand a power consumption of 1/3 Watt. Thus, do not use a too small size of resistor.
7. A electrolytic capacitor with at least 68uF is recommended to store the required energy during a burst.
The actual capacitance depends on the used driver current. Calculate the dip during one burst and take
care that there is always enough energy available. Adjust the capacitance accordingly.
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ULTRASONIC SENSOR ICs – PCB LAYOUT GUIDELINES
AN 0082
Apr 03, 2013
8. Do not route the supply line (VSUP) over the complete PCB. Place the filter capacitors C SUP1 and CSUP2 near
by the connector pins.
9. Route the signal lines from the transducer to AINS and AING parallel to each other to minimize the coup ling into the receiving path from disturbances.
10. Check the voltage rating of R TD and CTD. At the transformer side there will be voltages >100V.
11. Connect test pins and unused GPIOs to digital GND.
12. Connect as much VIA through holes as possible to ensure lowest possible resistance.
13. Additional hint regarding EMC, R SUP_TD can be changed to inductor for better EMC suppression in the supply line. This minimizes the emission on the cable harness.
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ULTRASONIC SENSOR ICs – PCB LAYOUT GUIDELINES
AN 0082
Apr 03, 2013
4 QFN land pattern layout
In general the following design rules apply for land pattern design on PCB’s:
1. Land pattern length is 0,05 mm extended (d2) to the centre of the package compared to the terminal
length of the package (L), as well as 0,2 mm extended (d1) outside the package outline unless this will
compromise distance between terminal and exposed die pad.
2. The land pattern width (b3) should be 0.25 mm or bigger, but not more than 0.3 mm on terminals for
pitches above 0,5 mm. However, to avoid solder bridging for components having lead pitches of 0,5 mm,
or smaller, the pad width (b3) should be reduced to 0,28mm or smaller.
3. Minimum spacing between land pattern and exposed die pad is 0,3 mm for packages up to 5x5
4. Placement accuracy should be 50% of the terminal length, since the reflow process will centre the
product.
5. Conductor patterns towards the package are not allowed to go underneath the package, since this can
create shorts.
6. The corners of the packages should be kept free of solder.
7. The land pattern for the exposed die pad can have the same dimension as the exposed die pad of the
package. Please refer to item 3, the exposed pad on the PCB could also be smaller.
8. For QFN packages with plated terminal side walls the land pattern outside the package (d1) has to be
extended as much as possible to benefit from the advantages of the side wall plating, recommended is
0.4 till 0.8 mm, but more would be better. The self alignment works well with d1 is 0.4 mm minimum.
9. The thermal holes on the PCB could have a diameter of 0.25 to 0.4 mm and a grid array of 0.8 to 1.2 mm.
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ULTRASONIC SENSOR ICs – PCB LAYOUT GUIDELINES
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Apr 03, 2013
Figure 2: QFN land pattern layout with package overlay
4.1 Recommended dimensions for land pattern
The Elmos ICs E524.02 / E524.03 and E524.04 are delivered in a QFN20L4 package and the Elmos ICs E524.11 /
E524.12 / E524.13 and E524.14 are delivered in a QFN20L5 package.
QFN20L4
QFN20L5
Symbol
Dimension [mm]
Dimension [mm]
e
0.5
0.65
D2/ E2
2.65
3.65
terminal length
L
0.40
0.40
lead width
b
0.25
0.30
land pattern extension 1
d1
min. 0.20
min. 0.20
2.65
3.65
Description
lead pitch
exposed pad
exposed pad pattern
land pattern length
L3 (d2)
min. 0.60 (0)
min. 0.60 (0)
land pattern width
b3
0.28
0.30
Table 1: Recommended dimensions for land pattern
1
land pattern extension outside the package (d1) must minimum be 0.2 mm, in case of sidewall plating the dimension
should be 0.40-0.80 mm, this will give a better wettability of side plated products.
5 References
[1]
25DS0068E.xx
Data sheet E524.02 / E524.03 (Elmos Semiconductor AG)
[2]
25DS0075E.xx
Data sheet E524.11 / E524.12 / E524.13 / E524.14 (Elmos Semiconductor AG)
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ULTRASONIC SENSOR ICs – PCB LAYOUT GUIDELINES
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WARNING – Life Support Applications Policy
Elmos Semiconductor AG is continually working to improve the quality and reliability of its products. Neverthe less, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vul nerability to physical stress. It is the responsibility of the buyer, when utilizing Elmos Semiconductor AG products,
to observe standards of safety, and to avoid situations in which malfunction or failure of an Elmos Semiconductor
AG Product could cause loss of human life, body injury or damage to property. In the development of your
design, please ensure that Elmos Semiconductor AG products are used within specified operating ranges as set
forth in the most recent product specifications.
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Information furnished by Elmos Semiconductor AG is believed to be accurate and reliable. However, no respons ibility is assumed by Elmos Semiconductor AG for its use, nor for any infringements of patents or other rights of
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document or the products contained therein without prior notice, to improve performance, reliability, or manu facturability.
Application Disclaimer
Circuit diagrams may contain components not manufactured by Elmos Semiconductor AG, which are included as
means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. The information in the application examples has been carefully checked and is
believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such
information does not convey to the purchaser of the semiconductor devices described any license under the pat ent rights of Elmos Semiconductor AG or others.
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