PRODUCTION DATA - SEP 03, 2012
Features
General Description
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The E524.xx with integrated microcontroller offer ultrasonic range detection with minimum component
count. A single ultrasonic transducer with a center
tapped transformer is directly driven with programmable 30kHz to 80kHz bursts. Supported transducers allow distance measuring from 15cm to 4m and beyond
in extended range mode.
The received echo signal is amplified and converted
by an ADC. Digital filtering achieves excellent tracking
with the sending frequency without external components or trimming. Optional temperature compensation is available through GPIO pins.
An onboard EEPROM stores processed values of the oscillator/sending frequency, transmitted power and receiver sensitivity. Communication to an ECU is via a single-wire bus compatible with LIN 2.1. For ease of use, a
System ROM is pre-programmed with the Elmos BootManager™ and application support routines. Available
software examples cover threshold-based echo detection, a basic LIN stack and a complete USPA application
example
All ICs contain EEPROM. Options include FLASH or ROM,
LIN Auto-addressing and Range Extension.
Stand-alone Ultrasonic Park Assist Solution
Includes Driver for Ultrasonic Transducer
Programmable Transducer Power
Programmable Receiver Sensitivity
EEPROM Storage of Calibration Values
Digital Filtering and Signal Processing
Adjustable Burst Length and Filter Bandwidth
Low Noise Down to 0.5μVRMS
Internal Oscillator
LIN 2.1 Interface with Auto-Addressing
Short/Long Distance Range Modes
8bit CPU with 16MHz Clock
8KByte Customer FLASH or ROM
Integrated Elmos BootManager™
512Byte RAM
Fast Calibration Data Exchange via LIN
FLASH
ROM*
E524.11
E524.12
E524.13
E524.14
E524.21
E524.22
E524.23
E524.24
LIN Auto­
addressing
Range
Extension
X
X
X
X
*Contact factory for more information
Applications
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Ordering Information
Ultrasonic Park Assist Systems (USPA)
Blind Spot Detection
Industrial Distance Measuring
Robotics
Product ID
Temp Range
Package
E524.xx
-40°C to +105°C
QFN20L5
Note: “xx” refers to available options such as FLASH, ROM, LIN
and Range Extension
Typical Applications Circuit
RSUP_TD
CTD1
RTD1
CSUP_TD
Ultrasonic
Transducer
CAIN2
RAIN
CAIN1
DRV1
VBAT
RSUP
DSUP
DRV2
AING
VSUP
AINS
GPIO1
GPIO2
CSUP1
TDO / GPIO3
CSUP2
TDI / GPIO4
Note:
BUS_S E524.x2 and E524.x4 only
VDDD
E524.1x/2x
GNDD
LIN_S
BUS_S
LIN_M
BUS_M
VDDA
GNDB
GNDA
CBUS
GNDP
TMEN
TCK
CVDDD
CVDDA
TMS
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
1/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
TMEN
TCK
TMS
TDO / GPIO3
TDI / GPIO4
VSUP
GNDD
VDDD
Functional Diagram
GNDP
Watchdog
GPIO
GPIO1
GPIO2
GNDB
BUS_M
Timer 1
Timer 2
DMF
AMP
ADC
AINS
8 Bit µC
BPF
AING
Bias /
References
Clamp
VDDA
GNDA
Reset
DRV1
8 KByte Flash/ROM
4 KByte System ROM
128 Byte EEPROM
512 Byte RAM
LIN Transceiver
DRV2
LIN SCI
Frequency
Generator
Driver
Regulator
JTAG Logic
1)
AMP
R
BUS_S
1)
1) E524.x2 and E524.x4 Only
Bottom Side
TCK
TMS
Pin 1
TDO / GPIO3
TMEN
Top View
TDI / GPIO4
Pin Configuration
20 19 18 17 16
AINS
1
15
GNDD
AING
2
14
VDDD
GNDA
3
13
GPIO1
VDDA
4
12
GPIO2
DRV1
5
11
VSUP
EP
6
7
8
9
10
GNDP
DRV2
GNDB
BUS_M
BUS_S
E524.xx
Note: Pin 10 is BUS_S for E524.x2 and E524.x4 and n.c. for all other versions.
Not to scale, EP Exposed die pad
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
2/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Pin Description
Pin
Name
Type 1)
Description
1
AINS
I
Positive Analog Signal Input from Transducer
2
AING
I
Negative Analog Signal Input from Transducer
3
GNDA
S
Analog Ground
4
VDDA
S
Analog Supply Voltage. Bypass with CVDDA to GNDA.
5
DRV1
O
Driver Output 1. Connects to push-pull-transformer
6
GNDP
S
Ground for Driver Outputs. Connect to ground plane. Ensures low-impedance
path for driver outputs.
7
DRV2
O
Driver Output 2. Connects to push-pull-transformer.
8
GNDB
S
Ground for Bidirectional Interface
9
BUS_M
I/O
LIN Bus I/O, Auto-addressing Input
10
BUS_S /
N.C.
O
Slave Node Position Detection (SNPD) only for E524.x2, E524.x4. N.C. for E524.x1
and E524.x3.
11
VSUP
S
Battery Supply Input. Connect to voltage source with reverse polarity protection
circuit as shown in Typical Application Circuit.
12
GPIO2
I/O
General Purpose Digital Input / Output
13
GPIO1
I/O
General Purpose Digital Input / Output
14
VDDD
S
Digital Supply Output. Can supply up to 4mA to an external load. Bypass with
CVDDD to GNDD
15
GNDD
S
Digital Ground
16
TCK
I
JTAG Clock Input. If not in test mode, connect to ground plane.
17
TMS
I
JTAG Select Input. If not in test mode, connect to ground plane.
18
TDO /
GPIO3
I/O
JTAG Data Output or General Purpose Digital Input / Output if not in test mode.
19
TDI /
GPIO4
I/O
JTAG Data Input or General Purpose Input / Output if not in test mode.
20
TMEN
I
Test Mode Enable Input. Connect to ground plane if not in test mode.
-
EP
S
Exposed Die Pad
1) I/O = Input/Output, S= Supply
Note: Connect GNDA, GNDP, GNDB, GNDD and EP to system ground.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
3/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
1 Absolute Maximum Ratings
Stresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These are stress ratings only; operation of the device at these or any other conditions beyond those listed in the operational sections of this document
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltages
with respect to ground. Currents flowing into terminals are positive, those drawn out of a terminal are negative.
Description
Condition
Supply Voltage
Symbol
Min
Max
Unit
VSUP
-0.3
30
V
Supply Voltage
t < 500ms
VSUP_DYN
-0.3
40
V
Voltage at Pin BUS_S, BUS_M
IBUS = 1mA
VBUS
-0.3
30
V
Voltage at Digital Pins
(TCK, TDO, TDI, TMS, VDDD)
VD
-0.3
3.6,
VDDD+0.3
V
Current into Digital Pins
(TCK, TDO, TDI, TMS, VDDD)
ID
-10
10
mA
Voltage at Analog Pins
( VDDA)
VA
-0.3
3.6
V
Voltage at Analog Pins
(AINS, AING)
VAIN
-0.8
3.6,
VDDA+0.3
V
Current into Analog Pins
(AINS, AING, VDDA)
IA
-20
20
mA
V TMEN
-0.3
3.6
V
VDRV
-0.3
40
V
24
K/W
Voltage at Pin TMEN
Voltage at Pins DRV1 and DRV2
IDRV = 500µA
Thermal Resistance
Junction to Ambient
RT,J-A
Ambient Temperature
TAMB
-40
+105
°C
Junction Temperature
TJ
-40
+125
°C
Storage Temperature
TSTG
- 55
+125
°C
2 ESD Protection
Description
Condition
Symbol
Min
Max
Unit
ESD HBM protection at pin BUS_M,
BUS_S
HBM
V BUS_M, BUS_S
±6
-
kV
ESD HBM, all other pins
HBM 1)
VPINS-OTHER
±2
-
kV
ESD CDM at edge pins
CDM
2)
V PINS EDGE
±0.75
-
kV
ESD CDM at all other pins
CDM
2)
VPINS-OTHER
±0.5
-
kV
1)
Note: Test point defined as tested pin to supply.
1) According to AEC-Q 100-002, Human Body Model, 1.5kΩ resistance, 100pF capacitance.
2) According to AEC-Q 100-011, Charged Device Model, pulse rise time (10% to 90%) <400ps, 1Ω resistance.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
4/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
3 Electrical Characteristics
(V VSUP = +8V to +18V, TAMB = -40°C to +85°C, unless otherwise noted. Slew rate at pin VSUP < 1V/µs. Typical values
are at V VSUP = +13.5V and TAMB = +25°C. Positive currents flow into the device pins.)
Description
Condition
Symbol
Min
Typ
Max
Unit
Functional Range
1)
VSUP
8
13.5
18
V
Input Voltage
pins AINS, AING
VIN
-0.8
0.8
V
Input Current
pins AINS, AING
IIN
-20
20
mA
Current Consumption VSUP
CPU active
IVSUP
Internal Analog Supply
external CVDDA
connected
VDDA
3.0
3.3
3.6
V
Internal Digital Supply
external CVDDD
connected
VDDD
3.0
3.3
3.6
V
Supply Voltages
10
mA
Current out of VDDA if shorted to
GNDA
IVDDA,SHORT
22
35
mA
Current out of VDDD if shortened
to GNDD
IVDDD,SHORT
55
75
mA
Output Current External Loads
DC load only
IVDDD,OUT
4
mA
CPU Clock Frequency
T= 25 °C
fOSC_RT
15.85
CPU Clock Frequency
2)
fOSC
15.6
Addressable Memory Size
words * width
N*W
64K*8
Bit
words * width
N*W
512 * 8
Bit
Memory Size
address size N, word
length W
N*W
8K * 8
Bit
One Page Memory Size
address size N, word
length W
N * WPAGE
256 * 8
Bit
Number of Pages
NPAGE
2
Data Retention Time
tRET_F
CPU Core and Oscillator
16
16.15
MHz
16.4
MHz
RAM
Memory Size
Flash (E524.1x Only)
Program/Erase Endurance
operating life 10000h NEND_F_85
10
Year
10
Cycle
ROM (E524.2x Only)
Memory Size
address size N, word
length W
N*W
8K * 8
Bit
address size N, word
length W
N*W
128 * 8
Bit
EEPROM
Memory Size
Data Retention Time
tRET_EE
10
Year
Program / Erase Endurance
NEND_EE_85
104
Cycle
1) The supply voltage should be limited to 18V to guarantee faultless LIN operation as defined in the LIN 2.1 specification.
2) Not production tested
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
5/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Electrical Characteristics (continued)
(V VSUP = +8V to +18V, TAMB = -40°C to +85°C, unless otherwise noted. Slew rate at pin VSUP < 1V/µs. Typical values
are at V VSUP = +13.5V and TAMB = +25°C. Positive currents flow into the device pins.)
Description
Condition
Symbol
Min
Typ
Max
Unit
Minimum Gain
fDRV = 52kHz received
echo
GMIN
52.5
56.5
60.5
dB
Maximum Gain
fDRV = 52kHz received
echo
GMAX
84
88
92
dB
Gain Temperature Variation
fDRV = 52kHz received
echo
GDRIFT
Step Size
fDRV = 52kHz received
echo
ΔG
Signal Processing - Amplifier
dB/
°C
0.0015
0.1
0.5
0.8
dB
Number of Steps
NG
63
Input Impedance
RIN
100
kΩ
eN
7
nV/
√Hz
0.65
V
Noise Level
fDRV = 52kHz received
echo
Limiting Voltage
IIN = 1mA, TAMB = 25°C,
VLIM
pin AINS, AING
Maximum Absolute Input Current
Pin AINS, AING
IIN
Resolution
No missing codes
N
Integral Nonlinearity
1)
INL
±1
LSB
tsetup_time
5
µs
-20
20
mA
Signal Processing - ADC
Input Setup Time
Supply Voltage Range Accuracy
8
VSUPACC
2)
Bit
+/- 3
%
Transducer Driver
Transducer Frequency Range
fDRV
30
80
kHz
VDRV1,2 = 0V, 12V
IDRV,LEAK
-400
400
nA
NI
63
Current Step Size
3)
STEPIDRV
5.33
mA
Minimum Adjustment Current
3)
IDRV,min
160
mA
Maximum Adjustment Current
3)
IDRV,max
496
mA
Current Step Size
4)
STEPIDRV
3.2
mA
Minimum Adjustment Current
4)
IDRV,min
96
mA
Maximum Adjustment current
4)
IDRV,max
298
mA
Voltage Drop at DRV1 and DRV2
IDRV < 200mA,
DRV_CUR = 63
VDROP,DRV
-
Clamping Voltage
IDRV,CLAMP = 500µA
VDRV,CLAMP
40
Leakage Current
Current Adjustment Steps
1)
2)
3)
4)
0.5
1
V
V
Not production tested
ADC reference voltage derived from VDDA
E524.13, E524.14, E524.23 and E524.24 only
E524.11, E524.12, E524.21 and E524.22 only
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
6/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Electrical Characteristics (continued)
(V VSUP = +8V to +18V, TAMB = -40°C to +85°C, unless otherwise noted. Slew rate at pin VSUP < 1V/µs. Typical values
are at V VSUP = +13.5V and TAMB = +25°C. Positive currents flow into the device pins.)
Description
Condition
Symbol
Min
VS
Typ
Max
Unit
7
18
V
VS-1V
VS
V
LIN Interface – Physical Layer
LIN Supply Voltage (Transceiver
Supply Voltage of Transmitting
Node)
Recessive Output Voltage
IBUS = 0mA
VBUS_REC
Dominant Output Voltage
IOUT = 20mA
VOUT_I20
0.7
1.1
V
Dominant Output Voltage
IOUT = 40mA
VOUT_I40
1.7
2.0
V
Leakage Current (driver off)
8V < VS < 16V
8V < VBUS < 18V
VBUS≥ VS
IBUS_PAS_rec
20
μA
Input Leakage Current incl. Pull-up
Resistor
VBUS = 0V
VS = 12V
IBUS_PAS_dom
-1
IBUS_SHORT
40
VBUS_THRES
0.40
0.475
Short Circuit Current
Threshold Voltage
Rising and falling
edge
Center Voltage
1)
VBUS_CENTER
Threshold Hysteresis Voltage
2)
VBUS_HYS
Loss of Ground Current
GNDB = VS = 0V
-12.8V < VBUS < 0V
IBUS_NO_GND1
Leakage Current
(VBAT disconnected)
VS=0V
0V<VBUS<18V
IBUS_NO_BAT
Pull-up Resistance
VBUS=0V
RPU
1)
V BUS _ THRES +V BUS _ THRES2
2)
V BUS _ HYS=V BUS _ THRES +−V BUS _ THRES -
mA
75
0.5
200
mA
0.60
VS
0.525
VS
0.175
VS
-1.0
mA
100
μA
20
40
60
kΩ
Min
Typ
Max
Unit
6
μs
2
μs
Note) VBUS_THRES+ : Receiver threshold of the recessive to dominant LIN bus edge.
VBUS_THRES- : Receiver threshold of the dominant to recessive LIN bus edge.
Description
Condition
LIN Interface – Bus Timing Parameters
Symbol
3)
trx_pdr ,
trx_pdf
Propagation Delay BUS - RXD
Propagation Delay Symmetry
Receiver
trx_sym= trx_pdf - trx_pdr
trx_sym
-2
Duty Cycle 1
THRec(Max) =0.744 *VS
THDom(Max) =0.581 *VS
7V ≤ VS ≤ 18V
tBit =50μs
D1
0.396
D1=
t BUS _ REC MIN 
2∗t Bit
3) Bus Load Conditions (CSlave; RBUS) : 1nF; 1kΩ / 6.8nF;660Ω / 10nF;500Ω.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
7/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Electrical Characteristics (continued)
(V VSUP = +8V to +18V, TAMB = -40°C to +85°C, unless otherwise noted. Slew rate at pin VSUP < 1V/µs. Typical values
are at V VSUP = +13.5V and TAMB = +25°C. Positive currents flow into the device pins.)
Description
Condition
Symbol
Duty Cycle 2
THRec(min) =0.422 *VS
THDom(min) =0.284 *VS
7.6V ≤ VS ≤ 18V
tBit = 50 μs
D2
THRec(Max) =0.778 *VS
THDom(max) =0.616 *VS
7V ≤ VS ≤ 18V
tBit=96μs
D3
THRec(Min) =0.389 *VS
THDom(Min) =0.251 *VS
7.6V ≤ VS ≤ 18V
tBit = 96μs
D4
D2=
t BUS _ REC MAX 
2∗t Bit
Duty Cycle 3
D3=
t BUS _ REC MIN 
2∗t Bit
Duty Cycle 4
t BUS _ REC MAX 
D4=
2∗t Bit
Min
Typ
Max
Unit
0.581
0.417
0.590
LIN Auto-Addressing (E524.12, E524.22, E524.14 and E524.24 only)
Bus Pull-up Current Source for
Auto-Addressing
VBUS = 0V
IPD
1.84
2.05
2.26
mA
Bus Shunt Resistor
1)
RSHUNT
0.62
1.00
1.55
Ω
Temperature Coefficient of Bus
Shunt Resistor
0°C < TAMB < +50°C 2)
TKSHUNT
Differential Amplifier Differential
Input Voltage Range
0°C < TAMB < +50°C 3)
VDIFF_AMP
-10
30
mV
Differential Amplifier Common
Mode Input Voltage Range
3)
VCOM_AMP
0.00
2.50
V
Differential Amplifier Gain
0V < VBUS < 2.5V 1)
ADIFF
65
74
V/V
0.4
%/K
70
GPIO (General Purpose Input / Output Pins)
Pull-up Current
VIN = 0V
IPULL_UP
-20
-35
μA
Pull-down Current
VIN = VDDD
IPULL_DOWN
20
35
μA
Threshold High
2)
VTHLOHI
0.9
2.1
V
Threshold Low
2)
VTHHILO
0.7
1.9
V
Hysteresis
2)
VHYS
0.2
1.4
V
IOUTLOW
4
15
mA
IOUTHIGH
-3
-15
mA
VGPIO4_A
0
3.3
V
Output Current Force Low
Output Current Force High
Analog Input Voltage Range ADC
GPIO4 only if config.
4)
1) Total gain of auto-addressing path is tested through digital ADC output.
2) Parameter not tested in production.
3) Operation outside of common mode and/or differential input voltage range within the absolute maximum ratings will not
result in damage, but will produce invalid results on the differential amplifier's output.
4) ADC reference voltage derived from VDDA
Note) The auto-addressing functions have limited ground shift tolerance compared to normal LIN operation.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
8/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
4 Typical Operating Characteristics
(VSUP = +13.5V, TAMB = +25°C, unless otherwise noted.)
Bandpass Filter Frequency Response
Lowpass Filter Frequency Response
Frequency [normalised to fDRV]
Frequency [normalised to fDRV]
Referenced to VS, IBUS = 0mA
16.10
IBUS (8V), VSUP=8V
16.00
15.95
20
18
18
16
16
14
14
12
12
10
10
8
8
6
6
4
4
2
2
0
15.90
-25
0
25
50
0
-60
75
-40
-20
0
40
60
80
100
Temp / ºC
Temp. / °C
LIN Dominant Output Voltage vs. Temperature
LIN Recessive Output Voltage vs. Temperature
1.00
1.80
-0.12
0.98
1.70
0.96
1.60
0.94
1.50
0.92
1.40
0.90
1.30
0.88
1.20
-0.24
0.86
1.10
-0.26
0.84
1.00
-0.28
0.82
0.90
V_BUS_DOM (I=20mA) / V
-0.10
-0.14
Rec. LIN Voltage / V
20
-0.16
-0.18
-0.20
-0.22
0.80
-0.30
-60
-40
-20
0
20
40
60
80
Temp. / °C
Referenced to Vs , Ibus = 0mA
0.80
-60
100
V_BUS_DOM (I=40mA) / V
f_osc / MHz
16.05
20
IBUS (18V), VSUP=8V
LIN Rec. Leakage Current vs. Temperature
Oscillator Frequency vs. Temperature
-40
-20
0
20
40
60
80
100
Temperature / ºC
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
9/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
46.8
46.7
DRV min / mA
46.5
46.4
46.3
550
240
540
230
530
220
520
210
510
200
500
190
490
180
480
170
470
160
460
150
46.2
-40
-20
0
20
40
60
80
450
-60
100
-40
-20
0.53
0.51
0.51
0.49
0.49
0.47
Idrv min / mA
0.53
V_BUS_REC_Thres / VSUP
V_BUS_DOM_Thres / VSUP
0.55
0.47
0.45
0.45
-20
0
20
40
60
80
145
335
140
330
135
325
130
320
125
315
120
310
115
305
110
300
105
295
290
2
4
6
8
10
3.30
3.25
3.25
3.20
3.20
3.15
3.15
3.10
Idrv min / mA
VDDA / V
3.30
VDDD / V (Iout = 4mA)
3.35
3.10
40
14
16
18
20
Extended Driver Current vs. Driver Voltage
3.35
20
12
Vdrv / V
3.40
0
100
100
VDDA and VDDD vs.Temperature
-20
80
340
100
3.40
-40
60
150
Temperature / ºC
-60
40
Driver Current vs. Driver Voltage
LIN Bus Thresholds vs. Temperature
0.55
-40
20
Temperature / ºC
Temp. / °C
-60
0
Idrv max / mA
-60
60
80
100
220
520
215
515
210
510
205
505
200
500
195
495
190
490
185
485
180
480
175
475
170
470
2
Temperature / ºC
4
6
8
10
12
14
16
18
Idrv max / mA
RPU / Ω
46.6
250
DRV max / mA
Extended Driver Current vs. Temperature
LIN Pull-up Resistor vs. Temperature
20
Vdrv / V
330
128
328
126
326
124
324
122
322
120
320
118
318
116
316
114
314
112
312
110
DRV max / V
DRV min / V
Driver Current vs. Temperature
130
310
-60
-40
-20
0
20
40
60
80
100
Temperature / ºC
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
10/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
5 Functional Description
5.1 Overview Central Processing Unit
The internal CPU primarily controls onboard peripherals
such as burst generator, LIN transceiver and memory.
It also coordinates the measurement and digital signal
processing of the received echo signal.
Following events or sources may generate interrupts.
Software interrupt (SWI) instruction, SCI interface, EEPROM, digital filter, sloping/rising edge of GPIO pins
and timers.
5.2 Device Operation Modes
sent out via the drivers. At the same time, received echo
signals are measured, processed and stored. The LIN interface is active at all times.
After power-up, the IC always starts in Configuration
Mode. Within a specified time window the ELMOS Boot
Manager can be activated via LIN to take over control.
If not, the device switches into Operational Mode and
device registers are reset to their initial state.
The application in customer FLASH (or ROM) is executed starting at the address defined by the user applicationRESET vector.The Boot Manager activation time
window can be set through an ELMOS Boot Managerconfiguration command.
5.3 Memory Mapping
Two device mode operations are available: Configuration and Operational Mode.
In Configuration Mode, the ELMOS Boot Manager can
be used to exchange calibration data, store parameter
of custom designed applications and read/write specific memory areas via LIN in normal or high-speed mode.
In Operational Mode, burst signals are generated and
The memory map is designed to provide a defined
method for configuration and switching into Operational Mode at power-up. This is achieved by a pre-defined switching of memory addresses as shown in Table
1. Memory Map.
Table 1. Memory Map
Operational Mode
zero page
Configuration Mode
Special function registers (SFR) are accessible in direct mode or extended mode addressing. Unused addresses return 0x83 (opcodeSWI) when read.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
11/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Table 2. Special Function Registers
Note) Some register functions are restricted to specific device options.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
12/45
QM-No.: 25DS0075E.01
PRODUCTION DATA - SEP 03, 2012
5.4 Interrupt Vectors
Power-on reset, Watchdog and Software interrupts
are always enabled. All others interrupts are disabled
by default with interrupt mask bit called “I”. Following
events affect the setting of the “I” bit and disable interrupts with an interrupt number under 14: Power-on
reset, Watchdog reset, switching to operational mode
and the assembler command STI (set of interrupt mask
bit). Interrupts 14 and 15 are always enabled.
Table 3 illustrates shows all interrupt sources and their
vector addresses. The highest interrupt number has the
highest priority.
Table 3. Interrupt Vector List
Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Block
POR / WD
CPU
EEPROM
EE_ERR_IRQ
EEPROM
EE_READY_IRQ
EEPROM
EE_ECCERR_IRQ
SCI
SCI_BIE_IRQ
SCI
SCI_MFIE_IRQ
SCI
SCI_RIE_IRQ
SCI
SCI_TIE_IRQ
FILTER
FILTER_IRQ
GPIO
GPIO_IRQ
TIMER1
TIMER1_OC_IRQ
TIMER1
TIMER1_OF_IRQ
TIMER2
TIMER2_OC_IRQ
TIMER2
TIMER2_OF_IRQ
-
Vector Address
0xFFFE - 0xFFFF
0xFFFC - 0xFFFD
Source
Power-On Reset, Watchdog
Software Interrupt (SWI)
0xFFFA - 0xFFFB
Wrong Write Sequence Detected
0xFFF8 - 0xFFF9
Erase/Programming Finished
0xFFF6 - 0xFFF7
ECC Error Detected
0xFFF4 - 0xFFF5
Break Detected
0xFFF2 - 0xFFF3
Measurement Finished
0xFFF0 - 0xFFF1
Receive Register Full
0xFFEE - 0xFFEF
Transmit Register Empty
0xFFEC - 0xFFED
New Filter Value Ready
0xFFEA - 0xFFEB
GPIO Edge Event
0xFFE8 - 0xFFE9
Timer 1 Output Compare
0xFFE6 - 0xFFE7
Timer 1 Overflow
0xFFE4 - 0xFFE5
Timer 2 Output Compare
0xFFE2 - 0xFFE3
Timer 2 Overflow
0xFFE0 - 0xFFE1
Reserved
5.5 CPU Programming
The ELMOS EL3.5 CPU core uses a standard architecture
where a CPU and a memory array are interconnected by
an address bus and a data bus. The operation code (opcode) is a subset of the 68HC05. The address bus identifies which memory space is being accessed, and the
data bus relays information either from the CPU to the
memory location or vice versa. The instruction set includes 8 by 8 multiplication, 16 interrupt vectors, 16 bit
address range, 6 Bit stack pointer and a 15 Bit extend-
ed program counter. Figure 1 gives an overview of the
accumulator, index register, control flow stack pointer,
program counter and the condition code register CCR.
Note) 68HC05 is a registered trademark of Freescale Semiconductor
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
13/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
4
2
Figure 1. CPU Register Layout
The CPU registers are hardwired and act as a small
scratch pad and control panel for the CPU. Available
CPU Registers are listed in Table 4. CPU Registers.
The accumulator (A) is used for general calculations and
the index register (X) for indirect and indexed addressing. The control flow stack pointer (SP) is internally used
by the CPU only. The program counter (PC) is 16 bit long.
Size
5 bits
16 bits
5 bits
8 bits
8 bits
Bit
4
3
2
1
0
Name
(H)
(I)
(N)
(Z)
(C)
Description
Half-Carry (from bit 3)
Interrupt Mask
Negative Flag
Zero Flag
Carry Bit
6 Memory Usage
Table 4. CPU Register
Name
(CCR)
(PC)
(SP)
(X)
(A)
Table 5. Condition Code Register CCR
Description
Condition Code Register
Program Counter
Control Flow Stack Pointer
Index Register
Accumulator
The EL3.5 CPU can be reset in three ways:
• Initial power-on reset
• WATCHDOG reset
• Switching from Configuration to Operational Mode
Any of these resets will set the program to its starting
address and clear all registers to their respective reset
values. The interrupt mask bit will be set to interrupt
disable and the stack pointer to its initial state.
All E524 versions include 512 Byte of random access
memory (RAM). The RAM incorporates a synchronous
read and write interface for temporary storage of data
and instructions. RAM memory is volatile and data is
lost when power is removed.
Customer programs can be stored in either Flash or
ROM space up to 8 KByte. Useful additional routines are
located in System ROM and save Flash or ROM memory
space.
Following devices use data and instructions stored permanently in read-only memory (ROM) at the time of
manufacture: E524.21, E524.22, E524.23 and E524.24.
Following devices contain non-volatile Flash memory
that can be re-programmed: E524.11, E524.12, E524.13
and E524.14.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
14/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
6.1 System ROM
All devices contain a special ROM area named SysROM™
as shown in Table 1. It is a device-integrated software
library available for user applications.
Built-in functionality via SysROM™ includes the ELMOS
Boot Loader™ (BMM). The boot loader controls the device behaviour after power up and offers synchronized
functions to manipulate EEPROM, FLASH and SFRs in
several devices at the same time. It is optimized to
rapidly handle typical tasks at system integration. The
boot loader supports calibration, re-flashing, LIN auto-addressing and custom applications. It communicates via LIN in standard and bi-directional high-speed
modes up to 125 Kbit/s.
SysROM user application extensions offer an API to facilitate EEPROM read and manipulation, access to LIN
auto addressing and version management as illustrated
in Figure 2.
Figure 2. SysROM Block Diagram
6.2 Flash Programming and Erasing (E524.1x)
The 8 KByte non-volatile ELMOS Flash memory block
is designed to store customer data. It allows programming up to 64 bytes at once and contains a mass erase
mode. Available lowercase Page erase saves time if reprogramming of dedicated data up to 512 bytes is required. Flash memory is available for all E524.1x versions.
Erasing or programming via LIN interface is fully supported by the ELMOS Boot Manager located in SysROM.
To avoid unwanted programming or erasing there is a
32 bit Flash Key hardware technique implemented that
must be handled in a specific sequence and time frame
to unlock Flash manipulation function. The key is transmitted to the E524 via LIN. It is recommended to erase
Flash cells before programming. The Flash erasing/programming voltage is generated internally.
Figure 3. Flash Segmentation illustrates how the first
of 512 bytes are separated by two pages. The size of
each of them is 256 bytes. Every page can be erased at
once in page erase mode. To save programming time,
the first or second page can be erased and written separately.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
15/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
256 256
PRODUCTION DATA - SEP 03, 2012
Figure 3. Flash Segmentation
6.3 EEPROM Programming / Usage
EEPROM non-volatile reprogrammable memory cells
are designed to store customer data. A predetermined
sequence of conditions is needed to erase or program,
securing the EEPROM from unintentional erasing/programming.
The E524.xx parking assist devices use EEPROM to store
calibration and adjustment data of up to 128 Byte. Every EEPROM cell is internally protected by an additional 4
Bit error correction code. Accessing EEPROM adds 4 additional wait cycles for one read operation.
EEPROMs are programmed as single bytes. The EEPROM
erasing/programming voltage is generated internally.
Before any programming takes place, the respective
EEPROM cell is erased. EEPROM cells may be erased in
single byte or in an all-in-one mode. All operations are
available as routines located in SysROM.
6.4 Typical USPA User Application Flow
A typical flow of an ultrasonic park assist application
driven by a LIN master is shown in Figure 4. It starts
with power up on the left and continues with a user
specific application run in operational mode after the
device leaves configuration mode. The Boot Manager
Module (BBM) can be completely disabled after assembly into the car.
Figure 4. USPA User Application Flowchart
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
16/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
7 Timer Functions
7.1 Overview
7.2 Watchdog Timer 0
The E524.xx has three dedicated timers. Timer 0 is a
configurable window watchdog. Timer 1 and 2 can be
used to generate defined timer interrupts to capture
the delay between a signal is sent out and the time it
took to return.
The configurable window watchdog period starts after
the first write to the window mode (WM) bits and can
not be stopped. In CPU debug mode (Pin TMEN = VDDD)
the watchdog is always disabled. Trigger the watchdog
by writingWDOG = 0x55. The watchdog resets if the
watchdog timer elapses (times out) if the trigger does
not occur in the specified time window.
Table 6. Watchdog Register WDOG
Address 0x01
b7
Content
Reset Value
Access
CFG
WM[1:0] 0
0
0
0
0
0
0
0
R/W
R/W
R/W
W
W
W
W
W
CFG : Configure Watchdog
CFG = 1 : The current write access is used to configure the watchdog window mode
CFG = 0 : The watchdog is triggered if value being written is 0x55
WM[1:0] : Window Mode
Watchdog must be reset within specified window settings since last reset
Bit Description
b6
b5
b4
b3
b2
b1
b0
Table 7. Watchdog Window Settings
[WM1:WM0]
Start Window
(Clock Cycles)
Stop Window
(Clock Cycles)
Time Period in μs
(fOSC = 16 MHz)
00
01
10
11
0
16384
16384
32768
131071
131071
65535
131071
0 - 8191
1024 - 8191
1024 - 4095
2048 - 8191
7.3 Timer 1 and Timer 2
The timers are configured as independent 16 bit free running counters. The counter frequency is adjustable with a
pre-scaler. The low byte is latched when the timer high byte is read to ensure consistent readout.
Table 8. Timer 1 Compare High Byte Register TIM1CMPH
Address 0x24
b7
b6
b5
Content
Reset Value
Access
Bit Description
TCMP[15:8] 0
0
0
R/W
R/W
R/W
TCMP[15:8] : High Byte
b4
b3
b2
b1
b0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
b4
b3
b2
b1
b0
0
R/W
0
R/W
0
R/W
Table 9. Timer 1 Compare Low Byte Register TIM1CMPL
Address 0x25
b7
b6
b5
Content
Reset Value
Access
Bit Description
TCMP[7:0]
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
TCMP[7:0] : Low Byte of Timer Compare Register
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
17/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Table 10. Timer 1 High Byte Register TIM1RH
Address 0x26
b7
b6
b5
b4
b3
b2
b1
b0
Content
Reset Value
Access
Bit Description
TR[15:8]
0
0
0
0
0
0
R
R
R
R
R
R
TR[15:8] : High Byte of Timer Register, access latches TIM1RL
0
R
0
R
Table 11. Timer 1 Low Byte Register TIM1RL
Address 0x27
b7
b6
b5
b4
Content
Reset Value
Access
Bit Description
TR[7:0]
0
0
0
0
R
R
R
R
TR[7:0] : Low Byte of Timer Register
b3
b2
b1
b0
0
R
0
R
0
R
0
R
b3
b2
b1
b0
Table 12. Timer 1 Status Register TIM1STAT
Address 0x28
b7
Content
Reset Value
Access
OCF
TOF
0
0
0
0
0
0
0
0
R
R
R/W
R
R
R
R
R
OCF : Flag for Output Compare. Set by timer hardware when values of TIM1RH/TIM1RL
and of TIM1CMPH/TIM1CMPL register match. No further comparison is made until the
OCF bit is cleared by reading of TIM1CMPL register.
TOF : Flag for Timer Overflow. Set by timer hardware, cleared by writing a '1' to TOF bit.
Bit Description
b6
b5
b4
Table 13. Timer 1 Control Register TIM1CTRL
Address 0x29
b7
b6
b5
b4
b3
b2
b1
b0
Content
Reset Value
Access
0
R
OCIE
0
R/W
TOFIE
0
R/W
INTD
1
R/W
0
R
PRE[1:0]
0
R/W
0
R/W
0
R
b3
b2
b1
b0
0
R/W
0
R/W
0
R/W
Bit Description
OCIE : Interrupt Enable for Output Compare
TOFIE : Interrupt Enable for Timer Overflow
INTD : Interrupt Disable for all Timer Interrupts
1 : Disables all
PRE[1:0] : Selects Prescaler for Timer Register
00 : Counter incremented with fOSC / 2
01 : Counter incremented with fOSC / 4
10 : Counter incremented with fOSC / 8
11 : Counter incremented with fOSC / 16
Table 14. Timer 2 Compare High Byte Register TIM2CMPH
Address 0x2A
b7
b6
b5
b4
Content
Reset Value
Access
Bit Description
TCMP[15:8] 0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
TCMP[15:8] : High Byte of Timer Compare Register
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
18/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Table 15. Timer 2 Compare Low Byte Register TIM2CMPL
Address 0x2B
b7
b6
b5
b4
b3
Content
Reset Value
Access
Bit Description
TCMP[7:0]
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
TCMP[7:0] : Low Byte of Timer Compare Register
b2
b1
b0
0
R/W
0
R/W
0
R/W
Table 16. Timer 2 High Byte Register TIM2RH
Address 0x2C
b7
b6
b5
b4
b3
b2
b1
b0
Content
Reset Value
Internal Access
External Access
Bit Description
TR[15:0]
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
TR[15:0] : High Byte of Timer Register 2, access latches TIM2RL
Table 17.Timer 2 Low Byte Register TIM2RL
Address 0x2D
b7
b6
b5
b4
Content
Reset Value
Access
Bit Description
TR[7:0]
0
0
0
0
R
R
R
R
TR[7:0] : Low Byte of Timer Register 2
b3
b2
b1
b0
0
R
0
R
0
R
0
R
b3
b2
b1
b0
Table 18. Timer 2 Status Register TIM2STAT
Address 0x2E
b7
Content
Reset Value
Access
OCF
TOF
0
0
0
0
0
0
0
0
R
R
R/W
R
R
R
R
R
OCF : Flag for Output Compare. Set by timer hardware when values of TIM2RH / TIM2RL
and of TIM2CMPH / TIM2CMPL register match. No further comparison is made until the
OCF bit is cleared by reading of TIM2CMPL register.
TOF : Flag for Timer Overflow. Set by timer hardware, cleared by writing '1' to TOF bit
Bit Description
b6
b5
b4
Table 19. Timer 2 Control Register TIM2CTRL
Address 0x2F
b7
Content
Reset Value
Access
OCIE
TOFIE
INTD
0
0
0
1
0
R
R/W
R/W
R/W
R
OCIE : Interrupt Enable for Output Compare
TOFIE : Interrupt Enable for Timer Overflow
INTD : Interrupt Disable for all Timer Interrupts
PRE[1:0] : Selects the Prescaler for Timer Register
00 : Counter incremented with fOSC / 2
01 : Counter incremented with fOSC / 4
10 : Counter incremented with fOSC / 8
11 : Counter incremented with fOSC / 16
Bit Description
b6
b5
b4
b3
b2
b1
b0
PRE[1:0]
0
R/W
0
R/W
0
R
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
19/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
8 Ultrasonic Transducer Driver
8.1 Overview
The transducer is powered by a push-pull center-tapped
transformer for maximum efficiency and reduced EMIradiation. The transducer power is controlled using an
adjustable current source. Current steering achieves a
more stable sound pressure level over temperature and
frequency. The relationship between the driver current
IDRV and the bits DRV_CUR is given by:
I DRV =I DRV ,minSTEP IDRV⋅DRV_CUR
The driver output current can be varied in 63 steps. The
driver current of E524.11, E524.12, E524.21 and E524.22
can be adjusted from 96mA to 298mA. Range Extended
versions E524.13, E524.14, E524.23 and E524.24 are adjustable from 160mA to 498mA. If higher currents are
required, two GPIO pins can be used to control external
drivers. Figure 5. Transducer Driver shows a typical application utilizing internal drivers DRV1 and DRV2.
Ultrasonic
Figure 5. Transducer Driver
Table 20. Driver Current Configuration Register DRV_CUR
Address 0x406
b7
b6
b5
b4
Content
Reset Value
Access
Bit Description
DRV_CUR[5:0]
0
0
0
0
0
0
R
R
R/W
R/W
R/W
R/W
DRV_CUR[5:0] : Sets driver current with 63 steps of granularity
8.2 Burst Generation
b3
f
The burst generation block provides the internal digital
control signals to the ultrasonic driver DRV1 and DRV2.
During a burst transmission the signals have opposite
polarity. After the burst both DRV1 and DRV2 are off.
The burst length NDRV can be configured between 4 and
64 periods and may be adjusted in steps of 4 periods.
The value of the burst length is given by follow equation:
N DRV =4⋅ BURSTLEN 1
Burst length 'BURSTLEN' is set in Table 21. Burst Configuration Register.
Additionally, the burst frequency is adjustable in Table
22. Burst Frequency Prescaler Register. Values between
0 and 255 are valid. The burst frequency fDRV is calculated by:
SEND=
b2
b1
b0
0
R/W
0
R/W
f OSC
2⋅ BURSTPREDIV 64
With fOSC = 16 MHz, the burst frequency is adjustable
from fDRV = 25kHz to fDRV = 125 kHz.
To calculate the required BURSTPREDIV value :
BURSTPREDIV =
f OSC
−64
2⋅f SEND
Burst lenghts are illustrated in Figure 6. Burst Generation Timing Diagram. The rising edge of the BURSTON
signal is generated by the µC setting the BURSTON bit
to one. The falling edge is generated by the burst generation logic.
For range extended versions E524.13, E524.14, E524.23
and E524.24 there is a short range mode to produce just
one single pulse at DRV1.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
20/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Figure 6. Burst Generation Timing Diagram
Table 21. Burst Configuration Register BURSTCFG
Address 0x03
b7
Content
Reset Value
Internal Access
SHORT
BURSTON BURSTLEN[3:0] 0
0
0
0
0
0
1)
W
R
R
R/W
R/W
R/W
SHORT : Enables Short Range Mode 1)
BURSTON : Write Start Burst; Read Burst Enable
BURSTLEN[3:0] : Number of Periods/Burst = (BURSTLEN+1) * 4
Bit Description
b6
b5
b4
b3
b2
1)
b1
b0
0
R/W
0
R/W
1) Range extended versions E524.13, E524.14, E524.23 and E524.24 only. Write “0” for all other versions.
Table 22. Burst Frequency Prescaler Register BURSTPREDIV
Address 0x04
b7
b6
b5
Content
Reset Value
Internal Access
Bit Description
BURSTPREDIV[7:0]
1
0
0
R/W
R/W
R/W
BURSTPREDIV[7:0] : Set burst frequency
8.3 Short Range Mode
Short range mode enables recognition of close-up obstacles. It reduces ringing time as well as sending power. The short range mode is turned on by the SHORT bit
of BURSTCFG register. Please verify with the transducer
manufacturer if the transducer is able to operate with
single pulses.
8.4 Range Extension
Range extension is available for E524.13, E524.14,
E524.23 and E524.24 only. It increases the maximum
detection distance by approximately 20%. For those
devices driver currents are increased up to 500mA. The
receiver path architecture includes a square law detec-
b4
b3
b2
b1
b0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
tor to improve signal to noise ratio for small signals. Via
GPIO, external drivers can be utilized to further increase
power.
9 Signal Processing
9.1 Overview
The principle of ultrasonic distance measuring is based
on transmitting a pulse and measuring the reflection
time of the received pulse as shown in Figure 7. The relationship between the distance from the transducer
to the object L and the time T it takes to receive the
echo is L = C * T/2, where C is the velocity of sound. The
E524 USPA requires only one transducer which acts as a
transmitter and receives the reflected pulse with a time
delay proportional to the distance to measure.
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ELMOS Semiconductor AG
Data Sheet
21/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Ultrasonic
Sensor
(Transceiver)
Control
Circuit
PulseTransmission
Circuit
Object
Distance : L
Receiving
Circuit
Reflection Time:T
Counter
Circuit
Standard
Oscillator
Circuit
Figure 7. Ultrasonic Distance Measuring
The algorithm to measure the distance is realized in a user application. The signal envelope is found with an echo
detection algorithm as shown in Figure 8. The E524.xx return new envelope values in exactly timed intervals based
on the selected transducer frequency. The interval event “New Envelope Data” is used as the time base to calculate
distance. The flow chart illustrates a basic echo detection scheme using interrupts for the event “New Envelope
Data”. The term echo[n] describes a memory array containing echo envelope values.
Figure 8. Echo Detection Flowchart
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
22/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
The echo signal is picked up at the transducer and goes through a programmable gain stage first. After digitization
with an 8 Bit ADC, the signal is further processed by a digital filter. An optional square law circuit increases signalto-noise ratio before data is sent to the microcontroller.
soc
Frequency
Generator
AING
Clamping
irq
eoc
8bit
ADC
AMP
AINS
Square
Law
Detector
DMF
10
8
AMP : Amplifier with Programmable Gain
ADC : Analog-to-Digital Donverter
DMF : Digital Matched Filter
soc
eoc
irq
10
MUX
8bit μC
EL3.5
8
: Start of Conversion
: End of Conversion
: Filter Interrupt
Figure 9. Echo Signal Receiving Path
9.2 Amplifier
Transducer output signal levels vary by type and application. The differential input of the amplifier minimizes
pickup of unwanted signals. One input is typically used
as signal input while the other input is tied to signal
ground.
The incoming analog echo signal has to be amplified
before it is converted by an ADC. The amplifier gain is
programmable with a range of 31.5dB with 0.5dB resolution to ensure an optimum amplifier output voltage
range. The E524.xx support transducers with a sensitivity from -56.5dB to -88dB. Total gain is calculated using
the following formula:
Gain = 56.5dB + 0.5dB * AMP_GAIN
Gain settings are typically stored in EEPROM. The amplifier output is internally connected to an 8-bit ADC.
Table 23. Aplifier Gain Configuration Register AMP_GAIN
Address 0x405
b7
b6
b5
b4
b3
b2
Content
Reset Value
Access
Bit Description
AMP_GAIN [5:0] 0
0
0
0
0
0
R
R
R/W
R/W
R/W
R/W
AMP_GAIN[5:0] : Sets amplifier gain with 63 steps of granularity.
b1
b0
0
R/W
0
R/W
9.3 Analog-to-Digital Converter (ADC)
The main purpose of the internal ADC is to digitize the
ultrasonic signal. Additionally, the ADC can be programmed to measure the supply voltage, support the
LIN auto-addressing function or to measure a voltage at
pin GPIO4. The GPIO input is useful in applications requiring a temperature sensor to compensate for speed
of sound variations over temperature.
Table 24. ADC Input Select and Control Register ADCIN
Address 0x0A
b7
Content
Reset Value
Access
SEL_GPIO4
SEL_VSUP EOC
SOC
0
0
0
0
0
0
1
0
R
R
R
R
R/W
R/W
R
R/W
SEL_GPIO4 : Select GPIO4 as ADC input
SEL_VSUP : Select VSUP/12 as ADC input
EOC : Read ADC end of conversion, the bit is valid if SOC is read as zero
SOC : Set ADC start of conversion, the bit is set back itself after the ADC has started
Bit Description
b6
b5
b4
b3
b2
b1
b0
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ELMOS Semiconductor AG
Data Sheet
23/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
The ADC 8-bit output is directly available at Register ADCDAT as shown in Table 25. ADC Output Register.
Table 25. ADC Output Register ADCDAT
Address 0x0B
b7
b6
b5
Content
Reset Value
Internal Access
External Access
Bit Description
ADCDOUT[7:0]
0
0
0
R
R
R
R
R
R
ADCDOUT[7:0] : Output Data of ADC
b4
b3
b2
b1
b0
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
9.4 Digital Filter
Following the conversion, the signal is filtered through
a digital filter block. Since the clock of the transducer
driver and the ADC/filter clock are synchronized, the
digital filter finds the sending frequency reliably. The
output of the digitally matched filter (DMF) represents
the envelope of the echo signal. To increase the dynamic range for small echoes the signal can be sent optionally through a square law detector. The resulting envelope signal is then fed to the μC for further analysis as
shown in Figure 9. Echo Signal Receiving Path.
The digital filter has 3 stages: Bandpass input filter, envelope generation stage and a lowpass output filter
as shown in Figure 10. Digital Filtering. The bandpass
bandwidth is set with coefficient k1 and the low pass
corner frequency can be selected with coefficient k2.
As transducers characteristics vary significantly, optimum values for k1 and k2 must be found through experimentation.
ADC
k2
Envelope
10
FILTOUT
k1
FILTER_IRQ
Figure 10. Digital Filtering
To optimize the signal-to-noise ratio, set the bandpass
bandwidth as close as possible to a given burst length.
After sending a burst, the sensor and the transformer
resonance circuit ring at two or more frequencies. This
is partially filtered out by the bandpass filter. As a result, expect peaks and dips in the echo signal during the
early phase of the detection. To counter this, k1 can be
set to a lower value (2 or 3) during the ringing period of
1-2 msec. Special filter design allows glitch free switching of filters coefficients during operation. Table 26. Filter Coefficients lists recommended values for different
burst lengths.
Table 26. Filter Coefficients
Burst Periods
8
16
32
k1 (Receive)
3
4
5
k2 (Receive)
2(3)
2(..4)
2(..5)
The Typical Operating Characteristics show frequency
responses for different filter settings (k1, k2 =1...7) normalized to the transmitter frequency fDRV .
The filter at the output of the envelope generator is
used to smoothen the signal. This is necessary in particular during the burst phase when the first filter has
k1 (Burst)
2
2
2
k2 (Burst)
3
4
4
a wide bandwidth which results in higher noise at the
output of the envelope generator.
The -3dB filter bandwidth Δf for k1, the k1 quality factor Q of the bandpass and the -3dB corner frequency
relative to the transmit frequency fDRV for k2 is illustrated in Table 27. Filter Parameter.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
24/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Table 27. Filter ParameterADC Input Select and Control Register
Filter Coefficients k1, k2
0
1
2
3
4
5
6
7
f SEND
Q=
for k1
Filter Off
n.a.
0.472830
0.218631
0.105584
0.051931
0.025758
0.012828
f DRV
f − 3dB
for k2
f SEND
for k1
Filter Off
n.a.
2.11492
4.57392
9.47115
19.25646
38.82277
77.95330
Filter Off
0.9179315
0.3679600
0.1698662
0.0820065
0.0403312
0.0200043
0.0099626
The filters can be individually turned off by setting k1 or k2 = 0. The theoretical bandwidth for k1 = 1 is beyond the
signal bandwidth. Filter coefficients are set in register FILT_CFG.
An example for calculating the bandwidth for a transducer frequency fDRV = 51 kHz and k1 = 4 is :
∆f =
∆f
⋅f
f DRV
DRV
=0.10556⋅51kHz=5.38kHz
Table 28. Filter Configuration Register FILT_CFG
Address 0x0C
b7
Content
Reset Value
Access
K2[6:4]
0
0
0
R
R/W
R/W
K2[6:4] : Filter Coefficient k2
K1[2:0] : Filter Coefficient k1
Bit Description
b6
b5
b4
0
R/W
The internal filter has an output width of 10 bits. To allow fast access to the data, three output registers are
defined. Close to a burst, only the higher bits found in
FILTOUT1 are of value. For echoes at the end of the detection range, only values up to 8 bit are expected and
found in FILTOUT3.
Using FILTOUT1 attenuates the signal by a factor of 4 as
b3
b2
b1
b0
0
R
K1[2:0]
0
R/W
0
R/W
1
R/W
two LSBs are stripped off. FILTOUT2 attenuates the signal by a factor of 2 with one LSB stripped off. FILTOUT3
does not attenuate the signal.
FILTOUT2 and FILTOUT3 outputs are overflow protected. In overflow, the output of both registers shows a
value of 255. This value can be used for echo recognition by the µC.
Table 29. Digital Filter Output Register FILTOUT1
Address 0x0D
b7
b6
b5
b4
Content
Reset Value
Access
Bit Description
FILTOUT[7:0] 0
0
0
0
R
R
R
R
FILTOUT[7:0] : Upper 8 Bits Filter Output [9:2]
b3
b2
b1
b0
0
R
0
R
0
R
0
R
b3
b2
b1
b0
0
R
0
R
0
R
Table 30. Digital Filter Output Register FILTOUT2
Address 0x0E
b7
b6
b5
b4
Content
Reset Value
Access
Bit Description
FILTOUT[7:0] 0
0
0
0
0
R
R
R
R
R
FILTOUT[7:0] : Middle 8 Bits Filter Output [8:1]
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
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QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Table 31. Digital Filter Output Register FILTOUT3
Address 0x0F
b7
b6
b5
b4
Content
Reset Value
Access
Bit Description
FILTOUT[7:0] 0
0
0
0
R
R
R
R
FILTOUT[7:0] : Lower 8 Bits Filter Output [7:0]
b3
b2
b1
b0
0
R
0
R
0
R
0
R
One digit of the digital filter output corresponds to
V Digit=
VDDA 1
⋅
≈1.6mV
2
1023
9.5 Square Law Circuit
A square law circuit in the digital filter is useful to increase the dynamic range of small signals. It is available for the
following devices with range extension: E524.13, E524.14, E524.23 and E524.24.
The transfer characteristic is described by:
if (input < k)
input⋅input
output=
2⋅k
else
k
output=input −
2
end
Coefficient k can be set to 0 (linear), 16, 32 or 64. The input signal (in LSB) is squared and then divided by 2*k if the
input is less than k. Otherwise, the output is the input minus ½ k.
The transfer characteristic for k = 0, 16, 32 and 64 is shown in the following figure.
Output signal (LSB)
A square law function aids in the detection of weak signals in the presence of noise. Assuming a noise level of
10 LSB and a signal level of 20 LSB, the signal-to-noiseratio is 2. Applying a square law circuit, the noise level
now is at 100 LSB and the signal at 400 LSB. The signalto-noise ratio has now increased to 4.
The following two figures illustrate how the signal-tonoise ratio improves with the use of a square law circuit.
Input signal (LSB)
Figure 11. Square Law Circuit Transfer Characteristics
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Data Sheet
26/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Figure 12. Small Echo Signal with Linear Detector
Figure 13. Small Echo Signal with Square-Law Detector
In Figure 12 the noise is at 17 LSB and the signal at 38
LSB, a signal-to-noise-ratio is 2.2. Figure 13 shows the
same small signal with square law detection set at
k=32. Noise is now at 5 LSB and the signal at 23 LSB,
an improvement of the signal-to-noise ratio from 2.2
to 4.6.
Coefficients for k are set in the FILTCTRL Register with
K_SQUARE. Figure 14 shows a typical burst and echo
signal.
Figure 14. Typical Burst Envelope
9.6 Digital Filter Interrupt
To synchronize the CPU with the digital filter a flag can
be generated. The flag can be configured to occur once
each transducer period (1/ fDRV) or once each two trans-
ducer periods and subsequently generate an interrupt.
The flag is reset by the CPU. Table 32. FILTCTRL shows
the control bits.
Table 32. Filter Control Register FILTCTRL
Address 0x02
b7
Content
Reset Value
Access
K_SQUARE[5:4]
IRQ
0
0
0
0
0
R
R
R/W
R/W
R
K_SQUARE[5:4] : k Coefficient Square Law Circuit
00 : k = 0, 01 : k = 16, 10 : k = 32, 11 : k = 64
IRQ : Filter interrupt status (not influenced by IRQ_EN)
IRQ_CLR : Clear filter interrupt
IRQ_CONF : Interrupt configuration:
1 : One interrupt each transducer period
0 : One interrupt each two transducer periods
IRQ_EN : Interrupt enable:
0 : No CPU interrupt is generated
1 : Bit IRQ is connected to CPU interrupt
Bit Description
b6
b5
b4
b3
b2
b1
b0
IRQ_CLR
0
W
IRQ_CONF IRQ_EN
0
0
R/W
R/W
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
27/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
9.7 Ringing Frequency Measurement
To diagnose the transducer system health, the frequency of the received signal can be measured during the
ringing time. A fault in the transducer assembly is indicated if the measured frequency differs significantly
from the programmed burst frequency fDRV.
After a burst, the transducer continues to ring. To measure the ringing frequency, a number of periods of this
signal are measured by the ADC and averaged. Each period advances CROSS_COUNT by one. Register START_
COUNT sets the start time of a measurement period
as a number of periods after burst end. STOP_COUNT
defines the number of periods to measure. The number of measured periods is stored in register COUNTS
(COUNTS = CROSS_COUNT - START_COUNT). The difference between CROSS_COUNT and START_COUNT
equals the number measured in COUNTS. The ADC
takes 8 readings per period 1 / fDRV. Register SAMPLESL
and SAMPLESH store the number of readings taken
over the measurement period.
The measured frequency is calculated as follows:
f RING =
8⋅ f DRV⋅COUNTS
SAMPLES
The following timing diagram illustrates a frequency measurement cycle for a burst lenght of 8 periods.
NDRV = 8 periods
DRV1/DRV2
ADCDAT
CROSS_COUNT
1 2 3 4 5 6 ...
17
READY
START_COUNT
4
STOP_COUNT
8
SAMPLES
62
COUNTS
8
Figure 15. Ringing Frequency Measurement Timing
In the above example, the transducer is driven with fDRV
= 58 kHz. The READY bit indicates the begin and end
of a measurment cycle. In the example the start is set
to begin at 4 and measure for 8 periods. At the end of
f
RING
=
the measurement, the number read back from register
SAMPLES is 62. The ringing frequency in the diagram
above for a transducer frequency of is:
8⋅58000⋅8
=59.87kHz
62
Table 33. Frequency Measurement Register START_COUNT
Address 0x412
b7
Content
Reset Value
Access
START_COUNT [4:0] 0
0
0
0
0
0
0
0
R
R
R
R/W
R/W
R/W
R/W
R/W
START_COUNT[4:0] : Sets begin of period. If this number of measured periods in CROSS_
COUNT' is reached, the counter 'SAMPLES' starts to count.
Bit Description
b6
b5
b4
b3
b2
b1
b0
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Data Sheet
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QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Table 34. Frequency Measurement Register STOP_COUNT
Address 0x413
b7
Content
Reset Value
Access
STOP_COUNT [4:0]
0
0
0
0
0
0
0
0
R
R
R
R/W
R/W
R/W
R/W
R/W
STOP_COUNT[4:0] : Sets end of period. If this number of measured periods in CROSS_
COUNT' is reached, the counter 'SAMPLES' stops to count.
Bit Description
b6
b5
b4
b3
b2
b1
b0
Table 35. Frequency Measurement Register CROSS_COUNT
Address 0x411
b7
b6
b5
b4
b3
b2
b1
Content
Reset Value
Access
Bit Description
CROSS_COUNT [5:0] 0
0
0
0
0
0
0
R
R
R
R
R
R
R
CROSS_COUNT[5:0] : Counted periods measued by ADC after the burst is send.
b0
0
R
Table 36. Frequency Measurement Register SAMPLESL
Address 0x415
b7
b6
b5
b4
b3
b2
b1
Content
Reset Value
Access
Bit Description
SAMPLES [7:0]
0
0
0
0
0
0
0
R
R
R
R
R
R
R
SAMPLES[7:0] : Counted ADC Samples[7:0], measured samples low byte
b0
0
R
Table 37. Frequency Measurement Register SAMPLESH
Address 0x414
b7
Content
Reset Value
Access
READY
SAMPLES [9:8]
0
0
0
0
1
0
0
R
R
R
R
R
R
R
READY : '0' Measurement in progress, '1' Measurement ready
SAMPLES[9:8] : Counted ADC Samples[9:8], measured samples high byte
Bit Description
b6
b5
b4
b3
b2
b1
b0
0
R
Table 38. Frequency Measurement Register COUNTS
Address 0x416
b7
Content
Reset Value
Access
Counts [4:0]
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Counts[4:0] : Counted periods expressed as the difference between CROSS_COUNT and
START_COUNT
Bit Description
b6
b5
b4
b3
b2
b1
b0
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
10 LIN Interface
10.1 LIN Overview and Registers
speed mode. Auto-addressing is available for E524.12,
E524.22,E524.14 and E524.24.
A basic LIN driver stack is available as example code and
part of the ELMOS development kit to speed up software development.
The Local Interconnect Network (LIN 2.1) communication module consists of an SCI interface with auto
baud rate measurement, break detection and receive
/ transmit control. The full-duplex LIN receiver / transmitter support baud rates up to 125 kbps in high-
LIN SCI
Auto Baud Rate
Measurement
Break Detection
µC
RXD
Receive Control
TXD
Transmit Control
BUS_M
LIN
Transceiver
Sense
Amp
R
BUS_S
(Note 1)
Note 1: E524.12, E524.22, E524.14 and E524.24 only
Figure 16. LIN SCI Block Diagram
The E524.xx LIN SCI implementation allows for full duplex operation in 8N1 data format and standard mark/
space NRZ format. The interrupt-driven operation supports four flags: Receiver full, Transmitter empty, Measurement finished and Break character received.
Special LIN support includes a 13 Bit break generation
and an 11 Bit break detection threshold. A fractionaldivide baud rate pre-scaler allows for fine adjustment
of the baud rate. A 16 bit measurement counter can
be used as a mini-timer to measure break and bit times
(useful in baud rate recovery). Baud measurement results can directly be fed into the baud register to adjust
S16
S1
q16 q1
S2
q2
q3
S3
S4
q4
q5
S5
S6
q6
S7
q7
S8
q8
the baud rate (baud self-synchronization with SYNC
byte). A high-speed LIN mode allows an increase of the
transceiver bit transfer up to 125 kbps as an option to
reduce programming time.
The LIN SCI uses a clock whose frequency is 16 times 1/
TBIT. The detection of the start bit takes place at S1 as
shown in Figure 17. LIN SCI Operations. The sampling of
the received signal occurs in the middle of the bit with
three samples. The majority of the samples define the
actual bit level meeting LIN requirements for tBFS, tEBS
and tLBS .
S9
S10 S11
S12
S13 S14
S15
S16
S1
q9 q10 q11 q12 q13 q14 q15 q16 q1
Bit Sampling
Start
1/2 Bit
1/2 Bit
Nominal Bit
RXD
Figure 17. LIN SCI Operations
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QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
tBit
tBit
tBit
TXD
(Input to Transmitting Node)
tBus_dom(max)
VS
(Transceiver Supply
of Transmitting Node)
THRec(max)
THDom(max)
tBus_rec(min)
Thresholds of
Receiving Node 1
LIN Bus Signal
Thresholds of
Receiving Node 2
THRec(min)
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(Output of Receiving Node 1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of Receiving Node 2)
trx_pdr(2)
trx_pdf(2)
Figure 18. LIN Bus Timing
Table 39. SCI Baud Rate Register High SCIBRH
Address 0x10
b7
b6
Content
Reset Value
Access
BD[10:3]
0
0
0
R/W
R/W
R/W
BD[10:3] : SCI Baud Divisor Select
Bit Description
Divisor:
BD=
b5
1
Baudrate
b4
b3
b2
b1
b0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
b3
b2
b1
b0
f OSC
16
Table 40. SCI Baud Rate Register Low SCIBRL
Address 0x11
b7
Content
Reset Value
Access
BD[2:0]
BDFA [4:0] 0
0
1
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BD[2:0] : SCI Baud Divisor select
BDFA[4:0] : SCI Baud Divisor Fine Adjust
These bits select the number of clocks inserted in each 32 output cycle frame to achieve
more timing resolution on the average baud frequency shown as follows:
BDFA[00000] = 0/32 = 0
BDFA[00001] = 1/32 = 0.031
Bit Description
b6
b5
b4
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QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Table 41. SCI Control Register SCICTRL
Address 0x13
b7
Content
Reset Value
Access
TIE
LIN
RIE
BIE
TE
RE
MFIE
SBK
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TIE : TxD Interrupt Enable. Generates interrupt when TDRE is set.
LIN : Selects special LIN support mode:
LIN Break Transmit Enable. 13 bit break symbol instead of 10 bit.
LIN Break Receive Detection Enable. Detects an 11 bit break symbol instead of 10 bit.
RIE : RxD Interrupt Enable. Generates interrupt when RDRF is set.
BIE : Break Detection Interrupt Enable. Generates interrupt when BRF is set.
TE : Transmitter Enable
If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit
shift register continues to shift out. To avoid accidentally cutting off the last frame in a
message, always wait for TDRE to go high after the last frame before clearing TE
RE : Receiver Enable
RE set to '0' suppresses start bit recognition. Setting RE to '1' or ‘0’ during an ongoing transfer can cause erroneous data reception and interrupt generation (RDRF); ignore received
data.
MFIE : Measurement Finish Interrupt Enable. Generates interrupt when MF is set.
SBK : Send Break Bit
Toggling SBK sends one break character. Results in ten logic 0s, respectively 13 logic 0s
if the LIN bit within this register is set). The bit has to be set to high for 6 times tBIT to be
recognized. Toggling implies clearing the SBK bit before the break character has finished
transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 bits respectively 13 bit).
Bit Description
b6
b5
b4
b3
b2
b1
b0
Table 42. SCI Status Byte High SCISTATH
Address 0x14
b7
Content
Reset Value
Access
ABT
AMT
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
ABT : Auto Baud Triggered. Set when new baud value was copied automatically to baud
configuration register after a valid SNYC byte measurement cleared when reading the MSB
of the status word.
AMT : Auto Measurement Triggered. Set when measurement was started automatically
after reception of a valid break cleared when reading MSB of status word.
Bit Description
b6
b5
b4
b3
b2
b1
b0
Table 43. SCI Status Register Flags SCISTATL
Address 0x15
b7
b6
b5
b4
b3
b2
b1
b0
Content
Reset Value
Access
TDRE
1
R
TC
1
R
RDRF
0
R
BRF
0
R
OV
0
R
MRUN
0
R
MF
0
R
FE
0
R
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QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Address 0x15
b7
b6
b5
b4
b3
b2
b1
b0
Bit Description
TDRE : Transmit Data Register Empty. Clear TDRE by writing to SCI data register. Write will
be ignored when transmit register is not empty. Check if TDRE = 1 before writing to transmit register.
TC : Transmit Complete Flag. TC is reset to '0' when a transmission is in progress.
RDRF : Receive Data Register Full Flag. Clear RDRF by reading SCI status with RDRF set and
then reading SCI data register.
BRF : Break Received Flag. Behaves according to LIN-Mode selected.
Clear BRF by reading SCI status with BRF set and then reading SCI data register.
The BR flag will be set when the start bit is followed by 8 bits (respectively 9 when LINMode is set), logic 0 data bits and a logic 0 where the stop bit should be.
When BRF is set also FE and RDRF will be set and the SCI data register is cleared.
OV : Receiver Overrun Detected. Clear OV by reading SCI status with OV set and then reading SCI data register. OV will be set when a received data byte is not read before the data
byte of the next frame or a break character arrives. The second data byte will be disallowed.
MRUN : LIN Measurement Running
MF : Measurement Finish flag. Clear MF by read accessing the measurement counter
FE : Framing Error Flag. FE is set when the logic does not detect a logic 1 where the stop bit
should be. FE is set and reset together with RDRF.
Note 1) RDRF will be set in data or break reception. In data reception, at 1/8 of nominal bit length after the recognized stop bit.
Since the bits are sampled in the middle of a nominal bit length the flags and IRQ will be set after the estimated end of
the active stop bit. In break reception see BRF description below.
Note 2) Flag generation (incl. BRF) will be suppressed when AUTO_MEAS (b2 AM, Table 46) is set.
Table 44. SCI Data (In/Out) SCIDATA
Address 0x17
b7
b6
b5
b4
b3
b2
b1
Content
Reset Value
Access
Bit Description
SCIDATA[7:0]
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCIDATA[7:0] : SCI data register, write for transmitting byte, read received byte
b0
0
R/W
Table 45. SCI Measurement Control Byte High SCIMEASCTRH
Address 0x18
b7
Content
Reset Value
Access
DBC[5:0] 0
0
1
0
1
0
0
0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
DBC[5:0] : DBC - debouncing filter threshold for baud rate measurement (MMODE=0)
DBC form the upper threshold value for the debouncing filter. Debouncing filter is reset to
81 which results in minimum filter delay of
Bit Description
b6
b5
b4
T DELAY= DBC [ 5: 0]⋅21
⋅
b3
b2
b1
b0
1
f OSC
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QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Table 46. SCI Measurement Control Byte Low SCIMEASCTRL
Address 0x19
b7
Content
Reset Value
Access
AB
AM
MMODE MEN
0
0
0
0
0
0
0
0
R
R
R
R
R/W
R/W
R/W
R/W
AB : Auto Baud. Automatically copy baud measurement result to baud configuration register after a valid baud measurement (expecting SYNC Byte). AUTO_BAUD_TRIGGERED will
be set. (Note 1)
AM : Auto Baud Measurement. Automatically start a baud rate measurement after reception of a valid break. AUTO_MEAS_TRIGGERED will be set. (Note 2)
MMODE : Measurement Mode Select
If set to ‘0’: Baud rate measurement; counter runs with system clock and measures time
between 4 falling edges (8 bit length are measured). Debouncer is enabled.
Note: Baud measurement expects a 0x55 data byte to measure which is the SYNC byte in
the LIN protocol.
If set to ‘1’: Break time measurement; counter runs with 16x baud rate, measures time
when RxD line is zero. (Note 3)
MEN : Measurement Enable
Set to '1' to start a measurement. When measurement is finished, MEN bit will be cleared
automatically. (Note 4)
Bit Description
b6
b5
b4
b3
b2
b1
b0
Note 1) During baud measurement the receiver is disabled and therefore no data will be received, only the measurement logic
is active which will generate a measurement finish flag (configurable as interrupt).
Note 2) AUTO_MEAS mode suppresses the specific flag generation (See SCI_status BRF bit, Table 43).
Note 3) Only applicable with MEN control bit.
Note 4) When AUTO_MEAS (AM) bit is set MEN must not be used. Writing a '0' to MEN resets measurement logic and allows
proper restart.
Table 47. SCI Measurement Data High Byte SCIMEASDATH
Address 0x1A
b7
Content
Reset Value
Access
MC[15:8]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MC[15:8] : Measurement Counter. Counter is cleared by every start of a new measurement.
When measurement counter overflows the counter value is 0xFFFF. Measurement will be
stopped (MF flag set). Measurement should be repeated with an adapted baud rate setting.
Bit Description
b6
b5
b4
b3
b2
b1
b0
Note) In Baud measurement mode, results of the baud measurement (8 bit length) are divided by 4 and rounded (resulting 2 bit
length value). The resulting 16 bit can be fed into the baud divider register to adjust baud rate
Table 48. SCI Measurement Data Low Byte SCIMEASDATL
Address 0x1B
b7
b6
b5
b4
b3
b2
b1
b0
Content
Reset Value
Access
Bit Description
MC[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MC[7:0] : Measurement Counter. See Table 47. SCI Measurement Data High Byte
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QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
10.2 LIN Receiver
The LIN receiver section is illustrated below. A low pass
filter at the input filters out high frequency components and assures faultless communication even under severe RF conditions. The reference voltage of the
comparator is derived from the supply voltage. The resulting duty cycle of close to 50 % is achieved under all
supply conditions. A debounce filter eliminates spikes
in the digital SCI receiver signal to ensure proper decoding of received data even in harsh automotive environments. In high-speed mode, the debounce filter is bypassed.
VS
High Speed RxD
R2
Comp1
R1
BUS_M
Debounce
R3
RxD
C1
Figure 19. LIN Receiver
10.3 LIN Transmitter
All USPA E524.xx devices communicate with the ECU
via a single-wire LIN 2.1 bus. Some devices support LIN
auto-addressing and all devices support a 125kbps high
speed LIN mode for the initial programming of the device. Shown in Figure 20. LIN Transmitter, the feedback
capacitor C1 controls the slew rate to minimize electrical noise on the bus line. Both negative and positive
edges are regulated, however, the positive edge is only
controlled when the slew rate is higher than the time
constant on the bus pin. The time constant is derived
of the capacitance and wiring of all nodes connected
to the bus.
The output stage is protected against a short circuit to
VBAT with a current limiting circuit. Diode D2 protects
the transmitter against loss of ground minimizing excessive current on the bus lines when the ground line is
interrupted. The recessive output voltage is defined by
diode D1 and pull-up resistance. M1 and D2 generate
the dominant voltage.
VSUP
D1
RPULLUP
VDD_INT
BUS_M
I1
D2
C1
TxD
M1
B
I2
Current
Limit
R3
GNDB
Figure 20. LIN Transmitter
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QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
10.4 LIN Mode Configuration
Register LIN_MODE is used to select between the normal and high speed LIN mode. The high speed LIN mode
allows a transceiver baud rate up to 125 kBaud. High
speed mode reduces programming time in end-of-line
and maintance operations and is not recommended to
be used when measuring distances because of the in-
crease of noise on the bus line.
Additionally the LIN / SCI module can be disabled in order to control the transceiver directly by CPU. This enables the E524.xx to operate on custom protocols with
edge detection at RXD.
Table 49. LIN Mode Configuration Register LIN_MODE
Address 0x1E
b7
Content
Reset Value
Access
RXD_FIRQ RXD_RIRQ RXD_IRQ_EN
HS_EN
SCI_DIS
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
RXD_FIRQ : RXD falling edge interrupt.
0: No interrupt
1: Falling edge on RXD
the interrupt bit is cleared by writing a '0' to this bit
RXD_RIRQ : RXD rising edge interrupt.
0: No interrupt
1: Rising edge on RXD
the interrupt bit is cleared by writing a '0' to this bit
RXD_IRQ_EN : enable RXD input interrupt
0: Interrupt disabled
1: Interrupt enabled
HS_EN : enable high speed transceiver:
0 : Normal LIN mode
1 : High speed mode enabled
SCI_DIS : disable internal SCI module:
0 : SCI module active
1 : SCI module disabled, LIN transmitter controlled by bit 1 'TXD'
TXD : CPU access to BUS (only if SCI_DIS=1):
0 : Bus dominant
1 : Bus recessive
RXD : Read current bus state
Bit Description
b6
b5
b4
b3
b2
b1
b0
TXD
1
R/W
RXD
R
10.5 LIN Auto-Addressing
This feature allows functionally identical LIN nodes to
be used off the shelf in a plug-and-play fashion without
manual intervention or DIP switch pre-programming of
the address. At start-up an ECU software routine determines the LIN slave’s node position in the network
and assigns a respective address. The address is stored
in EEPROM to shorten start-up time in operation. This
proven ELMOS proprietary method is also called SlaveNode-Position-Detection (SNPD) and is employed to
automatically address LIN nodes.
LIN Auto-addressing is available for family members
E524.12, E524.14, E524.22 through E524.24 and is
ready-to-use through the ELMOS Boot Manager.
Table 50. LIN Auto-Addressing Register LINAA
Address 0x1F
b7
Content
Reset Value
Access
I2MEN
ON30K
0
0
0
0
1
R
R
R
R/W
R/W
I2MEN 1 : Activates 2mA current source of LIN bus
ON30K 1 : Activates pull-up resistor on LIN bus
AAEN 1 : LIN Auto-addressing enable
EOC : Read ADC end of conversion
SOC : Set ADC start of conversion
Bit Description
b6
b5
b4
b3
b2
b1
b0
AAEN
0
R/W
EOC
0
R
SOC
0
W
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Data Sheet
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QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Auto-addressing LIN nodes remain compatible with LIN
2.1 as outlined in the Electrical Characteristics section.
The auto-addressing slaves detect their relative position
within a bus system without external components. Internally to each E524.xx slave, a shunt resistor between
pins BUS_M and BUS_S nodes allows to measure cur-
rent on the LIN bus while a 2mA pull-up current source
enables each E524.xx to signal during sync break.
The auto-addressing slaves within such a bus configuration have to be daisy-chained. Connect pin BUS_M
towards the master (ECU) side and pin BUS_N towards
slaves lower in the chain as shown in Figure 21.
Figure 21. LIN Bus Auto-addressing Architecture
In the example of Figure 21, the ECU terminates the bus
on the left and is followed by a group of addressable
slaves with individual auto-addressing. Standard and
auto-addressing slaves can be positioned as the actual
application requires it as long as the auto-addressing
nodes are connected in series.
The start of the addressing sequence is initialized by the
ECU. A command is sent to the slaves telling them the
addressing sequence starts with the next sync break.
During the next sync break each slave starts its se-
quence. The sequence is divided up in measuring the
offset current on the bus line, measuring the bus load
and, depending on the bus load, turning on the current
source for the detection of the last not addressed slave
in the line.
It is recommended to use a threshold value of 1 mA
for the decision illustrated in the following flow chart.
This gives maximum noise immunity to the low value
(0 mA) and the high value (2 mA) if only one other slave
is behind, see Figure 22.
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Data Sheet
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QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
START
Step 1
Master sends autoaddressing
command
All slaves
detect synch break
All addressable slaves
switch off 30kΩ LIN pullup
Y
Slave already addressed ?
N
Step 2
Measure bus current ISHUNT1
Step 3
All not addressed slaves
switch on 30kΩ LIN pullup
Step 4
Measure bus current ISHUNT2
Step 5
Calculate difference
IDIFF21 = ISHUNT2 - ISHUNT1
Y
IDIFF21 > threshold ?
N
All not addressed slaves
switch on 2mA pullup source
Switch off 30kΩ LIN pullup
and wait for end of procedure
Step 6
Measure bus current ISHUNT3
Step 7
Calculate difference
IDIFF31 = ISHUNT3 - ISHUNT1
Y
IDIFF31 > threshold ?
N
Slave saves address contained
in autoaddressing command
All slaves
switch off 2mA pullup source
and switch on 30kΩ LIN pullup
Master checks:
all slaves addressed?
N
Y
STOP
Figure 22. Flowchart Auto-Addressing
In order to assure different steps of the auto-addressing sequence are executed synchronously by all slaves, the
timing scheme for sync breaks are defined as time tBIT,SLAVE. Figure 23 illustrates the sequence of events during
sync break.
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QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
t
0
4
13
8
BIT
14
Master
30k Ω pullup resistor and
Pullup config.
All pullups off
Measurements
I
Step 1
30k Ω
I
SHUNT1
Step 2
2mA pullup source
pullup resistor
Step 3
30k Ω pullup resistor
I
SHUNT2
Step 4
Step 5
SHUNT3
Step 6
Step 7
Synch break with autoaddressing cycle
Figure 23. Timing Diagram Auto-addressing Process
11 General Purpose Input Output (GPIO)
Four bidirectional General Purpose Input Output (GPIO)
ports support positive and negative edge interrupts
and contain pull-up/down circuitry in input mode.
Pins GPIO1 and GPIO2 are always available. Pins GPIO3
and GPIO4 are shared with a JTAG (Joint Test Interface
Group) interface. Connecting pin TMEN to GNDD disables the JTAG CPU debug mode and allows access to the
GPIO3 and GPIO4 functions.
GPIO1 and GPIO2 are designated to control external
switches to drive transducers whose current demand
exceeds that of internal transducer drivers DRV1 and
DRV2. The function DRVOUT_EN is further described in
Table 56.
If enabled, GPIO3 and GPIO4 are available as digital
I/O ports as described in the GPIO registers. GPIO4 is
also configurable as an analog input pin for the internal ADC.
Table 51. GPIO Data Register GPIO_IO
Address 0x20
Content
Reset Value
Access
Bit Description
b7
b6
b5
0
0
0
R
R
R
GPIOn_IO :
Write: Set Output Data
Read: Read Pin State
b4
b3
b2
b1
b0
0
R
GPIO4_IO GPIO3_IO GPIO2_IO GPIO1_IO
0
0
0
0
R/W
R/W
R/W
R/W
Table 52. GPIO Configuration Register GPIO_CFG
Address 0x400
b7
Content
GPIO3_
GPIO2_
GPIO4_PD GPIO3_PD GPIO2_PD GPIO1_PD GPIO4_
DIR
DIR
DIR
1
1
1
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
GPIOn_PD : Enable Pull Down at GPIOn (only if DIR=0 and GPIOn_PU=0)
0 : Pull Down Disable
1 : Pull Down Enable
Reset Value
Access
Bit Description
b6
b5
b4
b3
b2
b1
b0
GPIO1_
DIR
0
R/W
GPIOn_DIR : Select Direction for GPIOn
1 : Output
0 : Input
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QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Table 53. GPIO Pull-up Configuration Register GPIO_CFG_PU
Address 0x417
Content
Reset Value
Access
Bit Description
b7
b6
b5
b4
0
0
0
0
R
R
R
R
GPIOn_PU : Enable pull up at GPIOn
0 : Pull-up Disable
1 : Pull-up Enable
b3
b2
b1
b0
GPIO4_PU
0
R/W
GPIO3_PU
0
R/W
GPIO2_PU
0
R/W
GPIO1_PU
0
R/W
Table 54. GPIO Interrupt Status Register GPIO_IRQ
Address 0x21
b7
Content
GPIO4_
GPIO3_
GPIO2_
GPIO1_
GPIO4_
RIRQ
RIRQ
RIRQ
RIRQ
FIRQ
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
GPIOn_RIRQ : GPIOn rising edge detected (active high)
Write 1 to this bit to clear interrupt
GPIOn_FIRQ : GPIOn falling edge detected (active high)
Write 1 to this bit to clear interrupt
Reset Value
Access
Bit Description
b6
b5
b4
b3
b2
b1
b0
GPIO3_
FIRQ
0
R/W
GPIO2_
FIRQ
0
R/W
GPIO1_
FIRQ
0
R/W
b2
b1
b0
GPIO2_
FIRQ_EN
0
R/W
GPIO1_
FIRQ_EN
0
R/W
Table 55. GPIO Interrupt Configuration Register GPIO_IRQ_CFG
Address 0x401
b7
Content
GPIO4_
GPIO3_
GPIO2_
GPIO1_
GPIO4_
GPIO3_
RIRQ_EN RIRQ_EN RIRQ_EN RIRQ_EN FIRQ_EN FIRQ_EN
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
GPIOn_RIRQ_EN : Enable rising edge interrupt at GPIOn
0 : Interrupt disable
1 : Interrupt enable
GPIOn_FIRQ_EN : enable falling edge interrupt at GPIOn
0 : Interrupt disable
1 : Interrupt enable
Reset Value
Access
Bit Description
b6
b5
b4
b3
Table 56. GPIO Burst-Driver Output Configuration Register GPIO_DRVOUT
Address 0x402
b7
Content
Reset Value
Access
DRVOUT_INV DRVOUT_EN
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R/W
R/W
DRVOUT_INV : Select output level at GPIO1/GPIO2
0 : Active high
1 : Active low
DRVOUT_EN : Connects DRV1/DRV2 control signals to GPIO1/GPIO2 (overwrites GPIO_CFG
for GPIO1/GPIO2)
0 : Disable
1 : Enable
Bit Description
b6
b5
b4
b3
b2
b1
b0
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Data Sheet
40/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
12 Applications Information
12.1 Supply Voltages
The USPA E524.xx family of devices is designed to operate in rugged automotive environments. Protection
against reverse polarity and negative transients at pin
VSUP is accomplished externally as shown in Figure 24.
External components are a series current limiting resistor, a reverse polarity protection diode and two by-pass
capacitors. With this circuit, VSUP sustains a standard
automotive load dump up to 40V.
E524.XX
VBAT
RSUP
DSUP
CSUP1
VSUP
VDDD regulator
CSUP2
VDDD
GNDD
CVDDD
GND
VDDA regulator
VDDD
GNDA
CVDDA
GND
BIAS generator
Supply and Bias
Figure 24. Power Supply
The voltage at VSUP feds an internal power supply
block where analog, digital and bias voltages are generated. Place by-pass capacitors CVDDA and CVDDD close to
analog and digital voltage pins VDDA and VDDD. Both
3.3V supplies are short circuit protected. VDDA is not
designed to power external loads. VDDD can supply external loads up to 4mA.
The 20 pin QFN package contains an exposed die pad
EDP. Connect EDP to GND star point.
12.2 Typical Operating Circuit
The E524.xx supports a wide range of ultrasound transducers and their associated transformers. Circuit diagrams may contain components not manufactured
by ELMOS Semiconductor AG, which are included as
means of illustrating a typical application. Elmos Sem-
iconductor does not endorse or warrant performance
specifications beyond the Electrical Characteristics
for the E524.xx. Please contact Elmos Semiconductor
for further assistance and application notes for sizing
transducer and transformer.
Table 57. External Components
Description
Serial Supply Resistor
Reverse Polarity Protection Diode
Blocking Supply Capacitor 1
Blocking Supply Capacitor 2
Serial Resistor for Transducer Supply
Reservoir Capacitor for Transducer
LIN Ferrite RF Attenuator
Condition
>1/3 Watt 1)
BAS321 general purpose
diode or equivalent
125mW
Stores charge for burst,
>35V
TDK MMZ2012Y202B or
equivalent, 0.5mΩ
Symbol
RSUP
Min
9
DSUP
200
CSUP1
CSUP2
RSUP_TD
1.5
150
CSUP_TD 47
Typ
10
Max
11
Unit
Ω
VReverse
2.2
220
100
100
2.9
290
nF
nF
Ω
μF
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Data Sheet
41/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
Description
Condition
TDK MMZ2012Y202B or
equivalent, 0.5mΩ
LIN Ferrite RF Attenuator
Capacitor at BUS_M Pin
Symbol
Min
Typ
Max
Unit
L_S
100
CSLAVE
120
180
240
pF
RAIN
CAIN1
CAIN2
CVDDA
CVDDD
RTD1
CTD1
90
7
270
70
0.7
100
10
330
100
1.0
6.2
1.2
110
13
390
130
1.3
Ω
pF
pF
nF
μF
kΩ
nF
MHz
Filter Resistor for Transducer Signal
Filter Capacitor for Transducer Signal
Filter Capacitor for Transducer Signal
Blocking Capacitor for Analog Supply
Blocking Capacitor for Digital Supply
Transducer Resonance Resistor
Transducer Resonance Capacitor
1/8W
Transformer
Suggested winding ratio
1:1:7, RDC ≤ 2Ω
2.7
mH
Transducer
Murata MA58AF14-0N
58
kHz
ESR <0.2Ω at 1MHz
ESR <0.2Ω at 1MHz
>100 V 2)
>100 V 2)
1) Replace resistor with inductor to achieve better EMC performance
2) Adjust to transducer
RSUP_TD
CTD1
RTD1
CSUP_TD
Ultrasonic
Transducer
CAIN2
RAIN
CAIN1
DRV1
VBAT
RSUP
DSUP
DRV2
AING
VSUP
AINS
GPIO1
GPIO2
CSUP1
TDO / GPIO3
CSUP2
TDI / GPIO4
Note:
BUS_S E524.x2 and E524.x4 only
VDDD
E524.1x/2x
GNDD
LIN_S
BUS_S
LIN_M
BUS_M
VDDA
GNDB
GNDA
CBUS
GNDP
TMEN
TCK
CVDDD
CVDDA
TMS
Figure 25. Typical Applications Circuit
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ELMOS Semiconductor AG
Data Sheet
42/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
PACKAGE
OUTLINE SPECIFICATION
Date : 04.01.2011
13 Package Information
20 Lead
Quad Flat
Non Leaded
Package
All devices are available in a Pb free,
RoHs compliant
QFN20L5
plastic package
according to JEDEC MO-220 VHHCQM-No.: 08SP0687.03
ASto
2. The Author:
package is
classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020
with a soldering
(QFN20L5)
peak temperature of (260+5)°C.
Package Outline and Dimensions are according JEDEC MO-220 K, variant VHHC-2
Description
Symbol
min
mm
typ
max
min
inch
typ
max
Package Height
A
0.80
0.90
1.00
0.031
0.035
0.039
Stand Off
Thickness of Terminal Leads, including Lead
Finish
Width of Terminal Leads
A1
0.00
0.02
0.05
0.000
0.00079
0.002
A3
--
0.20 REF
--
--
0.0079 REF
--
b
0.25
0.3
0.35
0.010
0.012
0.014
D/E
--
5.00 BSC
--
--
0.197 BSC
--
D2 / E2
3.50
3.65
3.80
0.138
0.144
0.150
e
--
0.65 BSC
--
--
0.026 BSC
--
Length of Terminal for Soldering to Substrate
L
0.35
0.40
0.45
0.014
0.016
0.018
Number of Terminal Positions
N
Package Length / Width
Length / Width of Exposed Pad
Lead Pitch
20
20
Note: the mm values are valid, the inch values contains rounding errors
Note 1: for assembler specific pin1 identification please see QM-document 08SP0363.xx (Pin 1 Specification)
Page 1 of 1
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ELMOS Semiconductor AG
Data Sheet
43/45
QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
PRODUCTION DATA - SEP 03, 2012
14 Marking
14.1 Top Side
ÿÿ
ÿÿ
ÿÿ
ÿÿ
Elmos Logo
52414
XXXSL
YWWR@
Signature
52414
A
XXX
S
L
YWW
R
@
Explanation
ELMOS project number
ELMOS project revision code
Production lot number
Assembler code
Production line code
Year and week of assembly
Mask revision code
ELMOS internal code
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Data Sheet
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QM-No.: 25DS0075E.01
PRODUCTION DATA - SEP 03, 2012
WARNING – Life Support Applications Policy
ELMOS Semiconductor AG is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing ELMOS Semiconductor AG products, to
observe standards of safety, and to avoid situations in which malfunction or failure of an ELMOS Semiconductor
AG Product could cause loss of human life, body injury or damage to property. In the development of your design,
please ensure that ELMOS Semiconductor AG products are used within specified operating ranges as set forth in
the most recent product specifications.
General Disclaimer
Information furnished by ELMOS Semiconductor AG is believed to be accurate and reliable. However, no responsibility is assumed by ELMOS Semiconductor AG for its use, nor for any infringements of patents or other rights of
third parties, which may result from its use. No license is granted by implication or otherwise under any patent or
patent rights of ELMOS Semiconductor AG. ELMOS Semiconductor AG reserves the right to make changes to this
document or the products contained therein without prior notice, to improve performance, reliability, or manufacturability.
Application Disclaimer
Circuit diagrams may contain components not manufactured by ELMOS Semiconductor AG, which are included as
means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. The information in the application examples has been carefully checked and is believed
to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does
not convey to the purchaser of the semiconductor devices described any license under the patent rights of ELMOS
Semiconductor AG or others.
Contact Information
Headquarters
ELMOS Semiconductor AG
Heinrich-Hertz-Str. 1 • D-44227 Dortmund (Germany)
: +492317549100
Regional Sales and Application Support Office Munich
ELMOS Semiconductor AG
Am Geflügelhof 12 • D-85716 Unterschleißheim/Eching (Germany)
: +49893183700
: sales@elmos.com
 : www.elmos.com
Sales and Application Support Office North America
ELMOS NA. Inc.
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Sales and Application Support Office Korea and Japan
ELMOS Korea
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: +82317141131
Sales and Application Support Office China
ELMOS Semiconductor Technology (Shanghai) Co., Ltd.
Unit London, 1BF GC Tower • No. 1088 Yuan Shen Road,
Pudong New District • Shanghai, PR China, 200122
: +862151785178
Sales and Application Support Office Singapore
ELMOS Semiconductor Singapore Pte Ltd.
60 Alexandra Terrace • #09-31 The Comtech • Singapore 118502
: +6566351141
: sales_china@elmos.com
© ELMOS Semiconductor AG, 2012. Reproduction, in part or whole, without the prior written consent of ELMOS Semiconductor AG, is prohibited.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0075E.01
E524.11, E524.12, E524.13, E524.14 – E524.21, E524.22, E524.23, E524.24
LIN SMART ULTRASONIC PARKING ASSIST
Mouser Electronics
Authorized Distributor
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