ISSN 1 746-7233, England, UK
World Journal of Modelling and Simulation
Vol. 6 (2010) No. 4, pp. 281-290
A new Space-Vector Pulse Width Modulation Algorithm for multilevel
inverters
P. Satish Kumar1∗ , J. Amarnath2 , S. V. L. Narasimham3
2
1
Department of Electrical Engineering, Osmania University, Hyderabad 500007, India
Department of Electrical & Electronics Engineering, J. N. T. University, Hyderabad 500085, India
3
School of Information Technology, J. N. T. University, Hyderabad 500085, India
(Received July 30 2009, Accepted June 15 2010)
Abstract. This paper proposed a new Space Vector Pulse Width Modulation (SVPWM) algorithm for multilevel neutral point clamped inverter. The SVPWM method is an advanced, computation intensive PWM
method and is also possibly the best among all the PWM techniques for variable frequency drive applications.
The SVPWM involves the sector identification, determination of switching voltage vectors, switching vector
sequence and dwelling time calculations. But as the level of the inverter increases, the sector identification,
switching vector determination and dwelling time calculation becomes more complex. The computational
complexity and execution time increases. In the proposed method, a correction to the duty cycles of reference
vector is applied to easily identify the location of reference vector in each region of multi-level inverter. Then
the appropriate switching sequence of the identified region and calculation of switching times for each state
with the obtained duty cycles are estimated. The scheme can be extended to high-level inverters. Based on the
above method the simulation results have been presented and analyzed for six-level and seven-level neutral
point clamped inverters. The total harmonic distortion have been calculated and compared with lower levels
also. The results have been good agreement with the published work.
Keywords: multi-level inverters, SVPWM, neutral point clamped inverter, induction motor, THD
1
Introduction
Multilevel Inverter technology finds significant applications in the area of high-power medium-voltage
energy control. Multilevel inverters generate sinusoidal voltages from discrete voltage levels and pulse width
modulation strategies accomplish this task of generating sinusoids of variable voltage and frequencies. The
two main techniques of PWM generation for multilevel inverters are Sine-triangle PWM and Space Vector
PWM. SVPWM involves synthesizing the reference voltage space vector by switching among the three nearest voltage space vectors[14] . Space Vector PWM is considered a better technique of PWM implementation
owing to its associated advantages of (1) Better fundamental output voltage. (2) Better harmonic performance.
(3) Easy implementation in Digital Signal Processor and Microcontrollers. The implementation of SVPWM
involves (1) Identification of the sector in which the tip of the reference vector lies. (2) Determination of the
three nearest voltage space vectors. (3) Determination of the duration of each of these switching voltage space
vectors and (4) Choosing an optimized switching sequence. The sector identification can be done by using
coordinate transformation of the reference vector into a two dimensional coordinate system. The sector can
also be determined by resolving the reference phase vector along a, b and c axis and by repeated comparison
with discrete phase voltages. After identifying the sector, the voltage vectors at the vertices of the sector are
to be determined. Once the switching voltage space vectors are determined the switching sequences can be
identified using lookup tables[6] . The calculations of the duration of the voltage vectors can be simplified by
∗
Corresponding author. E-mail address: satish 8020@yahoo.co.in.
Published by World Academic Press, World Academic Union
sequence. The sector identification can be done by using coordinate transformation of the reference vector
into a two dimensional
The sector :can
alsoSpace-Vector
be determined
byWidth
resolving
the reference
P. Kumar & coordinate
J. Amarnathsystem.
& S. Narasimham
A new
Pulse
Modulation
Algorithm
phase vector along a, b and c axis and by repeated comparison with discrete phase voltages. After
mapping
the identified
sector
to a sector
two-level
inverter.
To obtain
optimum switching,
identifying
the sector,
thecorrespond
voltage vectors
at the of
vertices
of the
sector are
to be determined.
Once the the
voltage
vectors voltage
are to bespace
switched
respective
a sequence
such
that only
onelookup
switching
switching
vectorsforaretheir
determined
thedurations,
switching in
sequences
can be
identified
using
[9, 15, 17] .
occurstables
as the[5].
inverter
moves
from
one
switching
state
to
another
The calculations of the duration of the voltage vectors can be simplified by mapping the
But
as thesector
levelcorrespond
of the inverter
increases,
the sector
identification,
switching
vector the
determination
identified
to a sector
of two-level
inverter.
To obtain optimum
switching,
voltage
vectors are
be switchedbecomes
for their more
respective
durations,
in a sequence such
that onlyand
oneexecution
switchingtime
and dwelling
timeto calculation
complex.
The computational
complexity
[8] . as
occurs
theduty
inverter
moves
from one switching
state to
another
increases
The
cycles
of reference
voltage vector
will
be m[8-10].
1 , m2 and 1 − (m1 + m2 ). The values of
asuseful
the level
the inverter
the sector
identification,
vector determination
and
m1 and mBut
in of
identifying
theincreases,
region where
reference
vector isswitching
located, which
is the major problem
2 are
time calculation
more complex.
The to
computational
complexity
and execution
in casedwelling
of multi-level
inverters.becomes
In this paper,
a correction
the duty cycles
of reference
vector istime
applied
m
and
1-(m
+m
).
The
values
of
increases
[13].
The
duty
cycles
of
reference
voltage
vector
will
be
m
1,
2
1
2
to easily identify the location of reference vector in each region of multi-level inverter. Then the appropriate
m
and
m
are
useful
in
identifying
the
region
where
reference
vector
is
located,
which
is
the
major
1 sequence
2
switching
of the identified region and calculation of switching times for each state with the obtained
problem
in
case
of multi-level
Inalgorithm
this paper, can
a correction
to thetoduty
cycles
of reference
duty cycles are estimated.
This newinverters.
SVPWM
be extended
higher
level
inverters vector
also. is
applied to easily identify the location of reference vector in each region of multi-level inverter. Then the
appropriate switching sequence of the identified region and calculation of switching times for each state
with the point
obtained
duty cycles
are estimated.
This new SVPWM algorithm can be extended to higher level
2 Neutral
clamped
multilevel
inverters
inverters also.
282
In these inverters, the voltage across semiconductor switches is limited by diodes connected to various
2. Neutral Point Clamped Multilevel Inverters
DC levels as such it is called Diode Clamed Multilevel inverters. According to the original invention, the
In can
these
voltage
across
switches
limitedofbycapacitors
diodes connected
various
concept
beinverters,
extendedthe
to any
number
of semiconductor
levels by increasing
the is
number
addition to
across
source
DC
levels
as
such
it
is
called
Diode
Clamed
Multilevel
inverters.
According
to
the
original
invention,
the
dc-bus. Early descriptions of this topology were limited to three-levels where two capacitors are connected
can resulting
be extended
to any
number of
levels
increasinglevel
the number
capacitors
across
acrossconcept
the dc bus
in one
additional
level.
Thebyadditional
was theofneutral
pointaddition
of the dc
bus, so
source
dc-bus.
Early
descriptions
of
this
topology
were
limited
to
three-levels
where
two
capacitors
are
the terminology Neutral Point Clamped (NPC) inverter was introduced. Due to capacitor voltage balancing
connected across the dc bus resulting in one additional level. The additional level was the neutral point of
issues, the diode-clamped inverter implementation has been mostly limited to the three- level. Because of
the dc bus, so the terminology Neutral Point Clamped (NPC) inverter was introduced. Due to capacitor
industrial developments over the past several years, the three-level inverter is now used extensively in industry
voltage balancing issues, the diode-clamped inverter implementation has been mostly limited to the threeapplications. The functional diagram of an n-level NPC inverter utilizing single-pole n-throw switches is
level. Because of industrial developments over the past several years, the three-level inverter is now used
shown in Fig. 1. To result a defined output voltage, (n − 1) consecutive switches of each leg must be in the
extensively in industry applications. The functional diagram of an n-level NPC inverter utilizing singlepole n-throw switches is shown in Fig. 1.
(n-1)
+
Vc(n-1)
2
Vdc
-
Vc2
Sa(n-1)
Sb(n-1)
Sc(n-1)
1
Vc1
0
a
b
c
Fig.
Functionaldiagram
diagramof
ofn-level
n-level NPC
NPC Inverter
Fig.
1. 1:
Functional
inverter
To result a defined output voltage, (n-1) consecutive switches of each leg must be in the On-state. All
On-state.
All possible
combinations
of the
above functional
can be summarized
possible
combinations
of the above
functional
diagram candiagram
be summarized
by the Eq.1. by the Eq. (1).
n
X
Sij = 1 with i = {a, b, c}.
(1)
j=1
The variables Sij are the control functions of the single-pole n-throw switches. These variables define
the position of switches, so that they have the unity value when the i output is connected to j point; other
wise they are zero. Referring all of the voltages to the lower DC-link voltage level (“0” reference) each output
voltage consists of contributions by a determined number of consecutive capacitors:


j
n
X
X
Sij
Vi0 =
V cp  with i = {a, b, c}.
(2)
j=1
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p=1
283
World Journal of Modelling and Simulation, Vol. 6 (2010) No. 4, pp. 281-290
When balanced distribution of DC-link voltage among the capacitors is assumed:
n
Vi0 =
V dc X
jSij
n−1
with
i = {a, b, c}.
(3)
j=1
In 1980s, three-level NPC inverter is most practical and widely studied multilevel inverter topology. One
application of the multilevel diode-clamped inverter is an interface between a high-voltage dc transmission line
and an ac transmission line. Another application would be as a variable speed drive for high-power mediumvoltage (2.4 kV to 13.8 kV ) motor.
The advantages of NPC inverter are:
(1) All of the phases share a common dc bus, which minimizes the capacitance requirements of the
inverter. For this reason, a back-to-back topology is not only possible but also practical for uses such as a highvoltage back-to-back inter-connection or an adjustable speed drive. (2) The capacitors can be pre-charged as
a group. (3) Efficiency is high for fundamental frequency switching.
Fig. 2. Functional diagram of six-level NPC inverter
The six-level neutral point clamped inverter is as shown in Fig. 2. But in case of seven-level inverters six
switches from each phase-leg will be ON at any point of time to produce predetermined output at phases. The
possible switching combinations will be 343.
3
Space Vector Pulse Width Modulation for multi-level inverters
Space Vector PWM (SVPWM) is quite different from other PWM techniques. With other PWM techniques, the inverter can be thought of as three separate stages, which create each phase wave form separately.
However, the SVPWM treats inverter as a single unit with inverter in specific unique state[6] . Modulation is
achieved by switching the state of the inverter. SVPWM is a digital modulating technique where the objective
is to generate PWM load line voltages that are in average equal to given (or reference) load line voltages. This
is done in each sampling period by properly selecting the switching states of the inverter and the calculation
of the appropriate time period for each state. The SVPWM is advanced and, computation-intensive PWM
method.
The space vector (Vs ) constituted by the pole voltages of inverter Vaz , Vbz and Vcz with 120◦ phase
displacement can be defined as:
Vs = Vaz + Vbz exp[j(2π/3)] + Vcz exp[j(4π/3)].
(4)
The space vector, Vs can be resolved into two rectangular components namely Vα and Vβ as indicated below:
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284
P. Kumar & J. Amarnath & S. Narasimham: A new Space-Vector Pulse Width Modulation Algorithm
Table 1. General characteristics of multi-level inverters
NPC inverter
a
b
c
d
e
3
3
3
n-level
6(n − 1) (n − 1) n
n − (n − 1)
(n − 1)3
2-level
6
1
8
7
1
3-level
12
2
27
19
8
4-level
18
3
64
37
27
5-level
24
4
125
61
64
6-level
30
5
216
91
125
7-level
36
6
343
127
216
a : number of switches with free wheeling diodes
a : number of consecutive switches of each leg to be in ON-state
b : number of different voltage states of the inverter
c : number of switches with free wheeling diodes
d : number of unique voltage states of the inverter
e : number of redundant voltage states of the inverter
g : phase voltage levels
Vs = Vα + jVβ ,
"
1
2 1 −2
Vα
√
=
3
Vβ
3 0
2
f
2n − 1
3
5
7
9
11
13
g
4n − 3
5
9
13
17
21
25
(5)
− 21
√
−
2
3
# V 
an
 Vbn 
Vcn
(6)
Equating volt-seconds along α axis gives:
Vs cos α × Ts = Vdc × T1 + (Vdc cos 60◦ ) × T2 .
(7)
Equating volt-seconds along β axis gives:
Vs sin α × Ts = (Vdc sin 60◦ ) × T2 .
(8)
Solving Eq. (7) and Eq. (8) gives the values for the on-time periods T1 , T2 and T0 are
T1 =
Vs × Ts × sin(π/3 − α)
,
Vdc × sin(π/3)
T2 =
Vs × T2 × sin α
,
Vdc × sin(π/3)
T0 = Ts − (T1 + T2 ).
(9)
In multilevel inverters the reference voltage vector can be reproduced in the average sense by switching
amongst the inverter states situated at the vertices, which are in closest proximity to it. In case of two-level
inverter, the identification of reference vector location in a Sector is straight forward. However, in higher level
inverter, the existence of more than one number of regions in Sector will require additional mathematical
computation to identify the region where the reference vector is located. The duty cycles (ON time for each
state) will be found by equating volt-seconds of reference voltage with nearest three states.
m = d 1 V1 + d 2 V2 + d 3 V3 ,
(10)
where d1 , d2 and d3 are duty cycles of nearest voltage vectors V1 , V2 and V3 and ‘m’ is the voltage reference
vector.
Calculation of duty cycles:
The vector states at vertices of each region can be identified from space vector diagrams. Consider the
space vector diagram of Sector 1 of Seven-level inverter, shown in Fig. 3. The reference vector m3 is located in
region 2 of three-level inverter. The m6 and m7 are reference vectors located in region 21 of six-level inverter
and region 29 of seven- level inverter, respectively. mx1 and mx2 (x = 3 or 6 or 7) are projections of reference
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285
World Journal of Modelling and Simulation, Vol. 6 (2010) No. 4, pp. 281-290
vectors on to zero and sixty degrees axes (angle ‘θ’ is angle made by reference vector from zero axes i.e.,
starting of sector 1; be noted m3 , m6 and m7 are having different angle ‘θ’ value). The reference vector can
be synthesized by sequential switching operation of nearest three switching states (vertices of the region in
which reference vector is located). The lengths of new vectors can be found from the below equation:
m1 = m × (cos θ − sin θ/
√
3) m2 = 2 × m × (sin θ/
√
3).
(11)
The values of m1 and m2 for reference vector in each region can be calculated with Eq. (11). The duty
cycles of vertices of reference voltage will be m1 , m2 and [1 − (m1 + m2 )]. For example, with reference to
m3 (reference vector in region 2), the reference vector can be synthesized by switching vectors V1 , V2 and V3 .
It shall be important to note that duty cycle for switching state V1 shall be length of the vector joining V3 and
V1 , whereas, m1 is the projection of reference vector m3 from origin. As such, the corrected duty cycle for
switching state V1 in present case would be (m1 − 0.25). The length of vector joining V3 and V2 is m2 . As
such, corrected duty cycles for switching states V1 , V2 and V3 would be (m1 −0.25), m2 and (0.75−m1 −m2 )
respectively.
The values of m1 and m2 are useful in identifying the region where reference vector is located, which
is the major problem in multilevel inverters. The conditions for identifying reference vector location in each
region and the corrected duty cycles for each of the level of inverter are shown in Tab. 2. Once the region is
identified, the appropriate switching sequence of a region can be identified.
The ON time period for each state can be calculated with duty cycles obtained:
TON for state l = Ts × m1 ,
TON for state 2 = Ts × m2 ,
TON for state 3 = Ts × [1 − (m1 + m2 )].
(12)
The SVPWM algorithm for multilevel inverters:
(1) Find the sector in which Vref lies.
(2) Calculate m1 , m2 from Eq. (11) and compute (m1 + m2 ) of reference voltage.
(3) Find the region in
ref is located.
Thewhich
SVPWM V
algorithm
for multilevel inverters:
1. Find
the sector
in which
Vref lies. of region) to the Vref .
(4) Identify the nearest
three
vectors
(vertices
2. Calculate m1, m2 from Eq.13 and compute (m1+m2) of reference voltage.
(5) Select appropriate
switching
sequences.
3. Find the region in which Vref is located.
(6) Compute ON time
for each
switching
state.
4. Identify
the nearest
three vectors
(vertices of region) to the Vref.
5. states
Select appropriate
switching sequences.
(7) Place the inverter
in the respective
states for the calculated ON times.
6. Compute ON time for each switching state.
7. Place the inverter states in the respective states for the calculated ON times.
36
35
34
33
32
m6
m62
21
31
30
m7
m72
29
28
27
26
0
V/6
m61
V/2
m71
V
First sector of Seven-level inverter space vector diagram.
Fig. 3. FirstFig.3:
sector
of seven-level inverter space vector diagram
Table. II: Location of reference vector in Seven-level inverter
Region
26
27
28
29
Condition for location
of reference vector
0.834<m1<1 ;
m2<0.167;
(m1+ m2)<1;
0.667 < m1<0.834;
m2<0.167 ;
(m1+ m2)>0.834;
0.667 <m1<0.834;
0.167 < m2<0.333;
(m1+ m2)<1;
0.5< m1<0.667;
Corrected m1, m2 and m3
for switching states
m1= m1-0.833;
m2= m2;
m3=1- m1- m2;
m1=0.833-m1;
m2=0.167- m2;
m3= m1+ m2-0.834;
m1=m1-0.667;
m2=m2-0.167;
m3=1- m1- m2;
m1=0.667-m1;
Region
32
33
34
35
Condition for location
of reference vector
0.333<m1<0.5;
0.5< m2<0.667;
(m1+ m2)<1;
0.167<m1<0.333;
0.5<m2<0.667;
(m1+m2)>0.834;
0.167<m1<0.333;
0.667<m2<0.834;
(m1+m2)<1;
m1<0.167;
Corrected m1, m2 and m3
for switching states
m1= m1-0.333;
m2= m2-0.5;
m3=1- m1- m2;
m1= 0.5-m1;
m2= 0.667-m2;
m3=m1+ m2-0.834;
m1= m1-0.167;
m2= m2-0.667;
m3=1- m1- m2;
m1= 0.167-m1.;
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0.04
0.05
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Time (s)
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Time (s)
P. Kumar &
Amarnath & S. Narasimham: A new Space-Vector (a)
Pulse
Width Modulation Algorithm
(a)J.two-level
two-level
286
Vab_2li
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Line voltage Vab (V)
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0
0
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voltageVab
Vab(V)
(V)
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Vab_5li
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(a)(b)two-level
(b)(b)three-level
(d)three-level
five-level
Vab_5li
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Line
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voltageVab
(V) (V)
Line voltage Vab (V)
Line voltage Vab (V)
voltage
LineLine
voltage
Vab(V)
(V)
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Time (s)
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0.09
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(c) four-level
400
0.01
Time (s)
Time (s)
Fig. 4. The line to line voltage of multi-level inverter
300
400
200
300
Simulation results and discussion
100
200
Line voltage Vab (V)
Line voltage Vab (V)
Line voltage Vab (V)
200
200
100
Line voltage Vab (V)
Line
voltage
(V)Vab (V)
Line
voltage
200
4
0.06
400
400
400
-400
0
0.05
0.05 (s) 0.06
Time
0.05
0.06
Time (s)
Time (s)
(e) six-level
(d)(c)
(d)five-level
five-level
four-level
(d)
five-level
(c)(b)
four-level
(c)
four-level
three-level
-300
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0.04
0.04
0.04
0
100
The simulation is carried out for the Two-level, Three-level, Four-level, Five-level, Six-level and Seven0
level inverters using the new Space vector PWM technique and the simulation results are presented. Fig. 4
-100
shows that the generated line to line voltage is very much improved with the level of inverter. Fig. 5 shows the
stator current, torque and speed of seven-level inverter fed-200
induction motor and Fig. 6 shows the total harmonic
-300
distortion (THD), which is highly
reduced as the level of inverter increases. From the results it is observed
Time (s)
that the generated voltage(f)spectrum
seven-level is very much increased
-400 with the level of inverter. The THD values of the
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
Time (s)
proposed inverter are lower than that of the same inverter using other modulation
techniques. The improved
(f) seven-level
speed and torque characteristics are obtained with this algorithm. The torque
ripples are also reduced and
output voltage waveform is highly improved. The fundamental component of the output voltage is increased
with the level of inverter.
The simulation is carried out for the two-level, three-level, four-level, five-level, fix-level and feven-level
inverters using the new space vector PWM technique with the following parameters.
-100
-200
-300
-400
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
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0.09
0.1
-20
Stato
Stat
-20
-40
-60
0
-40
0.1
0.2
0.3
0.4
-60
0.6
0.5
0.7
0
0.1
World Journal of Modelling and Simulation, Vol. 6 (2010) No. 4, Time
pp. (s)
281-290
0.8
0.2
0.9
0.3
160
0.5
0.6
0.7
0.8
0.9
1
0.6
0.7
0.8
0.9
1
0.6
0.7
0.8
0.9
1
Time (s)
Fig. 4: The line to line voltage of multi-level inverter. (a) Stator currents.
60
1
0.4
287
(a) Stator currents.
160
140
140
40
20
0
-20
120
Rotor speed Wm (rad/s)
Rotor speed Wm (rad/s)
Stator currents Ia, Ib, Ic (A)
120
100
80
60
40
100
80
60
40
20
20
-40
0
-60
0
0.1
0.2
0.3
0.4
-20
0.60
0.5
0
0.70.1
0.2
0.8
0.90.3
10.4
Time (s)
140
60
120
50
80
60
30
20
40
30
20
10
0
0.2
0.3
0.4
0.5
Time (s)
(b) Speed.
70
0.5
50
20
0.1
1
0.4
(b)Speed
Speed.
(b)
10
-20
0
0.9
0.3
60
40
-10
0.60
0.8
0.2
70
40
0
0.7
0.1
Time (s)
Torque Te (N-m)
100
Torque Te (N-m)
Rotor speed Wm (rad/s)
70
-20
0.6
0
(b) Speed.
(a)Stator
Stator currents.
(a)
currents
160
0.5
Time (s)
0
0.70.1
0.2
0.8
0.90.3
10.4
0.5
Time (s)
-10
0.6
0
Torque.
(c)(c)Torque
0.7
0.1
0.8
0.2
0.9
0.3
1
0.4
0.5
Time (s)
(c) Torque.
Fig. 5. Stator current, speed and torque of seven-level inverter fed induction motor
60
Torque Te (N-m)
50
40
Region
30
20
2610
0
-10
27 0
28
29
30
31
Table 2. Location of reference vector in seven-level inverter
Condition for location Corrected m1 , m2 and
Condition for location Corrected m1 , m2 and
Region
of reference vector
m3 for switching states
of reference vector
m3 for switching states
0.834 < m1 < 1;
m1 = m1 − 0.833;
0.333 < m1 < 0.5; m1 = m1 − 0.333;
32 0.5 < m2 < 0.667; m2 = m2 − 0.5;
m2 < 0.167;
m2 = m2 ;
(m1 + m2 ) < 1;
m3 = 1 − m1 − m2 ;
(m1 + m2 ) < 1;
m3 = 1 − m1 − m2 ;
0.167 < m1 < 0.333; m1 = 0.5 − m1 ;
0.667 < m1 < 0.834; m1 = 0.833 − m1 ;
0.3
0.4
0.5
0.7
0.8
33 0.5 < m2 < 0.667; m2 = 0.667 − m2 ;
m0.12 < 0.2
0.167;
m20.6= 0.167
− m0.92 ; 1
Time (s)
(m1 + m2 ) > 0.834; m3 = m1 + m2 − 0.834;
(m1 + m2 ) > 0.834;
m
=
m
+
m
−
0.834;
1
2
(c) Torque. 3
0.667 < m1 < 0.834; m1 = m1 − 0.667;
0.167 < m1 < 0.333; m1 = m1 − 0.167;
34 0.667 < m2 < 0.834; m2 = m2 − 0.667;
0.167 < m2 < 0.333; m2 = m2 − 0.167;
(m1 + m2 ) < 1;
m3 = 1 − m1 − m2 ;
(m1 + m2 ) < 1;
m3 = 1 − m1 − m2 ;
0.5 < m1 < 0.667; m1 = 0.667 − m1 ;
m1 < 0.167;
m1 = 0.167 − m1 ;
35 0.667 < m2 < 0.834; m2 = 0.834 − m2 ;
0.167 < m2 < 0.333; m2 = 0.333 − m2 ;
(m1 + m2 ) > 0.834; m3 = m1 + m2 − 0.834;
(m1 + m2 ) > 0.834; m3 = m1 + m2 − 0.834;
0.5 < m1 < 0.667; m1 = m1 − 0.5;
m1 < 0.167;
m1 = m1 ;
36 0.834 < m2 < 1;
0.333 < m2 < 0.5; m2 = m2 − 0.333;
m2 = m2 − 0.834;
(m1 + m2 ) < 1;
m3 = 1 − m1 − m2 ;
(m1 + m2 ) < 1;
m3 = 1 − m1 − m2 ;
0.333 < m1 < 0.5; m1 = 0.5 − m1 ;
0.333 < m2 < 0.5; m2 = 0.5 − m2 ;
(m1 + m2 ) > 0.834; m3 = m1 + m2 − 0.834;
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Mag (
5
0
0
200
400
600
800
1000
Frequency (Hz)
two-level
P. Kumar & J. Amarnath & S. Narasimham: A new Space-Vector(a)Pulse
Width Modulation Algorithm
288
Fig. 5: Stator current, speed and torque of seven-level inverter fed induction motor.
FFT window: 5 of 50 cycles of selected signal
FFT window: 5 of 50 cycles of selected signal
FFT window: 5 of 50 cycles of selected signal
400
400
400
200
200
200
0
0
0
-200
-200
-400
0
-400
0
-200
-400
0
0.02
0.04
0.06
0.08
0.02
0.02
8
Mag
(% (%
of Fundamental)
Mag
of Fundamental)
Mag (% of Fundamental)
25
20
15
10
5
0
200
400
600
800
48
6
2
4
2
0
1000
0
200
0
200
200
200
200
0
0
0
0
-200
-200
-200
0.04
0.06
0.08
0.02
0.04Time (s)0.06
0.08
-400
-400
0
0
126
10
84
6
2
4
0
200
0
200
400
600
800
1000
Frequency
(Hz)
400
600
Frequency
(Hz)
(c) four-level
800
1000
5
3
4
2
3
2
1
1
0
0
200
200
0
0
0
-200
-200
-200
-400
0
0.04
0.04
0.06
0.08
0.06
0.08
Time
Time (s)
(s)
Fundamental(50Hz)
(50Hz) == 198.3
365.1 ,, THD=
THD= 11.57%
6.71%
Fundamental
Mag (% of Fundamental)
Mag (%
(% of
of Fundamental)
Fundamental)
Mag
4
2
3
2
1
1
800
(e)
six-level
five-level
(e)(d)
six-level
0.04
0.06
0.08
Fundamental (50Hz) = 375.9 , THD= 4.67%
5
3
Frequency (Hz)
0.02
Time (s)
4
6
600
1000
1000
2.5
2
1.5
1
0.5
0
0
200
400
600
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-200
800
1000
Frequency (Hz)
seven-level
(f) (f)
seven-level
Fig. 6: FFT analysis and total harmonic distortion (THD) for multi-level inverters.
Fig. 6. FFT analysis and total harmonic distortion (THD) for multi-level inverters
FFT window: 5 of 50 cycles of selected signal
400
0
1000
FFT window: 5 of 50 cycles of selected signal
200
200
400
800
(e) six-level
400
200
600
five-level
(d)(d)five-level
FFT window: 5 of 50 cycles of selected signal
0
400
Frequency (Hz)
400
400
0
1000
0.04
0.06
0.08
0.04
0.06
0.08
Time
Time (s)
(s)
Fundamental(50Hz)
(50Hz)== 198.3
365.1 ,, THD=
THD= 11.57%
6.71%
Fundamental
(b) three-level
0.02
0.02
1000
0.02
0.02
(c) four-level
-400
-400
0
0
800
4
6
Mag (%
(% of
of Fundamental)
Fundamental)
Mag
Mag (% of Fundamental)
Mag (% of Fundamental)
0.02
Time
(s) , THD= 17.05%
Fundamental (50Hz)
= 332.1
Fundamental (50Hz) = 306.4 , THD= 24.99%
0
800
400
400
400
200
2
0
600
FFT window: 5 of 50 cycles of selected signal
FFT window: 5 of 50 cycles of selected signal
FFT window: 5 of 50 cycles of selected signal
8
400
Frequency
(Hz)
400
600
Frequency
(Hz)
(c)
four-level
three-level
(b)(b)
three-level
two-level
(a)(a)two-level
-200
-400
0
-400
0
0.08
10
Frequency (Hz)
400
0.08
12
6
0
0
0.06
Time (s) 0.06
0.04
Time
(s) , THD= 17.05%
Fundamental (50Hz)
= 332.1
Fundamental (50Hz) = 306.4 , THD= 24.99%
Time (s)
Fundamental (50Hz) = 341.6 , THD= 42.48%
0.04
289
World Journal of Modelling and Simulation, Vol. 6 (2010) No. 4, pp. 281-290
Table 3. Switching sequence for seven-level inverter
Sector Region
26
27
28
29
30
31
1
32
33
34
35
36
ON Sequence
Sector Region
ON Sequence
500 600 610 611
47
050 060 160 161
500 510 610 611
46
050 150 160 161
510 610 620 621
45
150 160 260 261
510 520 620 621
44
150 250 260 261
520 620 630 631
43
250 260 360 361
520 530 630 631
42
250 350 360 361
2
530 630 640 641
41
350 360 460 461
530 540 640 641
40
350 450 460 461
540 640 650 651
39
450 460 560 561
540 550 650 651
38
450 550 560 561
550 650 660 661
37
550 560 660 661
Table 4. Simulation results with full-load on induction motor
Inverter
2LI
3LI
4LI
5LI
6LI
7LI
No. of spikes/Half cycle in I - steady state
20
8
8
5
5
4
Peak to Peak I - starting
83
79
85
82
80
79
Peak to Peak I - steady state
15.4
16
14
12
11
10
Time taken to reach I - steady state
0.14
0.16
0.14
0.12 0.11 0.10
Speed ripple
0.3
0.2
0.2
0.5
0.3
0.1
THD
42.48% 24.99% 17.05% 11.57% 6.71% 4.67%
Parameter
SVPWM parameters:
Modulation index m = 0.866; DC Supply voltage = 400V ;
No. of switching intervals = 192; Sampling time T s = 1.984e − 5 sec.
Induction Motor parameters:
2 HP , 1500 W , 400 V , 50 Hz, 4-pole, 1430 rpm, Rs = 1.405 Ω; Rr = 1.395 Ω; Ls = 5.839 mH;
Lr = 5.839 mH; Lm = 0.143 H; J = 0.0131 Kg − m2 ; fr = 0.002985 N − m − s.
5
Conclusion
In this paper a new space vector pulse width modulation (SVPWM) algorithm has been proposed and
implemented for two-level, three-level, four-level, five-level, six-level and seven-level inverters. The SVPWM
involves the sector identification, determination of switching voltage vectors, switching vector sequence and
dwelling time calculations. But as the level of the inverter increases, the sector identification, switching vector
determination and dwelling time calculation becomes more complex. The computational complexity and execution time increases. In the proposed method, a correction to the duty cycles of reference vector is applied
to easily identify the location of reference vector in each region of multi-level inverter. Then the appropriate
switching sequence of the identified region and calculation of switching times for each state with the obtained
duty cycles are estimated. The scheme can be extended to high-level inverters also. Based on the reference
vector correction, the simulation results have been presented and analyzed. It is observed that the generated
voltage spectrum is very much improved with increase the level of inverter. The total harmonic distortion
(THD) is highly reduced as the level of inverter is increases. The THD values of the proposed SVPWM algorithm for two-level, three-level, four-level, five-level, six-level and seven-level inverters are 42.48%, 24.99%,
17.05%, 11.57%, 6.71% and 4.67% respectively, which are lower than that of the same inverter using other
modulation techniques. The results have been good agreement with the published work.
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WJMS email for subscription: info@wjms.org.uk
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