An Improved Three-Phase Auxiliary Resonant Snubber Inverter
for AC Motor Drive Applications
Byeong-Mun Song, *Seong-Ryong Lee, and Jih-Sheng (Jason) Lai
Virginia Power Electronics Center
The Bradley Department of Electrical Engineering
Virginia Polytechnic Institute and State University
Blacksburg, VA 24061-0111
Abstract
An improved three-phase auxiliary resonant snubber inverter
suitable for high power ac motor drive applications is proposed.
The topology is analyzed and the control strategies based on
voltage space vector modulations are discussed. For practical
implementation, three possible logical control strategies are
discussed and simulated. The detailed simulation and
experimental results indicate that zero-voltage operation during
transitions can be achieved. To verify the proposed topology, the
paper presents a comprehensive evaluation with theoretical
analysis, simulation, and experimental results.
I. INTRODUCTION
In the last decade, soft switching inverter (hereafter
referred to as SSI) technologies have been developed for ac
motor drive applications [1]-[7]. The SSI is more attractive
and desirable than the traditional hard-switched PWM
inverter because it can achieve high efficiency and reliability,
low EMI for high switching frequency, low cost and compact
heat sink. Even though a number of soft-switching circuits
have been developed, there exist several problems. The major
challenge is to develop control strategy to satisfy the zero
voltage switching condition of the main devices and zero
current switching condition of the auxiliary switches during
transitions.
The proposed circuit topology is to reduce the parts count
of the resonant snubber based soft-switching inverters,
mainly the number of the resonant inductors and blocking
diodes. This circuit can be controlled with space vector
modulation (SVM) to obtain high efficiency with sinusoidal
output waveforms and simultaneously to reduce the cost by
reducing the number of resonant components.
Therefore, the major benefits of the proposed topology
are less magnetic components and less blocking diodes with
potentially lower cost than the existing SSIs. This paper
presents an improved three-phase auxiliary resonant snubber
topology and its control strategies based on voltage space
vector modulations.
This work was supported by Korea Electrotechnology Research Institute
(KERI) under the Ministry of Science Technology (MOST) in Korea
*Dept. of Control and Instrumentation Engineering
Kunsan National University
Kunsan, Korea
II. OVERVIEW OF EXISTING AUXILIARY RESONANT
SNUBBER INVERTERS
The auxiliary resonant snubber inverter (RSI) topologies
have been proposed in the literature and the basic issue is to
improve efficiency, reduce EMI and have a smaller-sized
system. These topologies include the auxiliary resonant
commutated pole (ARCP) inverter [5], the bridge-diodesconfigured zero-voltage transition (BDZVT) inverter [3], and
Y/Delta-configured auxiliary resonant snubber (Y/DARS)
inverter [2],[7].
The ARCP inverter topology employs a center tapped
capacitor bank to provide commutation source. The problem
is voltage unbalance between split capacitors. To overcome
the voltage unbalance, several load side inverter topologies
including the BDZVTs and Y/DARSs were proposed by
placing the auxiliary circuits on the load side.
Figure 1 shows a bi-directional delta-configured RSI for
three-phase motor drive applications [2]. Although this circuit
has a benefit of easy implementation with high efficiency, it
adds significant cost in resonant components associated with
control logic and gate drive power supplies because each
resonant branch consists of two auxiliary switches, two
diodes and one inductor. The disadvantage is potential
unbalanced inductance between different phase legs due to
layout and package.
Figure 2 shows a zero-voltage transition (ZVT) RSI with
single auxiliary inductor [3]. This topology avoids the
unbalanced resonant circuit problem in [2] and has a cost
advantage over the previous topologies. However, two major
disadvantages exist in this topology:
(1) Three phases must resonate together during each
transition, lacking flexibility of operating single-phase or
single-leg.
(2) The resonant inductor current can swing to negative
direction even with precise timing control. Thus, the
zero-current turn-off can not be fully accomplished in the
auxiliary branch, and a voltage clamp circuit must be
added to protect the auxiliary device.
ã1998 IEEE. Reprinted with permission from IEEE Power Electronics Specialists Conference, Fukouka, Japan, May 17-22, pp. 423-428
C1 S3
S1
Vs
C3 S5
C5
AC
MOTOR
Cs
S4
C4 S6
La
C6 S2
Lb
Dab Sab
C2
connected across the main device. In four quadrant
operations, the operating principle is the same with the
motoring mode and with the generating mode using the
common auxiliary switch device. The detailed operation
modes follow:
Lc
Dbc Sbc
Ds Sr3
Scb Dcb
Sba Dac
Dba Sac
Sca Dca
Vs
Cs
Sr1
Sr5
Sr4
Sr2
S4
C1
Dr2
Vs
S3
C3
C5
Lr
Cs
S4
Dr1
S6
Sr2
C4
C3
C5
S6
AC
Motor
S2
Sr6
C6
C2
Figure 3. The Proposed RSI Topology with Single Auxiliary
Inductor
AC
MOTOR
S2
C6
C1
C4
S5
S5
S3
Lr
Figure 1. Bi-directional delta-configured ARS inverter topology
Sr1 Dm S1
S1
C2
Figure 2. ZVT RSI topology with single auxiliary inductor
III. OPERATING PRINCIPLE OF THE PROPOSED
CIRCUIT TOPOLOGY
A. Derivation of the new circuit
In order to overcome these problems, an improved threephase RSI with a single resonant inductor for high power
inverter applications is presented in Figure 3. The structure of
the proposed circuit topology contains a traditional six-step
inverter, consisting of six power switches, S1-S6, and their
six anti-parallel diodes. Six resonant capacitors can be
externally added to the inverter. The auxiliary branches along
with a single inductor are connected across three output
terminals. That is, the auxiliary resonant circuit consists of
only one resonant inductor, one blocking diode and six
auxiliary switches. The advantage of the proposed topology is
the reduction of the resonant inductor and blocking diodes.
B. Operation modes
The principle of operation of the proposed inverter is
that the resonant branch circuits operate to provide a zerovoltage condition to the IGBTs during turn-on, and the IGBT
turn-off voltage is snubbed by the capacitor across the main
device, as with a snubber capacitor in the conventional PWM
inverter. Since the resonant capacitor slows down the IGBT
voltage rise during turn-off, the turn-off loss is largely
reduced.
Figure 4 shows the proposed single-phase circuit
topology and its operating modes. The circuit is composed of
two pairs of main switch devices, S1-S4 and S2-S3. The antiparalleled diodes are built-in to the main switch devices, D1D4. To create the resonant condition, the capacitors were
Mode 0: i Lr = 0 ; ( t 0 - t1 )
Assume that the load current is positive. The free-wheeling
diodes D1 and D2, and main switches S2 and S3 are
conducting the load current.
Mode 1: 0 < i Lr £ i o ; (t1 - t 2 )
Turn on the auxiliary switches S14A and S14B when the
main switches S2 and S3 are still on as the resonant current
i Lr increases linearly. The current path is established through
S14A, Ds and S14B. The current in S2 and S3 becomes zero
at t 2 when the resonant current equals the load current.
Mode 2: io < ilr £ I x ; ( t 2 - t 3 )
Continue charging the resonant inductor. With a fixed dc bus
voltage VS , I x can be expressed by Equation (1).
Ix =
VS
(t 3 - t1 )
Lr
(1)
Equation (1) shows that the initial inductor current I x must be
larger than the load current of a motor.
Mode 3: I x < iLr ; ( t 3 - t 4 )
Turn-off S2 and S3 when the resonant inductor stores
sufficient energy to charge and discharge C2 and C3. At that
point, the capacitors C2 and C3 function as lossless snubbers
for zero-voltage turn-off. The initial inductor current I x can
be controlled by the linear charging period. After t 3 , all the
resonant capacitors are resonating with the resonant inductor,
Capacitors, C1and C4 are discharged to zero voltage, and C2
and C3 are charged to Vs until t 4 is reached by natural
resonance.
Mode 4: i o < i Lr £ I x ; (t 4 - t 5 )
At the end of the natural resonance period, the resonant
current begins to decrease until it equals the load current, and
then is diverted to diodes D1 and D4. Switches S1 and S4 can
then be turned on at zero-voltage condition. When the
resonant current equals the load current, the diode current is
diverted to the switch.
S1
S2
io
C1
Vs
i Lr
S14B
S3
C3
S1
S4
S2
io
C1
S1
Vs
S3
S14B
C3
S14A
Ds-Lr
S4
S2
io
S14B
C3
S3
C4
iLr
S4
S1
C2
S14B
C4
S3
C4
S2
S14A
Ds-Lr
S4
Mode 4
S2
io
C1
S14B
C3
C2
iLr
C4
C2
iLr
Vs
S4
Mode 2
S14A
io
C1
S14A
Ds-Lr
Ds-Lr
Mode 3
C3
C2
i Lr
Vs
Mode 1
C1
C3
S1
C2
iLr
Vs
S3
C4
Mode 0
S14B
S3
S2
io
C1
Vs
S14A
Ds-Lr
S1
C2
S14A
Ds-Lr
S4
C4
Mode 5
(a) Circuit operational sequence during ZVT transition
for a single-phase inverter
i Lr
Ix
io
0
io
I S 1, I S 4
0
IV. CONTROL STRATEGIES BASED ON VOLTAGE
SPACE VECTORS
As this ARS inverter topology has all the auxiliary resonant
components on the load side, the three legs of the auxiliary
circuit should resonate in coordination with the load current.
For the control of this inverter topology, the conventional
SVM is modified to obtain zero-voltage condition for the
main devices. There are three possible logical control
strategies to the proposed topology depending on the use of
the zero vectors. The details of these control strategies to the
proposed topology are discussed as following.
4.1 Conventional hard switching SVM strategy
Various SVM techniques based PWM strategies have
been widely used in industry. Figure 5 shows a three-phase
voltage source inverter space vector diagram. If the voltage
vector V r in Sector I is placed in the hexagonal area and is
presented by the Park’s Plane, vector V r can be synthesized
by switching sequence of the inverter states in Sector I which
contains adjacent vectors V1 and V2 and the zero vectors.
IS 2,IS 3
Ix
stored energy of the resonant capacitor should be related to
the control of the resonant circuit. There are two possible
solutions to implement this in ARSI topologies: fixed timing
control and variable timing control. The fixed timing control
has an advantage of simple control process, but it has the
disadvantage of lower inverter efficiency due to unnecessary
high peak resonant current. To overcome and to restrict the
auxiliary switch conducting time, a variable timing control
method is proposed for a wide current range.
I Cr 1, I Cr 4
0
Im
I Cr 2 , I C r 3
S
2,
S1, S
S3
V3 ( NPN )
4
0
S
t0
14 A , 14 B
V2 ( PPN )
Sector II
Sector
III
V4 ( NPP )
t1 t 2 t 3 t 4 t 5 t 6
(b) Operational modes and these corresponding waveforms
Figure 4. The Proposed single-phase inverter operational modes
Sector I
V1 ( PNN )
V0 ( NNN )
Sector
IV
V7 ( PPP)
Sector
VI
C. Control criteria
The ARSI topology has to satisfy zero-voltage switching
for the main devices and zero-current switching for the
auxiliary switches during transitions. In order to meet this
requirement, the inverter switching sequence should follow
the load current. That is, the relationship between the
deadtime of the main device and the discharging time of the
Re
y
Vr
y × V2
0
x × V1
Vys V
1
Vxs
Sector V
x
V5 ( NNP )
Mode 5: 0 < i Lr £ i L ; ( t 5 - t 6 )
The resonant current is decreasing at a rate of - V S / Lr , and
two switch currents S1 and S4 are increasing until the
resonant current equals zero. The auxiliary switches are
naturally turned off at zero current condition.
V2
V6 ( PNP)
(a) Hexagonal space vectors (b) Voltage reference vector
Figure 5. Three-phase voltage source inverter (VSI) space vectors
The following voltage reference vector equation can be
expressed based on Sector I, as ia > 0 , ib < 0 and i c < 0 .
Where,
V r = x × V1 + y × V 2 + z × V 0 (or × V 7 )
x = (V ys +
y=-
2
3
1
3
V xs ×
z = 1- x - y
V xs ) ×
1
Vs
(2)
1
Vs
(3)
4.2 Adjacent soft-switching SVM schemes
As briefly mentioned above, to satisfy the ZVT condition
during the commutation period in this topology, at least one
of the main switches should be charged or discharged.
However, conventional adjacent-space vector modulation is
not suitable for the proposed topology and other ac side
topologies [9],[11]. In spite of the topological restriction to
using zero vectors, the realization of the switching control
can be realized by changing the voltage vector sequence for a
short time to replace zero vectors. For example, the main
device sequence should be modified by vector NPP instead of
NNN for a short time until the resonant capacitor charges to
provide the zero-voltage turn-on for the next switching
sequence. To avoid the zero vectors, if needed, it can be
synthesized by two vectors V1 and V 4 . Therefore, a desired
B. Asymmetric SVM scheme
Figure 7 shows a repeated SVM scheme and its
corresponding auxiliary switching sequence. This scheme is
useful for calculation of the real time control due to the
repeated calculations. This case is the most simple
modulation scheme for a digital implementation. The voltage
reference vector is used to turn on all the lower side switches
at the beginning of the switching sequence and then to turn
these devices off sequentially so that the zero vector is split
between V 0 and V 7 equally. This asymmetric SVM scheme
has a logical step sequence for turn-on, and three switches are
turned off at the same time in a cycle. When vector V 0 (NNN)
transits to vector V1 (NPP), it should be modify with turning
on V4 (NPP) for a short time as the same rule mentioned
above. The advantage of this scheme is to modify only one
pattern in a cycle instead of two.
Phase Sw
Upper
IGBTs
A. Symmetric SVM scheme
Figure 6 shows a symmetric SVM scheme and its
corresponding auxiliary switching sequence. This scheme has
the advantage of the lowest THD due to symmetric switching
waveforms. Soft-switching constraints during a cycle occur at
two vectors V 0 and V 7 , respectively. From V 0 (NNN) to
V1 (PNN) transition, it should be modified with turning on
V4 (NPP) for a short time. From V7 (PPP) to V2 (PPN)
transition, it should be also modified with turning on
V5 (NNP) for a short time. This scheme requires two
PNN
PPN
PPP
NNN
PNN
PPN
PPP
S3
S5
S4
Lower
IGBTs
reference vector Vr is rearranged as the following:
(4)
V r = ( x + Dx ) × V1 + y × V 2 + Dx × V 4 + ( z - 2 × Dx ) × V 7
Where, Dx is the minimum duty cycle to provide a softswitching operation. This value can be determined by a
function of the auxiliary conducting time. The sequence for
all the sectors is the same with this procedure. Two widely
used SVM methods in the hard-switching inverter and three
possible SVM methods including non-adjacent SVM scheme
are presented below:
NNN
S1
S6
S2
ZVT Lost Upper IGBT
Conditions
Lower IGBT
Figure 7. Asymmetric SVM and soft-switching sequences
4.3. Non-adjacent SVM scheme
The other available control strategy is to use voltage
space vectors except zero vectors. Figure 8 shows nonadjacent voltage source inverter vectors.
Im
V3 ( NPN )
V2 ( PPN )
B
Va
Vb
Vc
Sector I
A
V 4 ( NPP )
Re
V1 ( PNN )
Sector II
Sector III
V5 ( NNP )
C
0
x, y and z are weighting factors for the duty cycle of the
voltage vectors, respectively. The sum of the duty cycle per
switching period is unity. Based on stationary reference
frame coordinator [8], a desired voltage vector is synthesized
with this sector. V s is the input voltage of the inverter.
ab
ac
bc
ba
ca
cb
V6 ( PNP )
(a) Non-adjacent space vectors (b) Voltage waveforms
modifications in Sector I.
Phase Sw
Upper
IGBTs
NNN
PNN
PPN
PPP
PPP
PPN
PNN
P hase S w
NNN
S1
S3
U pper
IG B T s
S4
S6
S2
ZVT Lost Upper IGBT
Conditions
Lower IGBT
Figure 6. Symmetric SVM and soft-switching sequences
S e c t o r I I (b )
S e c t o r I I I( c )
S3
S5
S5
Lower
IGBTs
S e cto r I (a )
S1
Low er
IG B T s
S4
S6
S2
Z V T L ost
C o n d itio n s
U p p e r IG B T
L o w e r IG B T
(c) Switching sequences
Figure 8. Non-adjacent voltage space vectors and these switching
sequences
This scheme is divided into three sectors with two phases
each, a-b, b-c and c-a, respectively.
Therefore, the structure is the same as a single-phase fullbridge inverter with 120° transition. In a three-phase inverter,
it needs to know the next phase sequence corresponding to
the motor directions. Hence, this method requires switch
voltage sensing. With a total of twelve voltage transitions
occurring under six different modes, the control scheme is
simple and easy to implement. It is difficult to get a
sinusoidal output current, but suitable for trapezoidal wave
bruchless dc motors.
The output currents, however, remain smooth sinusoidal
waveform. The simulation result indicates that the proposed
topology clearly satisfies the zero-voltage operation during
transitions based on the modified SVM control.
ia
ib
ic
ia
V. SIMULATION AND EXPERIMENTAL RESULTS
A. Simulation results
To verify the ZVT operation of the proposed topology, the
circuit was simulated with Pspice program. All the possible
SVM techniques mentioned above, the asymmetric SVM
scheme was picked due to easy implementation with digital
control.
Figure 9 shows the corresponding waveforms of the
proposed topology during transitions. Figure 9(a)-(c) shows
the gate signal sequences of the main devices in the inverter
based on a voltage space vector modulation (SVM). Figure
9(d) shows the body diode currents of the main devices S4,
S3 and S5, respectively. Total current of S4 for the phase A
region is the same as the sum of that of S3 and S5. Figure 9(e)
shows the voltage and current waveforms of the main devices
during a commutation period, where Ds1 is the diode
connected across the main switch S1 on the complementary
side.
(a)
V(G2)
(b)
V(G6)
(c)
(d)
(e)
V(G3)
I(Da4)
I(Da3)
VCE
B. Experimental results
In order to verify the proposed circuit topology, a softswitching inverter was designed and implemented. Tests have
been done on single-phase full bridge with resonant circuit
operation. Detailed design parameters for the proposed softswitching inverter are as follows:
1) Dual IGBT Module with 600 V - 400 A, MG400J2YS50
was used for the inverter topology.
2) The resonant capacitors used were the Polypropylene
capacitors with 0.22 mF-600 V.
3) The Resonant inductor used was of 2 mH.
4) The auxiliary switch chosen was with MCT 75 A-600 V.
This device was controlled with a negative pulse for
turn-on and a positive pulse for turn-off.
5) A blocking auxiliary diode was chosen with
HFA50PA60C rated 50 A-600 V, and a reverse recovery
time of 19 ns.
6) A saturable core was used to reduce EMI noises during
transitions.
The following test results show the circuit operation
waveforms of the proposed soft-switching inverter [12].
Figure 11 shows experimental turn-off current and
voltage waveforms for hard and soft-switching schemes. The
auxiliary capacitor C r , is used which has a dv/dt rate of
V(G1)
V(G4)
I(Da5)
V(G5)
Figure 10. Simulation output current waveforms of the proposed
topology with voltage space vectors
IDS1
Figure 9. Simulation waveforms of the proposed topology during
transitions
Figure 10 shows the output current waveforms of the
proposed three-phase inverter with voltage space vector
modulation. This topology needs NNN to be modified to NPP
and PPP to be modified to PNN for a short period in Sector I.
Similar modifications also need to be applied to other sectors.
380 V / ms , much reduced from 2.0 KV / ms that was obtained
from the hard-switching condition. The turn-off loss under
soft-switching was reduced 5 times as compared to that
obtained from the hard-switching scheme.
Figure 12 shows experimental main switch collectoremitter and gate-emitter voltage waveforms during turn-on
and turn-off. These waveforms illustrate turn-on and turn-off
switching characteristics of the main device under softswitching condition with a large charging time of 2 ms and
deadtime of 1.5 ms. This figure also shows a resonant
inductor current waveform when the main switch is turned on
at zero-voltage transition. This figure indicates that the device
is turned at a zero-voltage condition. As expected, the MCTs
conduct for 5.5 ms with a resonant current of 50A. The
amplitude of the resonant current is required to be larger than
the load current. Figure 12(a) indicates a zero-voltage
switching of IGBT during turn-on. Figure 12(b) shows the
turn-off voltage and current waveforms corresponding to the
operation.
Ic (40A/div)
Ic (40A/div)
VCE (100V/div)
VCE (100V/div)
dv / dt 380 V/ ms
. mJ
E off 1.42
dv / dt 2.0kV / ms
E off 7.5 mJ
(a) Hard-switching
(b) Soft-switching
Figure 11. Experimental turn-off current and voltage waveforms
between hard and soft-switching schemes
VCE (100V / div)
VGE (10V / div)
VCE (100V / div)
VI. CONCLUSIONS
In this paper, an improved three-phase auxiliary resonant
snubber inverter suitable for high power ac motor drive
applications was proposed and implemented on the 50kW
inverter test module, while considering the problems of the
existing soft-switching topologies. The proposed topology
was also analyzed with the proper control strategies based on
the voltage space vector modulation. For practical
implementation of the algorithms of the ARSI topologies,
three possible logical control strategies were discussed and
simulated for the proposed topology. The detailed simulation
and experimental results indicate that zero-voltage operation
during transitions was achieved.
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VGE (10V / div)
i Lr (50 A / div )
io (50 A / div)
io (50 A / div )
iLr (50 A / div )
Time : 1ms / div
(a) Turn-on
(b) Turn-off
Figure 12. Experimental turn-on and turn-off waveforms under the
proposed soft-switching inverter
Figure 13 shows the output current waveform of the
proposed inverter with the inductor load. The switching
frequency was 20kHz and the fundamental frequency was
30Hz. The current ripple is largely reduced with high
frequency switching.
io : 50 A / div)
Time : 10ms / div
Figure 13. Experimental output current waveform
of the proposed inverter
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