Common Mode Leakage Current Elimination For

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ISSN No: 2309-4893
International Journal of Advanced Engineering and Global Technology
I
Vol-04, Issue-03, May 2016
Common Mode Leakage Current Elimination For
Photovoltaic Grid Connected Power System
Mrs.Navita G.Pandey
Mr.Harishchandra S. Kulkarni
Assistant Professor
Department of Electrical Engineering
A.C.Patil College Of Engineering
University Of Mumbai
Final Year Student Of M.E.Power System
Department of Electrical Engineering
A.C.Patil College Of Engineering
University Of Mumbai
Abstract – We have often see that contribution of renewable
energy sources is increased due to the fact that they provide
environment clean energy output. Among them photovoltaic
power system is one of the biggest and easy available source.
When no transformer is used in grid connected power system
there is galvanic connection between grid and PV array .In these
condition dangerous leakage current(common mode leakage
current) can appear between PV array and ground through
parasitic capacitance. This common mode leakage current
increases the system losses, reduces the grid connected current
quality and induces electromagnetic interference with personal
safety. This paper presents the improved transformerless
inverter topology which deals with elimination of common mode
leakage current. Both the unipolar SPWM strategy and bipolar
SPWM strategy is used here to eliminate common mode leakage
current. Finally a 1Kw inverter has been simulated to verify
theoretical analysis by both strategies.
Index Terms— Bipolar SPWM ,Common mode leakage current,
Parasitic capacitance, SPWM technique, unipolar SPWM,
I. INTRODUCTION
It is often know that photovoltaic power system is best
among all renewable energy sources. It consist of solar array
which coverts solar energy into electrical energy.
But when it is connected to grid it is commonly used with
transformer which provides galvanic isolation with personal
safety. But use of transformer makes system bulky ,increases
cost of system with reduction of overall efficiency, so to
overcome this drawback we prefer transformerless inverter.
When no transformer is used ,a galvanic connection between
ground of the grid and PV array exist. Under this condition a
common mode leakage current flows through parasitic
capacitor between the PV array and ground.
The common mode leakage current increase the system
losses ,reduces the grid connected current quality, induces
severe conducted and radiated electromagnetic interference
and causes personal safety problems.
The general arrangement of flow of common mode
leakage current[3] is shown in fig.1
Fig.1.Resonant circuit of common mode leakage current.
II.
CONDITION OF ELIMINATING COMMON MODE LEAKAGE
CURRENT
The common mode voltage is the average value of the voltages
between the outputs and a common reference. For this system,
it is very useful to use the negative terminal of the dc bus,
point N, as the common reference. The simplified equivalent
model of common mode resonant circuit obtained in [2]- [4][5] as shown in fig.2
Fig.2 Simplified equivalent model of common mode resonant
circuit
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www.ijaegt.com
ISSN No: 2309-4893
International Journal of Advanced Engineering and Global Technology
I
Vol-04, Issue-03, May 2016
Where
is the parasitic capacitor ,
and
are the
filter inductors,
is the common mode leakage current and
hence a equivalent common mode voltage uecm is defined by
uecm = ucm +udm LB –LA
2 LA + LB
(1)
voltage. Here decoupling of additional two switches are made
in single full bridge inverter.Switch1 and switch 2 operating at
the grid frequency, switch 3 and switch 4 operating at
switching frequency. Two additional switches i.e switch 5 and
switch 6 commutate alternately at grid frequency and
switching frequency to achieve dc-decoupling state.
III. SWITCHING STRATEGY OF INVERTER WITH SPWM
TECHNIQUE
Sinusoidal Pulse Width Modulation
In this modulation technique are multiple numbers of output
pulse per half cycle and pulses are of different width. The
width of each pulse is varying in proportion to the amplitude
of a sine wave evaluated at the centre of the same pulse. The
gating signals are generated by comparing a sinusoidal signal
as a reference wave with a high frequency triangular signal as
a carrier wave as shown in figure 4.3. The intersection of
triangular carrier wave and a sinusoidal reference waves
determines the switching instants and commutation of the
modulated pulse.
Fig.3 Equivalent circuit for leakage current analysis.
Thus from above equation it is clear that common mode
leakage current
is ,
=
(2)
Thus from (2) it is derived that the common mode leakage
current is depend upon variation in common mode voltage.So
to eliminate leakage current it is necessary to keep common
mode voltage constant.
A .Improved inverter topology
Fig. 5 Representation Sinusoidal Pulse Width Modulation.
There are various types of SPWM techniques are available,
but in this research two control techniques are used as below ,
A Unipolar SPWM
B Double Frequency SPWM
Fig.4 Improved inverter circuit to eliminate common mode
leakage current
As shown in above figure we have one improved inverter
circuit through which we can make constant common mode
Unipolar SPWM strategy
The four operation modes that generate the voltage states of
+
,0,−
are shown in Fig. 10. Fig.11 shows the ideal
waveforms of the proposed inverter with unipolar SPWM. In
1969
www.ijaegt.com
ISSN No: 2309-4893
International Journal of Advanced Engineering and Global Technology
I
Vol-04, Issue-03, May 2016
the positive half cycle,S1 and S6 are always ON,S4 and S5
commutate at the switching frequency with the same
commutation orders.S2 andS3, respectively, commutate
complementarily to S1 and S4. Accordingly, Mode 1 and
Mode 2 continuously rotate to generate +
and zero states
and modulate the output voltage. Likewise, in the negative half
cycle, Mode 3 and Mode 4 continuously rotate to generate –
and zero states as a result of the symmetrical modulation.
Mode 1: when S4 and S5 are ON,
=+
and the inductor
current increases through the switches S5,S1,S4, and S6. The
common-mode voltage is
(5)
Mode 2: when S4 and S5 are turned OFF, the voltage
and
falls
circuit board and the life of the switching components
compared with H5 inverter.
B. Double-Frequency SPWM Strategy
The proposed inverter can also operate with the doublefrequency SPWM strategy to achieve a lower ripple and higher
frequency of the output current[10]. In this situation, both
phase legs of the inverter are modulated with 180◦ opposed
reference waveforms and the switches S1–S4 all acting at the
switching frequency. Two additional switches S5 and S6 also
commutate at the switching frequency cooperating with the
commutation orders of two phase legs. Accordingly, there are
six operation modes to continuously rotate with double
frequency and generate + and zero states or − and zero
states, as shown in Figs. 6 and 8 Fig. 9 shows the ideal
waveforms of the improved inverter with double-frequency
SPWM.
rises until their values are equal, and the antiparallel
diode of S3 conducts. Therefore,
=0 V and the inductor
current decreases through the switchS1 and the antiparallel
diode ofS3. The common-mode voltage changes into
(6)
=−
Mode 3: whenS3 andS6 are ON,
and the inductor
current increases reversely through the switches S5, S3, S2 and
S6. The common-mode voltage becomes
(7)
Mode 4: whenS3 andS6 are turned OFF, the voltage
rises
and
falls until their values are equal, and the antiparallel
=0 V and the
diode of S4 conducts. Similar as to Mode 2 ,
inductor current decreases through the switch S2 and the
antiparallel diode of S4. The common-mode voltage
Keeps
also
/2 referring to (6). From (5) to (7), the common-
mode voltage can remain a constant
/2 during the four
commutation modes in the improved inverter with unipolar
SPWM. The switching voltages of all commutating switches
Fig.6 Four operation modes of the improved inverter with
unipolar SPWM. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d)
Mode 4.
are half of the input voltage
/2, and thus, the switching
losses are reduced. Furthermore, in a grid period, the energies
of the switching losses are distributed averagely to the four
switches S3, S4, S5, and S6 with high-frequency
commutations, and it benefits the thermal design of printed
1970
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ISSN No: 2309-4893
International Journal of Advanced Engineering and Global Technology
I
Vol-04, Issue-03, May 2016
keep a constant
/2 in the whole switching process of six
operation modes. Furthermore, the higher frequency and lower
current ripples are achieved, and thus, the higher quality and
lower THD of the grid-connected current are obtained, or a
smaller filter inductor can be employed and the copper losses
and core losses are reduced. Thus the proposed method
eliminates common mode leakage current by keeping common
mode voltage constant for all six modes and also reduces the
amount of semiconductors as compared to other methods.
Fig.7 Ideal waveforms of the improved inverter with unipolar
SPWM.
In the positive half cycle,S6 and S1have the same
commutation orders, and S5and S4 have the same orders. S2
and S3, respectively, commutate complementarily to S1
andS4. Accordingly, Mode 1, Mode 2, and Mode 5
continuously rotate to generate +
and zero states and
modulate the output voltage with double frequency. In the
negative half cycle, Mode 3, Mode 4 and Mode 6 continuously
rotate to generate – and zero states with double frequency
due to the completely symmetrical modulation.
Mode 5: when S1 and S6 are turned OFF, the voltage
Fig. 8 remaining two of six operation modes under doublefrequency SPWM. (a) Mode 5. (b) Mode 6.
falls
and
rises until their values are equal, and the antiparallel
diode of S2 conducts. Therefore,
=0 V and the inductor
current decreases through the switchS4 and the antiparallel
diode ofS2. The common-mode voltage
keeps a constant
/2.
Mode 6: similarly, when S2 and S5 are turned OFF, the
voltage
rises and
falls until their values are equal,
and the antiparallel diode ofS1 conducts. Therefore
=0 V
and the inductor current decreases through the switch S3 and
the antiparallel diode ofS1. The common-mode voltage
still is a constant
/2 referring to (9). Under the doublefrequency SPWM strategy, the common-mode voltage can
Fig. 9 Ideal waveforms of the improved inverter with doublefrequency SPWM.
1971
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ISSN No: 2309-4893
International Journal of Advanced Engineering and Global Technology
I
Vol-04, Issue-03, May 2016
IV. SIMULATION RESULTS
8
6
A 1 kW inverter for PV array is simulated with PV panel is
connected to ground by parasitic capacitance 75 nF. The
details of components and parameters used are as: output
=1 kW; input voltage,
capacitor,
=940μF; grid voltage,
frequency,
=50Hz;switch frequency,
2
Current1
power,
4
=380V; input
=220
0
-2
; grid
-4
=20 kHz; filter
-6
inductor, =4 mH; parasitic capacitor,
=75 nF. Fig. 14
shows the simulated results by using the unipolar SPWM and
double frequency SPWM control strategy.
-8
0
0.01
0.02
0.03
0.04
0.05
Time
0.06
0.07
0.08
0.09
0.1
0.05
Time
0.06
0.07
0.08
0.09
0.1
c) Grid current
1
400
0.8
300
Common mode leakage current
0.6
200
Voltge2
100
0
-100
-200
0.4
0.2
0
-0.2
-0.4
-0.6
-300
-0.8
-400
0
0.01
0.02
0.03
0.04
0.05
Time
0.06
0.07
0.08
0.09
-1
0.1
0
0.01
a) Grid voltage
0.02
0.03
0.04
d) Common mode leakage current
Fig.10 Simulated waveforms with unipolar and double
frequency SPWM strategies.
400
300
200
Voltage
100
REFERENCES
0
-100
-200
-300
-400
0
0.01
0.02
0.03
0.04
0.05
Time
0.06
0.07
b) Common mode voltage
0.08
0.09
0.1
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[2] Gonzalez E. Gubia, J. Lopez and L. Marroyo,.”Transformerless
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[4] M.C. Cavalcanti,K.C. de Oliveira, A.M. de Farias,F.A.S. Neves,
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www.ijaegt.com
ISSN No: 2309-4893
International Journal of Advanced Engineering and Global Technology
I
Vol-04, Issue-03, May 2016
[5] Sushant S. Paymal, Prof. Mrs. V.S.Jape,”Transformerless grid
connected
inverters
for
photovoltaic
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[6] S.V. Araujo, P. Zacharias ,and, R. Mallwitz, “Highly efficient
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Authors Profile
Mr. Harishchandra S. Kulkarni
Final f
Final year student ,M.E.power system
Department of Electrical Engineering.
A.C.Patil college of Engineering
University Of Mumbai
Mrs.Navita G.Pandey
Assistant Professor
Department of Electrical Engineering
A.C.Patil college of Engineering
University Of Mumbai
1973
www.ijaegt.com
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