The MOSFET
Introduction
‰
Metal oxide semiconductor field effect transistor
(MOSFET) or MOS is widely used for
implementing digital designs
Assets: High integration density and relatively simple
manufacturing process
‰
Consequently, it is possible to realize 107-8
transistors on an integrated circuit (IC)
economically.
The MOS Transistor
Gate Oxide
Source
Gate
Polysilicon
n+
Drain
n+
p-substrate
Field-Oxide
(SiO2 )
p+ stopper
Heavily doped n-type source and drain regions are implanted
(diffused) into a lightly doped p-type substrate (body)
A thin layer (approx. 50 A0) of silicon dioxide (SiO2) is grown
over the region between source and drain and is called thin or
gate oxide
• Gate oxide is covered by a conductive material, often polycrystalline
silicon (polysilicon) and forms the gate of the transistor
• MOS transistors are insulated from each other by thick oxide
(SiO2) and reverse biased p-n+ diode
• Adding p+ field implant (channel stop implant) makes sure a
parasitic MOS transistor is not formed
MOS Transistor as a switch
Vin > VT : a conducting channel is formed between source and
drain and current flows
Vin <VT : the channel does not form and switch is said to be
Open
Vin >VT : current is a function of gate voltage
NMOS, PMOS, and CMOS Technology
In an NMOS transistor, current is carried by electrons (from
source, through an n-type channel to the drain
Different than diode where both holes and electrons contribute
to the total current
Therefore, MOS transistor is also known as unipolar device
Another MOS device can be formed by having p+ source and
drain and n-substrate (PMOS)
Current is carried by holes through a p-type channel
A technology that uses NMOS (PMOS) transistors only is
called NMOS (PMOS) technology
In NMOS or PMOS technologies, substrate is common and is
connected to +ve voltage, GND (NMOS) or VDD (PMOS)
In a complementary MOS (CMOS) technology, both PMOS
and NMOS transistors are used
NMOS and PMOS devices are fabricated in isolated region
from each other (i.e., no common substrate for all devices)
MOS transistor is a 4 terminal device, if 4th terminal is not
shown it is assumed to be connected to appropriate voltage
What is an MOS Transistor?
A Switch!
An MOS Transistor
VGS ≥ VT
S
|VGS|
Ron
D
When the voltage applied to the gate is larger than VT, a conducting channel is formed
between the drain and source. In the presence of a voltage difference between D & S,
electrical current flows between them. When the gate voltage is lower than the threshold, no
channel exists, and the switch is considered open.
Very few parasitic effects, high integration density, relatively simple manufacturing process
Threshold Voltage: Concept
+
VGS
S
-
D
G
n+
n+
n-channel
Depletion
Region
p-substrate
B
Initially: VGS=0, both pn-junctions have a 0V bias, and are considered off => extremely high
resistance between drain and source.
Then: VGS>0, channel is formed
If now the gate voltage (VGS) is increased, gate and substrate form plates of a capacitor with
oxide as dielectric
+ve gate voltage causes +ve charge on gate and -ve charge
on the substrate side. In substrate it occurs in two steps (i) depletion of mobile
holes, (ii) accumulation of -ve charge (inversion)
At certain Vgs, potential at the interface reaches a critical
value, where surface inverts to n-type (start of strong inversion)
Further Vgs increase does not increase the depletion width
but increases electrons in the inversion layer
Threshold Voltage
where
VT = VT 0 + γ [ − 2ΦF + VSB − − 2ΦF ]
where
γ =
2qεsiNA
COX
VT is +ve for NMOS and -ve for PMOS devices
The Threshold Voltage – Body Effect
0 .9
0 .8 5
VT is the VGS value where strong
inversion occurs.
Note that VBS should never exceed
0.6V, otherwise the source-body
becomes forward biased, which
deteriorates the transistor’s operation
0 .8
0 .7 5
T
V (V)
0 .7
0 .6 5
0 .6
0 .5 5
0 .5
0 .4 5
0 .4
- 2 .5
-2
- 1 .5
-1
V
BS
- 0 .5
0
(V )
VT = VT 0 + γ
(
− 2Φ F + VSB − 2Φ F
)
Function in manufacturing process (oxide thickness, fermi voltage, ion implants)
Transistor in Linear
S
n+
VGS
VDS
G
– V(x)
ID
D
n+
+
L
x
p-substrate
B
With VGS>VT, and a small VDS is applied, a current ID flows from the drain to source.
Using simple analysis, a first order expression of ID is obtained.
When VGS >VT
Let at any point along the channel, the voltage is V(x) and
gate to channel voltage at that point is VGS -V(x)
If the Vgs -V(x) >VT for all x, the induced channel charge per
unit area at x (Cox is the capacitance per unit area of the gate oxide – εox/tox)
Qi ( x) = −COX [Vgs − V ( x) − VT ]
Current is given by
I D = − υ ( x ) Q i ( x )W
The electron velocity is given by
υ n = − µ nE ( x ) = µ n
Therefore,
dV
dx
IDdx = µnCOXW (Vgs − V − VT )dV
Integrating the equation over the length L yields
2
W
Vds
]
ID = K ' n [(Vgs − VT )Vds −
2
L
2
Vds
]
ID = Kn[(Vgs − VT )Vds −
2
or
For small VDS values,
the MOS acts as a
resistor
Transistor in Saturation
VGS
V DS > VGS - V T
G
D
S
n+
-
VGS - VT
+
n+
Pinch-off
With VGS>VT, and a larger VDS applied, the channel thickness gradually is reduced from source
to drain until pinch-off occurs (channel depth depends on the voltage from G to channel). This
occurs when pinch-off condition meets the drain region,
VGS − VDS ≤ VT
and current remains constant
ID =
kn W
(VGS − VT )2
2 L
K’n is known as the process trans-conductance parameter and
equals
K ' n = µnCOX = µn
εox
tox
If the VGS is further increased, then at some x, Vgs - V(x) <VT
and that point the channel disappears and transistor is said to
be pinched-off
Close to drain no channel exists, the pinched-off condition in
the vicinity of drain is VGS - VDS ≤ VT
Under these conditions, transistor is in the saturation region
If a complete channel exists between source and drain, then
transistors is said to be in triode or linear region
Replacing Vds by Vgs -VT in the current equation we get,
MOS current-voltage relationship in saturation region
K'n W
ID =
(Vgs − VT ) 2
2 L
This equation is not entirely correct, the position of pinch-off
point and hence the effective channel length is a function of
Vds, a more accurate equation is given as
ID =
K'n W
(Vgs − VT ) 2 [1 + λVds ]
2 L
ID (mA)
2
Triode
VGS = 5V
Saturation
VGS = 4V
1
VGS = 3V
VGS = 2V
VGS = 1V
0.0
1.0
2.0
3.0
4.0
VDS (V)
(a) ID as a function of V DS
5.0
0.020
÷ √ID
VDS = V GS-VT
Square Dependence
where is an empirical constant parameter called channel
length modulation factor
0.010
Subthreshold
Current
0.0
2.0
VT1.0
VGS (V)
(b) √ID as a function of V GS
(for VDS = 5V).
3.0
Current-Voltage Relations
A good ol’ transistor
6
x 10
-4
VGS= 2.5 V
5
Resistive
Saturation
4
ID (A)
VGS= 2.0 V
3
VDS = VGS - VT
2
VGS= 1.5 V
1
0
Quadratic
Relationship
VGS= 1.0 V
0
0.5
1
1.5
VDS (V)
2
2.5
A model for manual analysis
The Transistor as a Switch (for hand analysis)
VDS (VDD
VGS ≥ VT
S
VDD
VDD/2)
ID
Ron
D
ID
Ron varies with time, nonlinear and
depends on operating point of the MOS.
t
t
1 2
1 2 VDS (t)
Req = average
Ron(t)dt =
dt
t =t1...t 2 (Ron(t)) =
t2 − t1 ∫t1
t2 − t1 ∫t1 ID (t)
1
Req ≈ (Ron(t1) + Ron(t2 ))
2
V GS = VD D
Rmid
R0
V DS
VDD/2
VDD
The Transistor as a Switch
• Resistance is inversely proportional to W/L ratio of the
device. Doubling the transistor width cuts the resistance
by half
7
x 10
5
6
4
eq
R
• For VDD >> the resistance becomes virtually
independent of VDD. Only a minor improvement is the
resistance can be seen when rising VDD (attributed to the
channel length modulation) – refer to the I-V equations
in linear and saturation
(Ohm)
5
3
2
1
• Once VDD approaches VT, the resistance dramatically
increases.
0
0.5
1
1.5
V
DD
(V)
2
2.5
Dynamic Behavior
G
CGS
CGD
D
S
CGB
CSB
B
CDB
Dynamic Behavior
MOS transistor is a unipolar (majority carrier) device, therefore,
its dynamic response is determined by time to (dis)charge various
capacitances
MOS capacitances
Gate oxide capacitance (Cg): COX = per unit area,
for a transistor of width, W and length, L, the Cg=Cox.W.L
From current equation it is apparent that Cox should
be high or gate oxide thickness should be small
Gate capacitance consists of several components
Source and drain diffusions extend below the thin oxide (lateral
diffusion) giving rise to overlap capacitance
The Gate Capacitance
Polysilicon gate
Source
xd
n+
xd
Ld
W
Drain
n+
Gate-bulk
overlap
Top view
Gate oxide
tox
n+
L
n+
Cross section
❍ Source and drain diffusions extend below the thin oxide (lateral diffusion) giving rise to overlap capacitance
❍ Xd is constant for a technology and this capacitance is linear and has a fixed value CgsO = CgdO = CoxXdW =
CoW
Average Gate Capacitance
Gate to channel capacitance consists of Cgs, Cgd, and Cgb components. All
these components are nonlinear and their value depends on operation region
of the device.
Most important regions in digital design: saturation and cut-off
Gate Capacitance
G
G
CGC
D
S
Cut-off
No channel exists, CGC appears
between gate and body
G
CGC
CGC
D
S
Resistive
Inversion layer is formed acting as
conductor between source and
drain. Cgb=0 (body electrode is
shielded by channel). CGC
divided evenly between source
and drain
D
S
Saturation
Channel is pinched off. Cgd~0 &
Cgb~0
Most important regions in digital design: saturation and cut-off
Gate Capacitance
CG C
WLC ox
WLC ox
2
CGC B
C G CS = CG CD
VG S
Capacitance as a function of VGS
(with VDS = 0)
WLC ox
CG C
2WLC ox
CG CS
WLC ox
2
3
CGCD
0
VDS /( VG S-VT)
1
Capacitance as a function of the
degree of saturation
Diffusion Capacitance